[llvm] r187863 - Create a pattern for the "trap" instruction.

[Reed Kotler]

Author: rkotler
Date: Tue Aug  6 23:00:26 2013
New Revision: 187863

URL: http://llvm.org/viewvc/llvm-project?rev=187863&view=rev
Log:
Create a pattern for the "trap" instruction.


Added:
    llvm/trunk/test/CodeGen/Mips/trap1.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td?rev=187863&r1=187862&r2=187863&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td Tue Aug  6 23:00:26 2013
@@ -148,6 +148,20 @@ class FRR16<bits<5> _funct, dag outs, da
   let Inst{4-0}   = funct;
 }
 
+class FRRBreak16<dag outs, dag ins, string asmstr,
+                 list<dag> pattern, InstrItinClass itin>:
+  MipsInst16<outs, ins, asmstr, pattern, itin>
+{
+  bits<6>  Code;
+  bits<5>  funct;
+
+  let Opcode = 0b11101;
+  let funct  = 0b00101;
+
+  let Inst{10-5} = Code;
+  let Inst{4-0}   = funct;
+}
+
 //
 // For conversion functions.
 //

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=187863&r1=187862&r2=187863&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Tue Aug  6 23:00:26 2013
@@ -292,6 +292,11 @@ class FRR16_ins<bits<5> f, string asmstr
         !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
 }
 
+class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
+  FRRBreak16<(outs), (ins), asmstr, [], itin> {
+  let Code=0;
+}
+
 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
   FRR16<f, (outs), (ins  CPU16Regs:$rx, CPU16Regs:$ry),
         !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
@@ -574,6 +579,13 @@ def BnezRxImm16: FRI16_B_ins<0b00101, "b
 //
 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
 
+
+//
+//Format: BREAK immediate
+// Purpose: Breakpoint
+// To cause a Breakpoint exception.
+
+def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; 
 //
 // Format: BTEQZ offset MIPS16e
 // Purpose: Branch on T Equal to Zero (Extended)
@@ -1796,3 +1808,6 @@ def : Mips16Pat<(i32 (extloadi8   addr16
                 (LbuRxRyOffMemX16  addr16:$src)>;
 def : Mips16Pat<(i32 (extloadi16  addr16:$src)),
                 (LhuRxRyOffMemX16  addr16:$src)>;
+
+def: Mips16Pat<(trap), (Break16)>;
+

Added: llvm/trunk/test/CodeGen/Mips/trap1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/trap1.ll?rev=187863&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/trap1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/trap1.ll Tue Aug  6 23:00:26 2013
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s -check-prefix=pic
+
+declare void @llvm.trap()
+
+; Function Attrs: nounwind optsize readnone
+define i32 @main()  {
+entry:
+  call void @llvm.trap()
+  unreachable
+; pic: break 0
+  ret i32 0
+}
+