[llvm] r187804 - This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,

[Mihai Popa]

Author: mpopa
Date: Tue Aug  6 11:07:46 2013
New Revision: 187804

URL: http://llvm.org/viewvc/llvm-project?rev=187804&view=rev
Log:
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s
    llvm/trunk/test/MC/ARM/thumb2-pldw.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=187804&r1=187803&r2=187804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug  6 11:07:46 2013
@@ -1604,33 +1604,33 @@ multiclass T2Ipl<bits<1> write, bits<1>
 
     let DecoderMethod = "DecodeT2LoadShift";
   }
+}
 
-  // pci variant is very similar to i12, but supports negative offsets
-  // from the PC.
-  def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
-                 "\t$addr",
-                 [(ARMPreload (ARMWrapper tconstpool:$addr),
-                              (i32 write), (i32 instr))]>,
-                 Sched<[WritePreLd]> {
-    let Inst{31-25} = 0b1111100;
-    let Inst{24} = instr;
-    let Inst{22} = 0;
-    let Inst{21} = write;
-    let Inst{20} = 1;
-    let Inst{19-16} = 0b1111;
-    let Inst{15-12} = 0b1111;
+defm t2PLD    : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
+defm t2PLDW   : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
+defm t2PLI    : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
+
+// pci variant is very similar to i12, but supports negative offsets
+// from the PC. Only PLD and PLI have pci variants (not PLDW)
+class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
+               IIC_Preload, opc, "\t$addr", 
+               [(ARMPreload (ARMWrapper tconstpool:$addr),
+                (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
+  let Inst{31-25} = 0b1111100;
+  let Inst{24} = inst;
+  let Inst{22-20} = 0b001;
+  let Inst{19-16} = 0b1111;
+  let Inst{15-12} = 0b1111;
 
-    bits<13> addr;
-    let Inst{23}   = addr{12};   // add = (U == '1')
-    let Inst{11-0} = addr{11-0}; // imm12
+  bits<13> addr;
+  let Inst{23}   = addr{12};   // add = (U == '1')
+  let Inst{11-0} = addr{11-0}; // imm12
 
-    let DecoderMethod = "DecodeT2LoadLabel";
-  }
+  let DecoderMethod = "DecodeT2LoadLabel";
 }
 
-defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
-defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
-defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
+def t2PLDpci : T2Iplpci<0, "pld">,  Requires<[IsThumb2]>;
+def t2PLIpci : T2Iplpci<1, "pli">,  Requires<[IsThumb2,HasV7]>;
 
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
@@ -4425,9 +4425,6 @@ def : t2InstAlias<"add${p} $Rd, pc, $imm
 // PLD/PLDW/PLI with alternate literal form.
 def : t2InstAlias<"pld${p} $addr",
                   (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
-def : InstAlias<"pldw${p} $addr",
-                 (t2PLDWpci  t2ldr_pcrel_imm12:$addr, pred:$p)>,
-      Requires<[IsThumb2,HasV7,HasMP]>;
 def : InstAlias<"pli${p} $addr",
                  (t2PLIpci  t2ldr_pcrel_imm12:$addr, pred:$p)>,
       Requires<[IsThumb2,HasV7]>;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=187804&r1=187803&r2=187804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug  6 11:07:46 2013
@@ -3354,6 +3354,7 @@ static DecodeStatus DecodeT2LoadImm8(MCI
   switch (Inst.getOpcode()) {
   case ARM::t2PLDi8:
   case ARM::t2PLIi8:
+  case ARM::t2PLDWi8:
     break;
   default:
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@@ -3417,6 +3418,7 @@ static DecodeStatus DecodeT2LoadImm12(MC
 
   switch (Inst.getOpcode()) {
   case ARM::t2PLDi12:
+  case ARM::t2PLDWi12:
   case ARM::t2PLIi12:
     break;
   default:

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=187804&r1=187803&r2=187804&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug  6 11:07:46 2013
@@ -156,3 +156,8 @@ error: invalid operand for instruction
 @ CHECK-ERRORS: yield
 @ CHECK-ERRORS: ^
 
+ at ------------------------------------------------------------------------------
+@ PLDW required mp-extensions
+ at ------------------------------------------------------------------------------
+        pldw [r0, #4]
+@ CHECK-ERRORS: error: instruction requires: mp-extensions

Modified: llvm/trunk/test/MC/ARM/thumb2-pldw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-pldw.s?rev=187804&r1=187803&r2=187804&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2-pldw.s (original)
+++ llvm/trunk/test/MC/ARM/thumb2-pldw.s Tue Aug  6 11:07:46 2013
@@ -3,5 +3,5 @@
 @------------------------------------------------------------------------------
 @ PLD(literal)
 @------------------------------------------------------------------------------
-        pldw [pc,#-4095]
-@ CHECK: pldw [pc, #-4095]            @ encoding: [0x3f,0xf8,0xff,0xff]
+         pldw   [r0, #257]
+@ CHECK: pldw   [r0, #257]              @ encoding: [0xb0,0xf8,0x01,0xf1]