[llvm] r187749 - R600: Implement TargetLowering::getVectorIdxTy()

[Tom Stellard]

On Mon, Aug 05, 2013 at 10:22:08PM -0000, Tom Stellard wrote:
> Author: tstellar
> Date: Mon Aug  5 17:22:07 2013
> New Revision: 187749
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=187749&view=rev
> Log:
> R600: Implement TargetLowering::getVectorIdxTy()
> 
> We use MVT::i32 for the vector index type, because we use 32-bit
> operations to caculate offsets when dynamically indexing vectors.
> 
> Modified:
>     llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
>     llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
>     llvm/trunk/lib/Target/R600/SIInstructions.td
> 

I forgot to add the test case with this commit.  The test case was
committed in r187754.

-Tom

> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=187749&r1=187748&r2=187749&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Mon Aug  5 17:22:07 2013
> @@ -121,6 +121,15 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
>    }
>  }
>  
> +//===----------------------------------------------------------------------===//
> +// Target Information
> +//===----------------------------------------------------------------------===//
> +
> +MVT AMDGPUTargetLowering::getVectorIdxTy() const {
> +  return MVT::i32;
> +}
> +
> +
>  //===---------------------------------------------------------------------===//
>  // Target Properties
>  //===---------------------------------------------------------------------===//
> 
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=187749&r1=187748&r2=187749&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Mon Aug  5 17:22:07 2013
> @@ -51,7 +51,7 @@ public:
>  
>    virtual bool isFAbsFree(EVT VT) const;
>    virtual bool isFNegFree(EVT VT) const;
> -
> +  virtual MVT getVectorIdxTy() const;
>    virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
>                                bool isVarArg,
>                                const SmallVectorImpl<ISD::OutputArg> &Outs,
> 
> Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=187749&r1=187748&r2=187749&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
> +++ llvm/trunk/lib/Target/R600/SIInstructions.td Mon Aug  5 17:22:07 2013
> @@ -1792,25 +1792,25 @@ multiclass SI_INDIRECT_Pattern <ValueTyp
>  
>    // 1. Extract with offset
>    def : Pat<
> -    (vector_extract vt:$vec, (i64 (zext (add i32:$idx, imm:$off)))),
> +    (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
>      (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
>    >;
>  
>    // 2. Extract without offset
>    def : Pat<
> -    (vector_extract vt:$vec, (i64 (zext i32:$idx))),
> +    (vector_extract vt:$vec, i32:$idx),
>      (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
>    >;
>  
>    // 3. Insert with offset
>    def : Pat<
> -    (vector_insert vt:$vec, f32:$val, (i64 (zext (add i32:$idx, imm:$off)))),
> +    (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)),
>      (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
>    >;
>  
>    // 4. Insert without offset
>    def : Pat<
> -    (vector_insert vt:$vec, f32:$val, (i64 (zext i32:$idx))),
> +    (vector_insert vt:$vec, f32:$val, i32:$idx),
>      (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
>    >;
>  }
> 
> 
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