[llvm] r187701 - Clean up code for Mips16 large frame handling.
Reed Kotler
rkotler at mips.com
Sat Aug 3 18:13:25 PDT 2013
Author: rkotler
Date: Sat Aug 3 20:13:25 2013
New Revision: 187701
URL: http://llvm.org/viewvc/llvm-project?rev=187701&view=rev
Log:
Clean up code for Mips16 large frame handling.
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/test/CodeGen/Mips/largefr1.ll
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Sat Aug 3 20:13:25 2013
@@ -10,7 +10,7 @@
// This file contains the Mips16 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
-
+#include <stdio.h>
#include "Mips16InstrInfo.h"
#include "InstPrinter/MipsInstPrinter.h"
#include "MipsMachineFunction.h"
@@ -109,8 +109,9 @@ storeRegToStack(MachineBasicBlock &MBB,
if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
Opc = Mips::SwRxSpImmX16;
assert(Opc && "Register class not handled!");
- BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
+ BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
+ addFrameIndex(FI).addImm(Offset)
+ .addMemOperand(MMO);
}
void Mips16InstrInfo::
@@ -323,48 +324,88 @@ Mips16InstrInfo::loadImmediate(unsigned
//
RegScavenger rs;
int32_t lo = Imm & 0xFFFF;
- int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
NewImm = lo;
- unsigned Reg =0;
- unsigned SpReg = 0;
+ int Reg =0;
+ int SpReg = 0;
+
rs.enterBasicBlock(&MBB);
rs.forward(II);
//
+ // We need to know which registers can be used, in the case where there
+ // are not enough free registers. We exclude all registers that
+ // are used in the instruction that we are helping.
+ // // Consider all allocatable registers in the register class initially
+ BitVector Candidates =
+ RI.getAllocatableSet
+ (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
+ // Exclude all the registers being used by the instruction.
+ for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = II->getOperand(i);
+ if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
+ !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ Candidates.reset(MO.getReg());
+ }
+ //
+ // If the same register was used and defined in an instruction, then
+ // it will not be in the list of candidates.
+ //
+ // we need to analyze the instruction that we are helping.
+ // we need to know if it defines register x but register x is not
+ // present as an operand of the instruction. this tells
+ // whether the register is live before the instruction. if it's not
+ // then we don't need to save it in case there are no free registers.
+ //
+ int DefReg = 0;
+ for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = II->getOperand(i);
+ if (MO.isReg() && MO.isDef()) {
+ DefReg = MO.getReg();
+ break;
+ }
+ }
+ //
+ BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
+
+ Available &= Candidates;
+ //
// we use T0 for the first register, if we need to save something away.
// we use T1 for the second register, if we need to save something away.
//
unsigned FirstRegSaved =0, SecondRegSaved=0;
unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
- Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
- if (Reg == 0) {
- FirstRegSaved = Reg = Mips::V0;
- FirstRegSavedTo = Mips::T0;
- copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
+
+ Reg = Available.find_first();
+
+ if (Reg == -1) {
+ Reg = Candidates.find_first();
+ Candidates.reset(Reg);
+ if (DefReg != Reg) {
+ FirstRegSaved = Reg;
+ FirstRegSavedTo = Mips::T0;
+ copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
+ }
}
else
- rs.setUsed(Reg);
- BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
- BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
- addImm(16);
+ Available.reset(Reg);
+ BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
+ NewImm = 0;
if (FrameReg == Mips::SP) {
- SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
- if (SpReg == 0) {
- if (Reg != Mips::V1) {
- SecondRegSaved = SpReg = Mips::V1;
+ SpReg = Available.find_first();
+ if (SpReg == -1) {
+ SpReg = Candidates.find_first();
+ // Candidates.reset(SpReg); // not really needed
+ if (DefReg!= SpReg) {
+ SecondRegSaved = SpReg;
SecondRegSavedTo = Mips::T1;
}
- else {
- SecondRegSaved = SpReg = Mips::V0;
- SecondRegSavedTo = Mips::T0;
- }
- copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
+ if (SecondRegSaved)
+ copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
}
- else
- rs.setUsed(SpReg);
-
+ else
+ Available.reset(SpReg);
copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
- BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
+ BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
.addReg(Reg);
}
else
@@ -380,6 +421,22 @@ Mips16InstrInfo::loadImmediate(unsigned
return Reg;
}
+/// This function generates the sequence of instructions needed to get the
+/// result of adding register REG and immediate IMM.
+unsigned
+Mips16InstrInfo::basicLoadImmediate(
+ unsigned FrameReg,
+ int64_t Imm, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator II, DebugLoc DL,
+ unsigned &NewImm) const {
+ const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
+ MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
+ unsigned Reg = RegInfo.createVirtualRegister(RC);
+ BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
+ NewImm = 0;
+ return Reg;
+}
+
unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
@@ -415,3 +472,27 @@ void Mips16InstrInfo::BuildAddiuSpImm
const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
return new Mips16InstrInfo(TM);
}
+
+#include <stdio.h>
+bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
+ int64_t Amount) {
+ switch (Opcode) {
+ case Mips::LbRxRyOffMemX16:
+ case Mips::LbuRxRyOffMemX16:
+ case Mips::LhRxRyOffMemX16:
+ case Mips::LhuRxRyOffMemX16:
+ case Mips::SbRxRyOffMemX16:
+ case Mips::ShRxRyOffMemX16:
+ case Mips::LwRxRyOffMemX16:
+ case Mips::SwRxRyOffMemX16:
+ case Mips::SwRxSpImmX16:
+ case Mips::LwRxSpImmX16:
+ return isInt<16>(Amount);
+ case Mips::AddiuRxRyOffMemX16:
+ if ((Reg == Mips::PC) || (Reg == Mips::SP))
+ return isInt<16>(Amount);
+ return isInt<15>(Amount);
+ }
+ printf("Unexpected opcode %i \n", Opcode);
+ llvm_unreachable("unexpected Opcode in validImmediate");
+}
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h Sat Aug 3 20:13:25 2013
@@ -68,7 +68,7 @@ public:
// Adjust SP by FrameSize bytes. Save RA, S0, S1
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const;
+ MachineBasicBlock::iterator I) const;
// Adjust SP by FrameSize bytes. Restore RA, S0, S1
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
@@ -88,6 +88,13 @@ public:
MachineBasicBlock::iterator II, DebugLoc DL,
unsigned &NewImm) const;
+ unsigned basicLoadImmediate(unsigned FrameReg,
+ int64_t Imm, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator II, DebugLoc DL,
+ unsigned &NewImm) const;
+
+ static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
+
static bool validSpImm8(int offset) {
return ((offset & 7) == 0) && isInt<11>(offset);
}
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Sat Aug 3 20:13:25 2013
@@ -21,13 +21,13 @@ def addr16 :
// Address operand
def mem16 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
+ let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
let EncoderMethod = "getMemEncoding";
}
def mem16_ea : Operand<i32> {
let PrintMethod = "printMemOperandEA";
- let MIOperandInfo = (ops CPU16Regs, simm16);
+ let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
let EncoderMethod = "getMemEncoding";
}
@@ -187,6 +187,11 @@ class FEXT_RI16_SP_explicit_ins<bits<5>
FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
!strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
+class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
+ InstrItinClass itin>:
+ FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
+ !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
+
//
// EXT-RRI instruction format
//
@@ -437,7 +442,7 @@ def Constant32:
MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
def LwConstant32:
- MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
+ MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
@@ -1196,7 +1201,8 @@ def SwRxRyOffMemX16:
// Purpose: Store Word rx (SP-Relative)
// To store an SP-relative word to memory.
//
-def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
+def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
+ <0b11010, "sw", IIStore>, MayStore;
//
//
Modified: llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16RegisterInfo.cpp Sat Aug 3 20:13:25 2013
@@ -134,8 +134,8 @@ void Mips16RegisterInfo::eliminateFI(Mac
DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
- if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) ||
- ((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) {
+ if (!MI.isDebugValue() &&
+ !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = II->getDebugLoc();
unsigned NewImm;
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Sat Aug 3 20:13:25 2013
@@ -159,6 +159,8 @@ getReservedRegs(const MachineFunction &M
if (Subtarget.inMips16Mode()) {
Reserved.set(Mips::RA);
Reserved.set(Mips::RA_64);
+ Reserved.set(Mips::T0);
+ Reserved.set(Mips::T1);
}
// Reserve GP if small section is used.
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Sat Aug 3 20:13:25 2013
@@ -261,6 +261,13 @@ def CPU16Regs : RegisterClass<"Mips", [i
// Callee save
S0, S1)>;
+def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
+ // Return Values and Arguments
+ V0, V1, A0, A1, A2, A3,
+ // Callee save
+ S0, S1,
+ SP)>;
+
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
Modified: llvm/trunk/test/CodeGen/Mips/largefr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largefr1.ll?rev=187701&r1=187700&r2=187701&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largefr1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largefr1.ll Sat Aug 3 20:13:25 2013
@@ -1,5 +1,6 @@
; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=1
+
@i = common global i32 0, align 4
@j = common global i32 0, align 4
@.str = private unnamed_addr constant [8 x i8] c"%i %i \0A\00", align 1
@@ -24,20 +25,32 @@ define i32 @main() nounwind {
entry:
; 1-LABEL: main:
; 1: 1: .word -797992
-; 1: li ${{[0-9]+}}, 12
-; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
+; 1: lw ${{[0-9]+}}, 1f
+; 1: b 2f
+; 1: .align 2
+; 1: .word 800016
+
+; 1: b 2f
+; 1: .align 2
+; 1: .word 400016
+
+; 1: move ${{[0-9]+}}, $sp
; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 2: move $sp, ${{[0-9]+}}
-; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 1: li ${{[0-9]+}}, 6
-; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
+; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
+
+
+
+; 1: b 2f
+; 1: .align 2
+; 1: .word 400216
+
+; 1: move ${{[0-9]+}}, $sp
; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 2: move $sp, ${{[0-9]+}}
-; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 6800
-; 1: li ${{[0-9]+}}, 1
-; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
-; 2: li ${{[0-9]+}}, 34463
+; 1: lw ${{[0-9]+}}, 0(${{[0-9]+}})
+
+
+
+
%retval = alloca i32, align 4
%one = alloca [100000 x i32], align 4
%two = alloca [100000 x i32], align 4
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