[PATCH] R600: Set scheduling preference to Sched::Source

Andrew Trick atrick at apple.com
Fri Aug 2 11:03:28 PDT 2013 

On Aug 1, 2013, at 11:57 AM, Tom Stellard <tom at stellard.net> wrote:

> From: Tom Stellard <thomas.stellard at amd.com>
> 
> R600 doesn't need to do any scheduling on the SelectionDAG now that it
> has a very good MachineScheduler.  Also, using the VLIW SelectionDAG
> scheduler was having a major impact on compile times. For example with
> the phatk kernel here are the LLVM IR to machine code compile times:
> 
> With Sched::VLIW
> 
> Total Compile Time:                  1.4890 Seconds (User + System)
> SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System)
> 
> With Sched::Source
> 
> Total Compile Time:                  0.3330 Seconds (User + System)
> SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System)
> 
> The code ouput was identical with both schedulers.  This may not be true
> for all programs, but it gives me confidence that there won't be much
> reduction, if any, in code quality by using Sched::Source.

Great. There are more compile-time reductions planned in the near term: reducing the MI scheduler overhead, and bypassing SD scheduler completely.
-Andy

> ---
> lib/Target/R600/R600ISelLowering.cpp | 2 +-
> test/CodeGen/R600/and.ll             | 2 +-
> test/CodeGen/R600/fadd.ll            | 2 +-
> test/CodeGen/R600/fmul.ll            | 2 +-
> test/CodeGen/R600/fmul.v4f32.ll      | 2 +-
> test/CodeGen/R600/fsub.ll            | 2 +-
> test/CodeGen/R600/kcache-fold.ll     | 2 +-
> test/CodeGen/R600/setcc.ll           | 2 +-
> test/CodeGen/R600/sub.ll             | 2 +-
> 9 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index ce6ac89..a89875c 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -99,7 +99,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
> 
>   setBooleanContents(ZeroOrNegativeOneBooleanContent);
>   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
> -  setSchedulingPreference(Sched::VLIW);
> +  setSchedulingPreference(Sched::Source);
> }
> 
> MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
> diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll
> index 44c21bd..5fbc843 100644
> --- a/test/CodeGen/R600/and.ll
> +++ b/test/CodeGen/R600/and.ll
> @@ -19,7 +19,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
> }
> 
> ;EG-CHECK: @test4
> -;EG-CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
> index 97dbe44..2716958 100644
> --- a/test/CodeGen/R600/fadd.ll
> +++ b/test/CodeGen/R600/fadd.ll
> @@ -26,7 +26,7 @@ entry:
> }
> 
> ; CHECK: @fadd_v4f32
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
> index 6ef3a11..471b04e 100644
> --- a/test/CodeGen/R600/fmul.ll
> +++ b/test/CodeGen/R600/fmul.ll
> @@ -26,7 +26,7 @@ entry:
> }
> 
> ; CHECK: @fmul_v4f32
> -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/fmul.v4f32.ll b/test/CodeGen/R600/fmul.v4f32.ll
> index 74a58f7..7af6610 100644
> --- a/test/CodeGen/R600/fmul.v4f32.ll
> +++ b/test/CodeGen/R600/fmul.v4f32.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> 
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
> index 0fc5860..b45aaff 100644
> --- a/test/CodeGen/R600/fsub.ll
> +++ b/test/CodeGen/R600/fsub.ll
> @@ -26,7 +26,7 @@ entry:
> }
> 
> ; CHECK: @fsub_v4f32
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/kcache-fold.ll b/test/CodeGen/R600/kcache-fold.ll
> index 3d70e4b..8bdb050 100644
> --- a/test/CodeGen/R600/kcache-fold.ll
> +++ b/test/CodeGen/R600/kcache-fold.ll
> @@ -1,7 +1,7 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> 
> ; CHECK: @main1
> -; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}}
> +; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}
> define void @main1() {
> main_body:
>   %0 = load <4 x float> addrspace(8)* null
> diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
> index 992de70..1ca216c 100644
> --- a/test/CodeGen/R600/setcc.ll
> +++ b/test/CodeGen/R600/setcc.ll
> @@ -12,7 +12,7 @@ define void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %
> }
> 
> ; CHECK: @setcc_v4i32
> -; EG-CHECK-DAG: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll
> index 3bd4cb8..596400e 100644
> --- a/test/CodeGen/R600/sub.ll
> +++ b/test/CodeGen/R600/sub.ll
> @@ -19,7 +19,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
> }
> 
> ;EG-CHECK: @test4
> -;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -- 
> 1.7.11.4
> 
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