[llvm] r187632 - [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,

[Akira Hatanaka]

Author: ahatanak
Date: Thu Aug  1 18:14:16 2013
New Revision: 187632

URL: http://llvm.org/viewvc/llvm-project?rev=187632&view=rev
Log:
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=187632&r1=187631&r2=187632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Aug  1 18:14:16 2013
@@ -37,21 +37,15 @@ def immZExt6 : ImmLeaf<i32, [{return Imm
 let DecoderNamespace = "Mips64" in {
 
 multiclass Atomic2Ops64<PatFrag Op> {
-  def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
-             Requires<[NotN64, HasStdEnc]>;
-  def _P8  : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
-             Requires<[IsN64, HasStdEnc]> {
-    let isCodeGenOnly = 1;
-  }
+  def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
+  def _P8  : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
 }
 
 multiclass AtomicCmpSwap64<PatFrag Op>  {
   def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
              Requires<[NotN64, HasStdEnc]>;
   def _P8  : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
-             Requires<[IsN64, HasStdEnc]> {
-    let isCodeGenOnly = 1;
-  }
+             Requires<[IsN64, HasStdEnc]>;
 }
 }
 let usesCustomInserter = 1, Predicates = [HasStdEnc],
@@ -67,9 +61,9 @@ let usesCustomInserter = 1, Predicates =
 }
 
 /// Pseudo instructions for loading and storing accumulator registers.
-let isPseudo = 1 in {
-  defm LOAD_AC128  : LoadM<"load_ac128", ACRegs128>;
-  defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
+let isPseudo = 1, isCodeGenOnly = 1 in {
+  defm LOAD_AC128  : LoadM<"", ACRegs128>;
+  defm STORE_AC128 : StoreM<"", ACRegs128>;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=187632&r1=187631&r2=187632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Aug  1 18:14:16 2013
@@ -791,10 +791,7 @@ class Atomic2Ops<PatFrag Op, RegisterCla
 
 multiclass Atomic2Ops32<PatFrag Op> {
   def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
-  def _P8  : Atomic2Ops<Op, CPURegs, CPU64Regs>,
-             Requires<[IsN64, HasStdEnc]> {
-    let DecoderNamespace = "Mips64";
-  }
+  def _P8  : Atomic2Ops<Op, CPURegs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
 }
 
 // Atomic Compare & Swap.
@@ -806,9 +803,7 @@ multiclass AtomicCmpSwap32<PatFrag Op>
   def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
              Requires<[NotN64, HasStdEnc]>;
   def _P8  : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
-             Requires<[IsN64, HasStdEnc]> {
-    let DecoderNamespace = "Mips64";
-  }
+             Requires<[IsN64, HasStdEnc]>;
 }
 
 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
@@ -879,9 +874,9 @@ let usesCustomInserter = 1 in {
 }
 
 /// Pseudo instructions for loading and storing accumulator registers.
-let isPseudo = 1 in {
-  defm LOAD_AC64  : LoadM<"load_ac64", ACRegs>;
-  defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
+let isPseudo = 1, isCodeGenOnly = 1 in {
+  defm LOAD_AC64  : LoadM<"", ACRegs>;
+  defm STORE_AC64 : StoreM<"", ACRegs>;
 }
 
 //===----------------------------------------------------------------------===//