[llvm] r187490 - [SystemZ] Add RISBLG and RISBHG instruction definitions
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Wed Jul 31 04:17:35 PDT 2013
Author: rsandifo
Date: Wed Jul 31 06:17:35 2013
New Revision: 187490
URL: http://llvm.org/viewvc/llvm-project?rev=187490&view=rev
Log:
[SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Wed Jul 31 06:17:35 2013
@@ -867,6 +867,13 @@ let Defs = [CC] in {
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
}
+// Forms of RISBG that only affect one word of the destination register.
+// They do not set CC.
+def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
+ Requires<[FeatureHighWord]>;
+def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
+ Requires<[FeatureHighWord]>;
+
// Rotate second operand left and perform a logical operation with selected
// bits of the first operand.
let Defs = [CC] in {
Modified: llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td Wed Jul 31 06:17:35 2013
@@ -26,8 +26,13 @@ def FeatureLoadStoreOnCond : SystemZFeat
"Assume that the load/store-on-condition facility is installed"
>;
+def FeatureHighWord : SystemZFeature<
+ "high-word", "HighWord",
+ "Assume that the high-word facility is installed"
+>;
+
def : Processor<"z10", NoItineraries, []>;
def : Processor<"z196", NoItineraries,
- [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+ [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
def : Processor<"zEC12", NoItineraries,
- [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+ [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Wed Jul 31 06:17:35 2013
@@ -21,7 +21,7 @@ SystemZSubtarget::SystemZSubtarget(const
const std::string &CPU,
const std::string &FS)
: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
- HasLoadStoreOnCond(false), TargetTriple(TT) {
+ HasLoadStoreOnCond(false), HasHighWord(false), TargetTriple(TT) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "z10";
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Wed Jul 31 06:17:35 2013
@@ -29,6 +29,7 @@ class SystemZSubtarget : public SystemZG
protected:
bool HasDistinctOps;
bool HasLoadStoreOnCond;
+ bool HasHighWord;
private:
Triple TargetTriple;
@@ -46,6 +47,9 @@ public:
// Return true if the target has the load/store-on-condition facility.
bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
+ // Return true if the target has the high-word facility.
+ bool hasHighWord() const { return HasHighWord; }
+
// Return true if GV can be accessed using LARL for reloc model RM
// and code model CM.
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Wed Jul 31 06:17:35 2013
@@ -4957,6 +4957,48 @@
# CHECK: risbg %r4, %r5, 6, 7, 8
0xec 0x45 0x06 0x07 0x08 0x55
+# CHECK: risbhg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x5d
+
+# CHECK: risblg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x51
+
+# CHECK: risblg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x51
+
# CHECK: rnsbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x54
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Wed Jul 31 06:17:35 2013
@@ -75,6 +75,46 @@
locr %r0,%r0,16
#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risbhg %r0,%r0,256,0,0
+
+ risbhg %r0,%r0,0,0,-1
+ risbhg %r0,%r0,0,0,64
+ risbhg %r0,%r0,0,-1,0
+ risbhg %r0,%r0,0,256,0
+ risbhg %r0,%r0,-1,0,0
+ risbhg %r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risblg %r0,%r0,256,0,0
+
+ risblg %r0,%r0,0,0,-1
+ risblg %r0,%r0,0,0,64
+ risblg %r0,%r0,0,-1,0
+ risblg %r0,%r0,0,256,0
+ risblg %r0,%r0,-1,0,0
+ risblg %r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,-524289
#CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,524288
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Wed Jul 31 06:17:35 2013
@@ -2176,6 +2176,16 @@
risbg %r0,%r0,-1,0,0
risbg %r0,%r0,256,0,0
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risbhg %r1, %r2, 0, 0, 0
+
+ risbhg %r1, %r2, 0, 0, 0
+
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risblg %r1, %r2, 0, 0, 0
+
+ risblg %r1, %r2, 0, 0, 0
+
#CHECK: error: invalid operand
#CHECK: rnsbg %r0,%r0,0,0,-1
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=187490&r1=187489&r2=187490&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Wed Jul 31 06:17:35 2013
@@ -337,6 +337,38 @@
ork %r15,%r0,%r0
ork %r7,%r8,%r9
+#CHECK: risbhg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
+#CHECK: risbhg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
+#CHECK: risbhg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d]
+#CHECK: risbhg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x5d]
+
+ risbhg %r0,%r0,0,0,0
+ risbhg %r0,%r0,0,0,63
+ risbhg %r0,%r0,0,255,0
+ risbhg %r0,%r0,255,0,0
+ risbhg %r0,%r15,0,0,0
+ risbhg %r15,%r0,0,0,0
+ risbhg %r4,%r5,6,7,8
+
+#CHECK: risblg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51]
+#CHECK: risblg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x51]
+#CHECK: risblg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x51]
+#CHECK: risblg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x51]
+#CHECK: risblg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x51]
+
+ risblg %r0,%r0,0,0,0
+ risblg %r0,%r0,0,0,63
+ risblg %r0,%r0,0,255,0
+ risblg %r0,%r0,255,0,0
+ risblg %r0,%r15,0,0,0
+ risblg %r15,%r0,0,0,0
+ risblg %r4,%r5,6,7,8
+
#CHECK: sgrk %r0, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0x00]
#CHECK: sgrk %r0, %r0, %r15 # encoding: [0xb9,0xe9,0xf0,0x00]
#CHECK: sgrk %r0, %r15, %r0 # encoding: [0xb9,0xe9,0x00,0x0f]
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