Repost on commits list: Predication bug in AggressiveAntiDepBreaker?

[Verena Beckham]

Hi,

I wondered whether the AggressiveAntiDepBreaker can properly handle
predicated instructions.

At the end of PrescanInstruction the "DefIndices" array is updated with
the destination register without checking whether the instruction is
predicated. That shortens the live range: Later on, in HandleLastUse we
check whether the register IsLive, which considers only "KillIndices"
and "DefIndices", and therefore returns False for the interval between
the predicated instruction and any non-predicated read before it. So
that read is considered the last use.
In my example this leads to a register not being fully renamed everywhere.

I don't think a predicated write should count as a define.

The attached patch fixes this test case.

I'm afraid I'm working on a custom target and am not sufficiently 
familiar with other predicated architectures to write a test case that I 
can post. Maybe someone who has worked on predication can think of a test?

-- 
Verena Beckham

Vice President Engineering

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-------------- next part --------------
Index: AggressiveAntiDepBreaker.cpp
===================================================================
--- AggressiveAntiDepBreaker.cpp	(revision 186828)
+++ AggressiveAntiDepBreaker.cpp	(working copy)
@@ -399,7 +399,7 @@
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
     // Ignore KILLs and passthru registers for liveness...
-    if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
+    if (MI->isKill() || (PassthruRegs.count(Reg) != 0) || TII->isPredicated(MI))
       continue;
 
     // Update def for Reg and aliases.