R600: Scheduling support for VLIW5 gen

[Tom Stellard]

On Fri, Jul 26, 2013 at 07:00:27AM -0700, Vincent Lejeune wrote:
> Hi,
> 
> the first 2 patches in this serie make our scheduler properly support vliw5 hardware. Previously a vliw4 was always assumed;
> it was compatible with vliw5 scheduling but provided not optimal performance as the transALU slot was never used.
> 
> The last patch is a more general performance improvement that increase performance in Lightmark 2008, and the other one
> just make sure that there is never more than 4 litteral in a single ig instead of crashing at R600ControlFlowFinalizer.
> 
> Vincent

> From 13b24a905a9e61b354df4f24400fdc501d77fa51 Mon Sep 17 00:00:00 2001
> From: Vincent Lejeune <vljn at ovi.com>
> Date: Wed, 26 Jun 2013 18:32:52 +0200
> Subject: [PATCH 2/4] R600: Non vector only instruction can be scheduled on
>  trans unit
> 

It would be nice to have a test for this.  You should be able to write a
simple one with 5 fmul instructions.

Other than that the series is:

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

I still would like to test this on r600g with compute, so I'll let you
know when I've finished.

-Tom