[llvm] r187234 - [mips] Increase the number of floating point condition code registers to eight.

[Akira Hatanaka]

Author: ahatanak
Date: Fri Jul 26 14:03:48 2013
New Revision: 187234

URL: http://llvm.org/viewvc/llvm-project?rev=187234&view=rev
Log:
[mips] Increase the number of floating point condition code registers to eight.


Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=187234&r1=187233&r2=187234&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Fri Jul 26 14:03:48 2013
@@ -181,8 +181,9 @@ let Namespace = "Mips" in {
   foreach I = 0-31 in
   def FCR#I : MipsReg<#I, ""#I>;
 
-  // fcc0 register
-  def FCC0 : MipsReg<0, "fcc0">;
+  // FP condition code registers.
+  foreach I = 0-7 in
+  def FCC#I : MipsReg<#I, "fcc"#I>;
 
   // PC register
   def PC : Register<"pc">;
@@ -292,7 +293,8 @@ def CCR : RegisterClass<"Mips", [i32], 3
           Unallocatable;
 
 // FP condition code registers.
-def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
+def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
+          Unallocatable;
 
 // Hi/Lo Registers
 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;