[llvm] r186624 - Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change.
Stephen Lin
stephenwlin at gmail.com
Thu Jul 18 15:47:10 PDT 2013
Author: stephenwlin
Date: Thu Jul 18 17:47:09 2013
New Revision: 186624
URL: http://llvm.org/viewvc/llvm-project?rev=186624&view=rev
Log:
Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change.
All changes were made by the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
grep -q "^; *RUN: *llc.*debug" $NAME && continue
grep -q "^; *RUN:.*llvm-objdump" $NAME && continue
grep -q "^; *RUN: *opt.*" $NAME && continue
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
done
This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621.
Modified:
llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll
llvm/trunk/test/CodeGen/ARM/2012-11-14-subs_carry.ll
llvm/trunk/test/CodeGen/ARM/arm-modifier.ll
llvm/trunk/test/CodeGen/ARM/vcge.ll
llvm/trunk/test/CodeGen/ARM/vdup.ll
llvm/trunk/test/CodeGen/ARM/vldlane.ll
llvm/trunk/test/CodeGen/ARM/vmov.ll
llvm/trunk/test/CodeGen/ARM/vst2.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-22-SRet.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll
llvm/trunk/test/CodeGen/X86/2011-04-19-sclr-bb.ll
llvm/trunk/test/CodeGen/X86/2011-05-09-loaduse.ll
llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll
llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll
llvm/trunk/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
llvm/trunk/test/CodeGen/X86/2012-01-11-split-cv.ll
llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll
llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll
llvm/trunk/test/CodeGen/X86/2012-07-15-broadcastfold.ll
llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll
llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll
llvm/trunk/test/CodeGen/X86/StackColoring.ll
llvm/trunk/test/CodeGen/X86/WidenArith.ll
llvm/trunk/test/CodeGen/X86/atom-call-reg-indirect.ll
llvm/trunk/test/CodeGen/X86/avx-blend.ll
llvm/trunk/test/CodeGen/X86/avx-shuffle.ll
llvm/trunk/test/CodeGen/X86/avx-zext.ll
llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/blend-msb.ll
llvm/trunk/test/CodeGen/X86/chain_order.ll
llvm/trunk/test/CodeGen/X86/code_placement_align_all.ll
llvm/trunk/test/CodeGen/X86/pmovext.ll
llvm/trunk/test/CodeGen/X86/sandybridge-loads.ll
llvm/trunk/test/CodeGen/X86/sse41-blend.ll
llvm/trunk/test/CodeGen/X86/trunc-ext-ld-st.ll
llvm/trunk/test/CodeGen/X86/v8i1-masks.ll
llvm/trunk/test/CodeGen/X86/vec_cast2.ll
Modified: llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll Thu Jul 18 17:47:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
; rdar://12201387
-;CHECK: select_s_v_v
+;CHECK-LABEL: select_s_v_v:
;CHECK: it ne
;CHECK-NEXT: vmovne.i32
;CHECK: bx
Modified: llvm/trunk/test/CodeGen/ARM/2012-11-14-subs_carry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-11-14-subs_carry.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-11-14-subs_carry.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-11-14-subs_carry.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
-;CHECK: foo
+;CHECK-LABEL: foo:
;CHECK: adds
;CHECK-NEXT: adc
;CHECK-NEXT: bx
Modified: llvm/trunk/test/CodeGen/ARM/arm-modifier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-modifier.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-modifier.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Thu Jul 18 17:47:09 2013
@@ -60,7 +60,7 @@ ret void
define i64 @f4(i64* %val) nounwind {
entry:
- ;CHECK: f4
+ ;CHECK-LABEL: f4:
;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
ret i64 %0
Modified: llvm/trunk/test/CodeGen/ARM/vcge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcge.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcge.ll Thu Jul 18 17:47:09 2013
@@ -187,7 +187,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) n
; Floating-point comparisons against zero produce results with integer
; elements, not floating-point elements.
define void @test_vclez_fp() nounwind optsize {
-;CHECK: test_vclez_fp
+;CHECK-LABEL: test_vclez_fp:
;CHECK: vcle.f32
entry:
%0 = fcmp ole <4 x float> undef, zeroinitializer
Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vdup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vdup.ll Thu Jul 18 17:47:09 2013
@@ -263,7 +263,7 @@ define void @redundantVdup(<8 x i8>* %pt
}
define <4 x i32> @tdupi(i32 %x, i32 %y) {
-;CHECK: tdupi
+;CHECK-LABEL: tdupi:
;CHECK: vdup.32
%1 = insertelement <4 x i32> undef, i32 %x, i32 0
%2 = insertelement <4 x i32> %1, i32 %x, i32 1
@@ -273,7 +273,7 @@ define <4 x i32> @tdupi(i32 %x, i32 %y)
}
define <4 x float> @tdupf(float %x, float %y) {
-;CHECK: tdupf
+;CHECK-LABEL: tdupf:
;CHECK: vdup.32
%1 = insertelement <4 x float> undef, float %x, i32 0
%2 = insertelement <4 x float> %1, float %x, i32 1
@@ -285,7 +285,7 @@ define <4 x float> @tdupf(float %x, floa
; This test checks that when splatting an element from a vector into another,
; the value isn't moved out to GPRs first.
define <4 x i32> @tduplane(<4 x i32> %invec) {
-;CHECK: tduplane
+;CHECK-LABEL: tduplane:
;CHECK-NOT: vmov {{.*}}, d16[1]
;CHECK: vdup.32 {{.*}}, d16[1]
%in = extractelement <4 x i32> %invec, i32 1
Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Thu Jul 18 17:47:09 2013
@@ -502,7 +502,7 @@ declare %struct.__neon_float32x4x4_t @ll
; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
-;CHECK: test_qqqq_regsequence_subreg
+;CHECK-LABEL: test_qqqq_regsequence_subreg:
;CHECK: vld3.16
%tmp63 = extractvalue [6 x i64] %b, 5
%tmp64 = zext i64 %tmp63 to i128
Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmov.ll Thu Jul 18 17:47:09 2013
@@ -386,7 +386,7 @@ entry:
; rdar://10723651
define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
entry:
-;CHECK: any_extend
+;CHECK-LABEL: any_extend:
;CHECK: vmovl
%and.i186 = zext <4 x i1> %x to <4 x i32>
%add.i185 = sub <4 x i32> %and.i186, %y
Modified: llvm/trunk/test/CodeGen/ARM/vst2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst2.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst2.ll Thu Jul 18 17:47:09 2013
@@ -111,7 +111,7 @@ define void @vst2Qf(float* %A, <4 x floa
}
define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
-;CHECK: vst2update
+;CHECK-LABEL: vst2update:
;CHECK: vst2.16 {d16, d17}, [r0]!
%tmp1 = load <4 x i16>* %B
tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
@@ -120,7 +120,7 @@ define i8* @vst2update(i8* %out, <4 x i1
}
define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
-;CHECK: vst2update2
+;CHECK-LABEL: vst2update2:
;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
%tmp1 = load <4 x float>* %this
call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll Thu Jul 18 17:47:09 2013
@@ -63,10 +63,10 @@ entry:
define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
entry:
-;V8: test_select_int_fcc
+;V8-LABEL: test_select_int_fcc:
;V8: fcmps
;V8: {{fbe|fbne}}
-;V9: test_select_int_fcc
+;V9-LABEL: test_select_int_fcc:
;V9: fcmps
;V9-NOT: {{fbe|fbne}}
;V9: mov{{e|ne}} %fcc0
@@ -78,10 +78,10 @@ entry:
define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
entry:
-;V8: test_select_fp_fcc
+;V8-LABEL: test_select_fp_fcc:
;V8: fcmps
;V8: {{fbe|fbne}}
-;V9: test_select_fp_fcc
+;V9-LABEL: test_select_fp_fcc:
;V9: fcmps
;V9-NOT: {{fbe|fbne}}
;V9: fmovs{{e|ne}} %fcc0
@@ -92,10 +92,10 @@ entry:
define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
entry:
-;V8: test_select_dfp_fcc
+;V8-LABEL: test_select_dfp_fcc:
;V8: fcmpd
;V8: {{fbne|fbe}}
-;V9: test_select_dfp_fcc
+;V9-LABEL: test_select_dfp_fcc:
;V9: fcmpd
;V9-NOT: {{fbne|fbe}}
;V9: fmovd{{e|ne}} %fcc0
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Thu Jul 18 17:47:09 2013
@@ -6,12 +6,12 @@
define i8* @frameaddr() nounwind readnone {
entry:
-;V8: frameaddr
+;V8-LABEL: frameaddr:
;V8: save %sp, -96, %sp
;V8: jmp %i7+8
;V8: restore %g0, %fp, %o0
-;V9: frameaddr
+;V9-LABEL: frameaddr:
;V9: save %sp, -96, %sp
;V9: jmp %i7+8
;V9: restore %g0, %fp, %o0
@@ -21,13 +21,13 @@ entry:
define i8* @frameaddr2() nounwind readnone {
entry:
-;V8: frameaddr2
+;V8-LABEL: frameaddr2:
;V8: ta 3
;V8: ld [%fp+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
-;V9: frameaddr2
+;V9-LABEL: frameaddr2:
;V9: flushw
;V9: ld [%fp+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
@@ -42,10 +42,10 @@ declare i8* @llvm.frameaddress(i32) noun
define i8* @retaddr() nounwind readnone {
entry:
-;V8: retaddr
+;V8-LABEL: retaddr:
;V8: or %g0, %o7, {{.+}}
-;V9: retaddr
+;V9-LABEL: retaddr:
;V9: or %g0, %o7, {{.+}}
%0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -54,25 +54,25 @@ entry:
define i8* @retaddr2() nounwind readnone {
entry:
-;V8: retaddr2
+;V8-LABEL: retaddr2:
;V8: ta 3
;V8: ld [%fp+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
;V8: ld [{{.+}}+60], {{.+}}
-;V9: retaddr2
+;V9-LABEL: retaddr2:
;V9: flushw
;V9: ld [%fp+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
;V9: ld [{{.+}}+60], {{.+}}
-;V8LEAF: retaddr2
+;V8LEAF-LABEL: retaddr2:
;V8LEAF: ta 3
;V8LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
;V8LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
;V8LEAF: ld [%[[R1]]+60], {{.+}}
-;V9LEAF: retaddr2
+;V9LEAF-LABEL: retaddr2:
;V9LEAF: flushw
;V9LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
;V9LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll Thu Jul 18 17:47:09 2013
@@ -54,7 +54,7 @@ bb5:
define i32 @test_inlineasm(i32 %a) nounwind {
entry:
-;CHECK: test_inlineasm
+;CHECK-LABEL: test_inlineasm:
;CHECK: sethi
;CHECK: !NO_APP
;CHECK-NEXT: cmp
@@ -80,7 +80,7 @@ declare i32 @bar(i32)
define i32 @test_implicit_def() nounwind {
entry:
-;UNOPT: test_implicit_def
+;UNOPT-LABEL: test_implicit_def:
;UNOPT: call func
;UNOPT-NEXT: nop
%0 = tail call i32 @func(i32* undef) nounwind
@@ -89,7 +89,7 @@ entry:
define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {
entry:
-;CHECK: prevent_o7_in_call_delay_slot
+;CHECK-LABEL: prevent_o7_in_call_delay_slot:
;CHECK: add %i0, 2, %o5
;CHECK: add %i0, 3, %o7
;CHECK: add %o5, %o7, %o0
@@ -150,7 +150,7 @@ entry:
define i32 @restore_sethi(i32 %a) {
entry:
-;CHECK: restore_sethi
+;CHECK-LABEL: restore_sethi:
;CHECK-NOT: sethi 3
;CHECK: restore %g0, 3072, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
@@ -161,7 +161,7 @@ entry:
define i32 @restore_sethi_3bit(i32 %a) {
entry:
-;CHECK: restore_sethi_3bit
+;CHECK-LABEL: restore_sethi_3bit:
;CHECK: sethi 6
;CHECK-NOT: restore %g0, 6144, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
@@ -172,7 +172,7 @@ entry:
define i32 @restore_sethi_large(i32 %a) {
entry:
-;CHECK: restore_sethi_large
+;CHECK-LABEL: restore_sethi_large:
;CHECK: sethi 4000, %i0
;CHECK: restore %g0, %g0, %g0
%0 = tail call i32 @bar(i32 %a) nounwind
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll Thu Jul 18 17:47:09 2013
@@ -6,7 +6,7 @@
define i32 @test() nounwind {
entry:
-;CHECK: test
+;CHECK-LABEL: test:
;CHECK: st
;CHECK: st
;CHECK: st
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-22-SRet.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-22-SRet.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-22-SRet.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-22-SRet.ll Thu Jul 18 17:47:09 2013
@@ -4,7 +4,7 @@
define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind {
entry:
-;CHECK: make_foo
+;CHECK-LABEL: make_foo:
;CHECK: ld [%sp+64], {{.+}}
;CHECK: jmp %o7+12
%0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0
@@ -18,7 +18,7 @@ entry:
define i32 @test() nounwind {
entry:
-;CHECK: test
+;CHECK-LABEL: test:
;CHECK: st {{.+}}, [%sp+64]
;CHECK: call make_foo
;CHECK: unimp 12
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll Thu Jul 18 17:47:09 2013
@@ -259,7 +259,7 @@ define i32 @f5(i32 %a) {
}
define i32 @f6(i32 %a) {
-;CHECK: f6
+;CHECK-LABEL: f6:
;CHECK: movw r0, #65535
%tmp = add i32 0, 65535
ret i32 %tmp
Modified: llvm/trunk/test/CodeGen/X86/2011-04-19-sclr-bb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-04-19-sclr-bb.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-04-19-sclr-bb.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-04-19-sclr-bb.ll Thu Jul 18 17:47:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
; Make sure that values of illegal types are not scalarized between basic blocks.
-;CHECK: test
+;CHECK-LABEL: test:
;CHECK-NOT: pinsrw
;CHECK-NOT: pextrb
;CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/2011-05-09-loaduse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-09-loaduse.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-05-09-loaduse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-05-09-loaduse.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
-;CHECK: test
+;CHECK-LABEL: test:
;CHECK-not: pshufd
;CHECK: ret
define float @test(<4 x float>* %A) nounwind {
Modified: llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll Thu Jul 18 17:47:09 2013
@@ -2,7 +2,7 @@
target triple = "x86_64-unknown-linux-gnu"
-;CHECK: ltstore
+;CHECK-LABEL: ltstore:
;CHECK: movq
;CHECK: movq
;CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
-;CHECK: addXX_test
+;CHECK-LABEL: addXX_test:
;CHECK: padd
;CHECK: ret
@@ -10,7 +10,7 @@ define <16 x i8> @addXX_test(<16 x i8> %
ret <16 x i8> %b
}
-;CHECK: instcombine_test
+;CHECK-LABEL: instcombine_test:
;CHECK: padd
;CHECK: ret
define <16 x i8> @instcombine_test(<16 x i8> %a) {
Modified: llvm/trunk/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll Thu Jul 18 17:47:09 2013
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gn
; 0x1 means that we only look at the first bit.
;CHECK: 0x1
-;CHECK: ui_to_fp_conv
+;CHECK-LABEL: ui_to_fp_conv:
;CHECK: ret
define void @ui_to_fp_conv(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
allocas:
Modified: llvm/trunk/test/CodeGen/X86/2012-01-11-split-cv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-01-11-split-cv.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-01-11-split-cv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-01-11-split-cv.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
-;CHECK: add18i16
+;CHECK-LABEL: add18i16:
define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind {
;CHECK: vmovaps
%b = load <18 x i16>* %bp, align 16
Modified: llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s
-;CHECK: vcast
+;CHECK-LABEL: vcast:
define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {
;CHECK: pmovzxdq
;CHECK: pmovzxdq
Modified: llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll Thu Jul 18 17:47:09 2013
@@ -13,7 +13,7 @@ entry:
}
; Make sure that we store a 64bit value, even on 32bit systems.
-;CHECK: store_64
+;CHECK-LABEL: store_64:
define void @store_64(<2 x i32>* %ptr) {
BB:
store <2 x i32> zeroinitializer, <2 x i32>* %ptr
@@ -22,7 +22,7 @@ BB:
;CHECK: ret
}
-;CHECK: load_64
+;CHECK-LABEL: load_64:
define <2 x i32> @load_64(<2 x i32>* %ptr) {
BB:
%t = load <2 x i32>* %ptr
Modified: llvm/trunk/test/CodeGen/X86/2012-07-15-broadcastfold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-07-15-broadcastfold.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-07-15-broadcastfold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-07-15-broadcastfold.ll Thu Jul 18 17:47:09 2013
@@ -2,7 +2,7 @@
declare x86_fastcallcc i64 @barrier()
-;CHECK: bcast_fold
+;CHECK-LABEL: bcast_fold:
;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]]
;CHECK: barrier
;CHECK: vbroadcastss [[SPILLED]], %ymm0
Modified: llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-1-10-buildvector.ll Thu Jul 18 17:47:09 2013
@@ -3,7 +3,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
target triple = "i686-pc-win32"
-;CHECK: bad_cast
+;CHECK-LABEL: bad_cast:
define void @bad_cast() {
entry:
%vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
@@ -14,7 +14,7 @@ entry:
}
-;CHECK: bad_insert
+;CHECK-LABEL: bad_insert:
define void @bad_insert(i32 %t) {
entry:
;CHECK: vpinsrd
Modified: llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll (original)
+++ llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll Thu Jul 18 17:47:09 2013
@@ -147,7 +147,7 @@ define void @merge_nonconst_store(i32 %c
}
-;CHECK: merge_loads_i16
+;CHECK-LABEL: merge_loads_i16:
; load:
;CHECK: movw
; store:
@@ -181,7 +181,7 @@ define void @merge_loads_i16(i32 %count,
}
; The loads and the stores are interleved. Can't merge them.
-;CHECK: no_merge_loads
+;CHECK-LABEL: no_merge_loads:
;CHECK: movb
;CHECK: movb
;CHECK: movb
@@ -215,7 +215,7 @@ a4:
}
-;CHECK: merge_loads_integer
+;CHECK-LABEL: merge_loads_integer:
; load:
;CHECK: movq
; store:
@@ -249,7 +249,7 @@ define void @merge_loads_integer(i32 %co
}
-;CHECK: merge_loads_vector
+;CHECK-LABEL: merge_loads_vector:
; load:
;CHECK: movups
; store:
@@ -290,7 +290,7 @@ block4:
ret void
}
-;CHECK: merge_loads_no_align
+;CHECK-LABEL: merge_loads_no_align:
; load:
;CHECK: movl
;CHECK: movl
Modified: llvm/trunk/test/CodeGen/X86/StackColoring.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/StackColoring.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/StackColoring.ll (original)
+++ llvm/trunk/test/CodeGen/X86/StackColoring.ll Thu Jul 18 17:47:09 2013
@@ -297,8 +297,8 @@ bb3:
}
-;YESCOLOR: multi_region_bb
-;NOCOLOR: multi_region_bb
+;YESCOLOR-LABEL: multi_region_bb:
+;NOCOLOR-LABEL: multi_region_bb:
define void @multi_region_bb() nounwind ssp {
entry:
%A.i1 = alloca [100 x i32], align 4
@@ -353,9 +353,9 @@ bb3:
; Regression test for PR15707. %buf1 and %buf2 should not be merged
; in this test case.
-;YESCOLOR: myCall_pr15707
+;YESCOLOR-LABEL: myCall_pr15707:
;YESCOLOR: subq $200008, %rsp
-;NOCOLOR: myCall_pr15707
+;NOCOLOR-LABEL: myCall_pr15707:
;NOCOLOR: subq $200008, %rsp
define void @myCall_pr15707() {
%buf1 = alloca i8, i32 100000, align 16
@@ -374,8 +374,8 @@ define void @myCall_pr15707() {
; Check that we don't assert and crash even when there are allocas
; outside the declared lifetime regions.
-;YESCOLOR: bad_range
-;NOCOLOR: bad_range
+;YESCOLOR-LABEL: bad_range:
+;NOCOLOR-LABEL: bad_range:
define void @bad_range() nounwind ssp {
entry:
%A.i1 = alloca [100 x i32], align 4
@@ -400,8 +400,8 @@ block2:
; Check that we don't assert and crash even when there are usages
; of allocas which do not read or write outside the declared lifetime regions.
-;YESCOLOR: shady_range
-;NOCOLOR: shady_range
+;YESCOLOR-LABEL: shady_range:
+;NOCOLOR-LABEL: shady_range:
%struct.Klass = type { i32, i32 }
Modified: llvm/trunk/test/CodeGen/X86/WidenArith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/WidenArith.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/WidenArith.ll (original)
+++ llvm/trunk/test/CodeGen/X86/WidenArith.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
-;CHECK: test
+;CHECK-LABEL: test:
;CHECK: vaddps
;CHECK: vmulps
;CHECK: vsubps
Modified: llvm/trunk/test/CodeGen/X86/atom-call-reg-indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atom-call-reg-indirect.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atom-call-reg-indirect.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atom-call-reg-indirect.ll Thu Jul 18 17:47:09 2013
@@ -8,7 +8,7 @@
%class.A = type { i32 (...)** }
define i32 @test1() #0 {
- ;ATOM: test1
+ ;ATOM-LABEL: test1:
entry:
%call = tail call %class.A* @_Z3facv()
%0 = bitcast %class.A* %call to void (%class.A*)***
@@ -30,7 +30,7 @@ declare %class.A* @_Z3facv() #1
@p = external global void (i32)**
define i32 @test2() #0 {
- ;ATOM: test2
+ ;ATOM-LABEL: test2:
entry:
%0 = load void (i32)*** @p, align 8
%1 = load void (i32)** %0, align 8
Modified: llvm/trunk/test/CodeGen/X86/avx-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Thu Jul 18 17:47:09 2013
@@ -2,7 +2,7 @@
; AVX128 tests:
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
;CHECK: vblendvps
;CHECK: ret
define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -11,7 +11,7 @@ define <4 x float> @vsel_float(<4 x floa
}
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
;CHECK: vblendvps
;CHECK: ret
define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -20,7 +20,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1
}
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
;CHECK: vblendvpd
;CHECK: ret
define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
@@ -29,7 +29,7 @@ define <2 x double> @vsel_double(<2 x do
}
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
;CHECK: vblendvpd
;CHECK: ret
define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
@@ -38,7 +38,7 @@ define <2 x i64> @vsel_i64(<2 x i64> %v1
}
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
;CHECK: vpblendvb
;CHECK: ret
define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -50,7 +50,7 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1,
; AVX256 tests:
-;CHECK: vsel_float8
+;CHECK-LABEL: vsel_float8:
;CHECK: vblendvps
;CHECK: ret
define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
@@ -58,7 +58,7 @@ define <8 x float> @vsel_float8(<8 x flo
ret <8 x float> %vsel
}
-;CHECK: vsel_i328
+;CHECK-LABEL: vsel_i328:
;CHECK: vblendvps
;CHECK: ret
define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
@@ -66,7 +66,7 @@ define <8 x i32> @vsel_i328(<8 x i32> %v
ret <8 x i32> %vsel
}
-;CHECK: vsel_double8
+;CHECK-LABEL: vsel_double8:
;CHECK: vblendvpd
;CHECK: ret
define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
@@ -74,7 +74,7 @@ define <8 x double> @vsel_double8(<8 x d
ret <8 x double> %vsel
}
-;CHECK: vsel_i648
+;CHECK-LABEL: vsel_i648:
;CHECK: vblendvpd
;CHECK: ret
define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Thu Jul 18 17:47:09 2013
@@ -220,7 +220,7 @@ define <16 x i16> @narrow(<16 x i16> %a)
ret <16 x i16> %t
}
-;CHECK: test17
+;CHECK-LABEL: test17:
;CHECK-NOT: vinsertf128
;CHECK: ret
define <8 x float> @test17(<4 x float> %y) {
Modified: llvm/trunk/test/CodeGen/X86/avx-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-zext.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-zext.ll Thu Jul 18 17:47:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_8i16_to_8i32
+;CHECK-LABEL: zext_8i16_to_8i32:
;CHECK: vpunpckhwd
;CHECK: ret
@@ -10,7 +10,7 @@ define <8 x i32> @zext_8i16_to_8i32(<8 x
}
define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_4i32_to_4i64
+;CHECK-LABEL: zext_4i32_to_4i64:
;CHECK: vpunpckhdq
;CHECK: ret
@@ -19,7 +19,7 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x
}
define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
-;CHECK: zext_8i8_to_8i32
+;CHECK-LABEL: zext_8i8_to_8i32:
;CHECK: vpunpckhwd
;CHECK: vpmovzxwd
;CHECK: vinsertf128
Modified: llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll Thu Jul 18 17:47:09 2013
@@ -259,7 +259,7 @@ define <4 x double> @_inreg3(double %sca
ret <4 x double> %wide
}
-;CHECK: _inreg8xfloat
+;CHECK-LABEL: _inreg8xfloat:
;CHECK: vbroadcastss
;CHECK: ret
define <8 x float> @_inreg8xfloat(<8 x float> %a) {
@@ -267,7 +267,7 @@ define <8 x float> @_inreg8xfloat(<8 x
ret <8 x float> %b
}
-;CHECK: _inreg4xfloat
+;CHECK-LABEL: _inreg4xfloat:
;CHECK: vbroadcastss
;CHECK: ret
define <4 x float> @_inreg4xfloat(<4 x float> %a) {
@@ -275,7 +275,7 @@ define <4 x float> @_inreg4xfloat(<4 x
ret <4 x float> %b
}
-;CHECK: _inreg16xi16
+;CHECK-LABEL: _inreg16xi16:
;CHECK: vpbroadcastw
;CHECK: ret
define <16 x i16> @_inreg16xi16(<16 x i16> %a) {
@@ -283,7 +283,7 @@ define <16 x i16> @_inreg16xi16(<16 x
ret <16 x i16> %b
}
-;CHECK: _inreg8xi16
+;CHECK-LABEL: _inreg8xi16:
;CHECK: vpbroadcastw
;CHECK: ret
define <8 x i16> @_inreg8xi16(<8 x i16> %a) {
@@ -292,7 +292,7 @@ define <8 x i16> @_inreg8xi16(<8 x i16
}
-;CHECK: _inreg4xi64
+;CHECK-LABEL: _inreg4xi64:
;CHECK: vpbroadcastq
;CHECK: ret
define <4 x i64> @_inreg4xi64(<4 x i64> %a) {
@@ -300,7 +300,7 @@ define <4 x i64> @_inreg4xi64(<4 x i64
ret <4 x i64> %b
}
-;CHECK: _inreg2xi64
+;CHECK-LABEL: _inreg2xi64:
;CHECK: vpbroadcastq
;CHECK: ret
define <2 x i64> @_inreg2xi64(<2 x i64> %a) {
@@ -308,7 +308,7 @@ define <2 x i64> @_inreg2xi64(<2 x i64
ret <2 x i64> %b
}
-;CHECK: _inreg4xdouble
+;CHECK-LABEL: _inreg4xdouble:
;CHECK: vbroadcastsd
;CHECK: ret
define <4 x double> @_inreg4xdouble(<4 x double> %a) {
@@ -316,7 +316,7 @@ define <4 x double> @_inreg4xdouble(<4
ret <4 x double> %b
}
-;CHECK: _inreg2xdouble
+;CHECK-LABEL: _inreg2xdouble:
;CHECK: vpbroadcastq
;CHECK: ret
define <2 x double> @_inreg2xdouble(<2 x double> %a) {
@@ -324,7 +324,7 @@ define <2 x double> @_inreg2xdouble(<2
ret <2 x double> %b
}
-;CHECK: _inreg8xi32
+;CHECK-LABEL: _inreg8xi32:
;CHECK: vpbroadcastd
;CHECK: ret
define <8 x i32> @_inreg8xi32(<8 x i32> %a) {
@@ -332,7 +332,7 @@ define <8 x i32> @_inreg8xi32(<8 x i32
ret <8 x i32> %b
}
-;CHECK: _inreg4xi32
+;CHECK-LABEL: _inreg4xi32:
;CHECK: vpbroadcastd
;CHECK: ret
define <4 x i32> @_inreg4xi32(<4 x i32> %a) {
@@ -340,7 +340,7 @@ define <4 x i32> @_inreg4xi32(<4 x i32
ret <4 x i32> %b
}
-;CHECK: _inreg32xi8
+;CHECK-LABEL: _inreg32xi8:
;CHECK: vpbroadcastb
;CHECK: ret
define <32 x i8> @_inreg32xi8(<32 x i8> %a) {
@@ -348,7 +348,7 @@ define <32 x i8> @_inreg32xi8(<32 x i8
ret <32 x i8> %b
}
-;CHECK: _inreg16xi8
+;CHECK-LABEL: _inreg16xi8:
;CHECK: vpbroadcastb
;CHECK: ret
define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
Modified: llvm/trunk/test/CodeGen/X86/blend-msb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/blend-msb.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/blend-msb.ll (original)
+++ llvm/trunk/test/CodeGen/X86/blend-msb.ll Thu Jul 18 17:47:09 2013
@@ -4,7 +4,7 @@
; In this test we check that sign-extend of the mask bit is performed by
; shifting the needed bit to the MSB, and not using shl+sra.
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
;CHECK: movl $-2147483648
;CHECK-NEXT: movd
;CHECK-NEXT: blendvps
@@ -14,7 +14,7 @@ define <4 x float> @vsel_float(<4 x floa
ret <4 x float> %vsel
}
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
;CHECK: movl $-2147483648
;CHECK-NEXT: movd
;CHECK-NEXT: blendvps
@@ -28,7 +28,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1,
; We do not have native support for v8i16 blends and we have to use the
; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
; reduce the mask in this case.
-;CHECK: vsel_8xi16
+;CHECK-LABEL: vsel_8xi16:
;CHECK: psllw
;CHECK: psraw
;CHECK: pblendvb
Modified: llvm/trunk/test/CodeGen/X86/chain_order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/chain_order.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/chain_order.ll (original)
+++ llvm/trunk/test/CodeGen/X86/chain_order.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-linux | FileCheck %s
-;CHECK: cftx020
+;CHECK-LABEL: cftx020:
;CHECK: vmovsd (%rdi), %xmm{{.*}}
;CHECK: vmovsd 16(%rdi), %xmm{{.*}}
;CHECK: vmovhpd 8(%rdi), %xmm{{.*}}
Modified: llvm/trunk/test/CodeGen/X86/code_placement_align_all.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code_placement_align_all.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/code_placement_align_all.ll (original)
+++ llvm/trunk/test/CodeGen/X86/code_placement_align_all.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s
-;CHECK: foo
+;CHECK-LABEL: foo:
;CHECK: .align 65536, 0x90
;CHECK: .align 65536, 0x90
;CHECK: .align 65536, 0x90
Modified: llvm/trunk/test/CodeGen/X86/pmovext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pmovext.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pmovext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pmovext.ll Thu Jul 18 17:47:09 2013
@@ -2,7 +2,7 @@
; rdar://11897677
-;CHECK: intrin_pmov
+;CHECK-LABEL: intrin_pmov:
;CHECK: pmovzxbw (%{{.*}}), %xmm0
;CHECK-NEXT: movdqu
;CHECK-NEXT: ret
Modified: llvm/trunk/test/CodeGen/X86/sandybridge-loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sandybridge-loads.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sandybridge-loads.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sandybridge-loads.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
-;CHECK: wideloads
+;CHECK-LABEL: wideloads:
;CHECK: vmovaps
;CHECK: vinsertf128
;CHECK: vmovaps
Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
;CHECK: blendvps
;CHECK: ret
define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -9,7 +9,7 @@ define <4 x float> @vsel_float(<4 x floa
}
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
;CHECK: blendvps
;CHECK: ret
define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
@@ -17,7 +17,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1,
ret <4 x i8> %vsel
}
-;CHECK: vsel_4xi16
+;CHECK-LABEL: vsel_4xi16:
;CHECK: blendvps
;CHECK: ret
define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
@@ -26,7 +26,7 @@ define <4 x i16> @vsel_4xi16(<4 x i16> %
}
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
;CHECK: blendvps
;CHECK: ret
define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -35,7 +35,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1
}
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
;CHECK: blendvpd
;CHECK: ret
define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
@@ -44,7 +44,7 @@ define <4 x double> @vsel_double(<4 x do
}
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
;CHECK: blendvpd
;CHECK: ret
define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
@@ -53,7 +53,7 @@ define <4 x i64> @vsel_i64(<4 x i64> %v1
}
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
;CHECK: pblendvb
;CHECK: ret
define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
Modified: llvm/trunk/test/CodeGen/X86/trunc-ext-ld-st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/trunc-ext-ld-st.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/trunc-ext-ld-st.ll (original)
+++ llvm/trunk/test/CodeGen/X86/trunc-ext-ld-st.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s
-;CHECK: load_2_i8
+;CHECK-LABEL: load_2_i8:
; A single 16-bit load
;CHECK: pmovzxbq
;CHECK: paddq
@@ -16,7 +16,7 @@ define void @load_2_i8(<2 x i8>* %A) {
ret void
}
-;CHECK: load_2_i16
+;CHECK-LABEL: load_2_i16:
; Read 32-bits
;CHECK: pmovzxwq
;CHECK: paddq
@@ -30,7 +30,7 @@ define void @load_2_i16(<2 x i16>* %A)
ret void
}
-;CHECK: load_2_i32
+;CHECK-LABEL: load_2_i32:
;CHECK: pmovzxdq
;CHECK: paddq
;CHECK: pshufd
@@ -42,7 +42,7 @@ define void @load_2_i32(<2 x i32>* %A)
ret void
}
-;CHECK: load_4_i8
+;CHECK-LABEL: load_4_i8:
;CHECK: pmovzxbd
;CHECK: paddd
;CHECK: pshufb
@@ -54,7 +54,7 @@ define void @load_4_i8(<4 x i8>* %A) {
ret void
}
-;CHECK: load_4_i16
+;CHECK-LABEL: load_4_i16:
;CHECK: pmovzxwd
;CHECK: paddd
;CHECK: pshufb
@@ -66,7 +66,7 @@ define void @load_4_i16(<4 x i16>* %A)
ret void
}
-;CHECK: load_8_i8
+;CHECK-LABEL: load_8_i8:
;CHECK: pmovzxbw
;CHECK: paddw
;CHECK: pshufb
Modified: llvm/trunk/test/CodeGen/X86/v8i1-masks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/v8i1-masks.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/v8i1-masks.ll (original)
+++ llvm/trunk/test/CodeGen/X86/v8i1-masks.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
-;CHECK: and_masks
+;CHECK-LABEL: and_masks:
;CHECK: vmovaps
;CHECK: vcmpltp
;CHECK: vcmpltp
Modified: llvm/trunk/test/CodeGen/X86/vec_cast2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_cast2.ll?rev=186624&r1=186623&r2=186624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_cast2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_cast2.ll Thu Jul 18 17:47:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
-;CHECK: foo1_8
+;CHECK-LABEL: foo1_8:
;CHECK: vcvtdq2ps
;CHECK: ret
define <8 x float> @foo1_8(<8 x i8> %src) {
@@ -8,7 +8,7 @@ define <8 x float> @foo1_8(<8 x i8> %src
ret <8 x float> %res
}
-;CHECK: foo1_4
+;CHECK-LABEL: foo1_4:
;CHECK: vcvtdq2ps
;CHECK: ret
define <4 x float> @foo1_4(<4 x i8> %src) {
@@ -16,7 +16,7 @@ define <4 x float> @foo1_4(<4 x i8> %src
ret <4 x float> %res
}
-;CHECK: foo2_8
+;CHECK-LABEL: foo2_8:
;CHECK: vcvtdq2ps
;CHECK: ret
define <8 x float> @foo2_8(<8 x i8> %src) {
@@ -24,7 +24,7 @@ define <8 x float> @foo2_8(<8 x i8> %src
ret <8 x float> %res
}
-;CHECK: foo2_4
+;CHECK-LABEL: foo2_4:
;CHECK: vcvtdq2ps
;CHECK: ret
define <4 x float> @foo2_4(<4 x i8> %src) {
@@ -32,14 +32,14 @@ define <4 x float> @foo2_4(<4 x i8> %src
ret <4 x float> %res
}
-;CHECK: foo3_8
+;CHECK-LABEL: foo3_8:
;CHECK: vcvttps2dq
;CHECK: ret
define <8 x i8> @foo3_8(<8 x float> %src) {
%res = fptosi <8 x float> %src to <8 x i8>
ret <8 x i8> %res
}
-;CHECK: foo3_4
+;CHECK-LABEL: foo3_4:
;CHECK: vcvttps2dq
;CHECK: ret
define <4 x i8> @foo3_4(<4 x float> %src) {
More information about the llvm-commits
mailing list