[llvm] r186616 - R600/SI: Fix crash with VSELECT

[Tom Stellard]

Author: tstellar
Date: Thu Jul 18 16:43:53 2013
New Revision: 186616

URL: http://llvm.org/viewvc/llvm-project?rev=186616&view=rev
Log:
R600/SI: Fix crash with VSELECT

https://bugs.freedesktop.org/show_bug.cgi?id=66175

Modified:
    llvm/trunk/lib/Target/R600/SIISelLowering.cpp
    llvm/trunk/lib/Target/R600/SIInstructions.td
    llvm/trunk/test/CodeGen/R600/vselect.ll

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=186616&r1=186615&r2=186616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Thu Jul 18 16:43:53 2013
@@ -34,6 +34,9 @@ SITargetLowering::SITargetLowering(Targe
   addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
 
+  addRegisterClass(MVT::v2i1, &AMDGPU::VReg_64RegClass);
+  addRegisterClass(MVT::v4i1, &AMDGPU::VReg_128RegClass);
+
   addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
   addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
   addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
@@ -72,6 +75,9 @@ SITargetLowering::SITargetLowering(Targe
 
   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
 
+  setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
+  setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
+
   setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@@ -318,7 +324,10 @@ MachineBasicBlock * SITargetLowering::Em
 }
 
 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
-  return MVT::i1;
+  if (!VT.isVector()) {
+    return MVT::i1;
+  }
+  return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
 }
 
 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {

Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=186616&r1=186615&r2=186616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Thu Jul 18 16:43:53 2013
@@ -1487,6 +1487,9 @@ def : BitConvert <f64, i64, VReg_64>;
 def : BitConvert <v2f32, v2i32, VReg_64>;
 def : BitConvert <v2i32, v2f32, VReg_64>;
 
+def : BitConvert <v4f32, v4i32, VReg_128>;
+def : BitConvert <v4i32, v4f32, VReg_128>;
+
 /********** =================== **********/
 /********** Src & Dst modifiers **********/
 /********** =================== **********/

Modified: llvm/trunk/test/CodeGen/R600/vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/vselect.ll?rev=186616&r1=186615&r2=186616&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/vselect.ll (original)
+++ llvm/trunk/test/CodeGen/R600/vselect.ll Thu Jul 18 16:43:53 2013
@@ -1,9 +1,14 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
 
 ;EG-CHECK: @test_select_v2i32
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
+;SI-CHECK: @test_select_v2i32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+
 define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
 entry:
   %0 = load <2 x i32> addrspace(1)* %in0
@@ -18,6 +23,10 @@ entry:
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
+;SI-CHECK: @test_select_v2f32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+
 define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
 entry:
   %0 = load <2 x float> addrspace(1)* %in0
@@ -34,6 +43,12 @@ entry:
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
+;SI-CHECK: @test_select_v4i32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+
 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
 entry:
   %0 = load <4 x i32> addrspace(1)* %in0