[llvm] r186507 - Implement eret and deret(return from exception) instructions for Mips. Test examples are given.

[Vladimir Medic]

Author: vmedic
Date: Wed Jul 17 09:05:19 2013
New Revision: 186507

URL: http://llvm.org/viewvc/llvm-project?rev=186507&view=rev
Log:
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.

Added:
    llvm/trunk/test/MC/Mips/mips-control-instructions.s
Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/MC/Mips/mips_directives.s

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=186507&r1=186506&r2=186507&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Jul 17 09:05:19 2013
@@ -520,6 +520,19 @@ class BRK_FM<bits<6> funct>
 }
 
 //===----------------------------------------------------------------------===//
+//  Exception return format <Cop0|1|0|funct>
+//===----------------------------------------------------------------------===//
+
+class ER_FM<bits<6> funct>
+{
+  bits<32> Inst;
+  let Inst{31-26} = 0x10;
+  let Inst{25}    = 1;
+  let Inst{24-6}  = 0;
+  let Inst{5-0}   = funct;
+}
+
+//===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS
 //

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=186507&r1=186506&r2=186507&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Jul 17 09:05:19 2013
@@ -652,6 +652,11 @@ class BRK_FT<string opstr> :
   InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
          !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
 
+// (D)Eret
+class ER_FT<string opstr> :
+  InstSE<(outs), (ins),
+         opstr, [], NoItinerary, FrmOther>;
+
 // Sync
 let hasSideEffects = 1 in
 class SYNC_FT :
@@ -958,6 +963,9 @@ def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TE
 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
 
+def ERET : ER_FT<"eret">, ER_FM<0x18>;
+def DERET : ER_FT<"deret">, ER_FM<0x1f>;
+
 /// Load-linked, Store-conditional
 let Predicates = [NotN64, HasStdEnc] in {
   def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;

Added: llvm/trunk/test/MC/Mips/mips-control-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-control-instructions.s?rev=186507&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-control-instructions.s (added)
+++ llvm/trunk/test/MC/Mips/mips-control-instructions.s Wed Jul 17 09:05:19 2013
@@ -0,0 +1,28 @@
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
+# RUN: FileCheck -check-prefix=CHECK32  %s
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips64r2 | \
+# RUN: FileCheck -check-prefix=CHECK64  %s
+
+# CHECK32:    break                      # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK32:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK32:    break   7, 5               # encoding: [0x00,0x07,0x01,0x4d]
+# CHECK32:    syscall                    # encoding: [0x00,0x00,0x00,0x0c]
+# CHECK32:    syscall 13396              # encoding: [0x00,0x0d,0x15,0x0c]
+# CHECK32:    eret                       # encoding: [0x42,0x00,0x00,0x18]
+# CHECK32:    deret                      # encoding: [0x42,0x00,0x00,0x1f]
+
+# CHECK64:    break                      # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK64:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK64:    break   7, 5               # encoding: [0x00,0x07,0x01,0x4d]
+# CHECK64:    syscall                    # encoding: [0x00,0x00,0x00,0x0c]
+# CHECK64:    syscall 13396              # encoding: [0x00,0x0d,0x15,0x0c]
+# CHECK64:    eret                       # encoding: [0x42,0x00,0x00,0x18]
+# CHECK64:    deret                      # encoding: [0x42,0x00,0x00,0x1f]
+
+    break
+    break 7
+    break 7,5
+    syscall
+    syscall 0x3454
+    eret
+    deret

Modified: llvm/trunk/test/MC/Mips/mips_directives.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips_directives.s?rev=186507&r1=186506&r2=186507&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips_directives.s (original)
+++ llvm/trunk/test/MC/Mips/mips_directives.s Wed Jul 17 09:05:19 2013
@@ -41,15 +41,5 @@ $JTI0_0:
     .set f6,$f6
 # CHECK:    abs.s   $f6, $f7           # encoding: [0x46,0x00,0x39,0x85]
 # CHECK:    and     $3, $15, $15       # encoding: [0x01,0xef,0x18,0x24]
-# CHECK:    break                      # encoding: [0x00,0x00,0x00,0x0d]
-# CHECK:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
-# CHECK:    break   7, 5               # encoding: [0x00,0x07,0x01,0x4d]
-# CHECK:    syscall                    # encoding: [0x00,0x00,0x00,0x0c]
-# CHECK:    syscall 13396              # encoding: [0x00,0x0d,0x15,0x0c]
     abs.s  f6,FPU_MASK
     and    r3,$t7,STORE_MASK
-    break
-    break 7
-    break 7,5
-    syscall
-    syscall 0x3454