llvm.trap instrinsic for Mips

[Sasa Stankovic]

Hi,

Please find attached the patch that implements llvm.trap intrinsic for
Mips. Default behavior for this intrinsic is to call abort(). X86 and Arm
implement the intrinsic by emitting undefined instruction opcodes. Since
I'm not sure whether the undefined opcodes exist for Mips, I implemented
the intrinsic by emitting opcode for the break instruction (0xd) (break
instruction generates SIGTRAP signal).

Regards,
Sasa


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