[llvm] r186280 - Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
Stephen Lin
stephenwlin at gmail.com
Sat Jul 13 23:24:16 PDT 2013
Author: stephenwlin
Date: Sun Jul 14 01:24:09 2013
New Revision: 186280
URL: http://llvm.org/viewvc/llvm-project?rev=186280&view=rev
Log:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
Modified:
llvm/trunk/test/CodeGen/AArch64/addsub.ll
llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll
llvm/trunk/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
llvm/trunk/test/CodeGen/AArch64/basic-pic.ll
llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
llvm/trunk/test/CodeGen/AArch64/breg.ll
llvm/trunk/test/CodeGen/AArch64/callee-save.ll
llvm/trunk/test/CodeGen/AArch64/code-model-large-abs.ll
llvm/trunk/test/CodeGen/AArch64/compare-branch.ll
llvm/trunk/test/CodeGen/AArch64/dp1.ll
llvm/trunk/test/CodeGen/AArch64/dp2.ll
llvm/trunk/test/CodeGen/AArch64/extract.ll
llvm/trunk/test/CodeGen/AArch64/fastcc-reserved.ll
llvm/trunk/test/CodeGen/AArch64/fastcc.ll
llvm/trunk/test/CodeGen/AArch64/floatdp_1source.ll
llvm/trunk/test/CodeGen/AArch64/fp-dp3.ll
llvm/trunk/test/CodeGen/AArch64/fpimm.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/func-calls.ll
llvm/trunk/test/CodeGen/AArch64/got-abuse.ll
llvm/trunk/test/CodeGen/AArch64/i128-align.ll
llvm/trunk/test/CodeGen/AArch64/ldst-regoffset.ll
llvm/trunk/test/CodeGen/AArch64/ldst-unscaledimm.ll
llvm/trunk/test/CodeGen/AArch64/ldst-unsignedimm.ll
llvm/trunk/test/CodeGen/AArch64/literal_pools.ll
llvm/trunk/test/CodeGen/AArch64/local_vars.ll
llvm/trunk/test/CodeGen/AArch64/logical_shifted_reg.ll
llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll
llvm/trunk/test/CodeGen/AArch64/sibling-call.ll
llvm/trunk/test/CodeGen/AArch64/tail-call.ll
llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
llvm/trunk/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll
llvm/trunk/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
llvm/trunk/test/CodeGen/ARM/2011-04-07-schediv.ll
llvm/trunk/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
llvm/trunk/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
llvm/trunk/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
llvm/trunk/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
llvm/trunk/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
llvm/trunk/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
llvm/trunk/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
llvm/trunk/test/CodeGen/ARM/2013-01-21-PR14992.ll
llvm/trunk/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
llvm/trunk/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
llvm/trunk/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
llvm/trunk/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll
llvm/trunk/test/CodeGen/ARM/a15-partial-update.ll
llvm/trunk/test/CodeGen/ARM/arguments.ll
llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll
llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll
llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
llvm/trunk/test/CodeGen/ARM/atomicrmw_minmax.ll
llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
llvm/trunk/test/CodeGen/ARM/bfc.ll
llvm/trunk/test/CodeGen/ARM/bfi.ll
llvm/trunk/test/CodeGen/ARM/bswap-inline-asm.ll
llvm/trunk/test/CodeGen/ARM/call-noret-minsize.ll
llvm/trunk/test/CodeGen/ARM/call-noret.ll
llvm/trunk/test/CodeGen/ARM/call-tc.ll
llvm/trunk/test/CodeGen/ARM/call_nolink.ll
llvm/trunk/test/CodeGen/ARM/carry.ll
llvm/trunk/test/CodeGen/ARM/code-placement.ll
llvm/trunk/test/CodeGen/ARM/ctz.ll
llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
llvm/trunk/test/CodeGen/ARM/data-in-code-annotations.ll
llvm/trunk/test/CodeGen/ARM/divmod.ll
llvm/trunk/test/CodeGen/ARM/ehabi-filters.ll
llvm/trunk/test/CodeGen/ARM/ehabi.ll
llvm/trunk/test/CodeGen/ARM/extload-knownzero.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-ext.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-frameaddr.ll
llvm/trunk/test/CodeGen/ARM/fmacs.ll
llvm/trunk/test/CodeGen/ARM/fmscs.ll
llvm/trunk/test/CodeGen/ARM/fnmacs.ll
llvm/trunk/test/CodeGen/ARM/fnmscs.ll
llvm/trunk/test/CodeGen/ARM/fp.ll
llvm/trunk/test/CodeGen/ARM/fp16.ll
llvm/trunk/test/CodeGen/ARM/fparith.ll
llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
llvm/trunk/test/CodeGen/ARM/fpcmp.ll
llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll
llvm/trunk/test/CodeGen/ARM/fpconsts.ll
llvm/trunk/test/CodeGen/ARM/fpconv.ll
llvm/trunk/test/CodeGen/ARM/fpmem.ll
llvm/trunk/test/CodeGen/ARM/fptoint.ll
llvm/trunk/test/CodeGen/ARM/fusedMAC.ll
llvm/trunk/test/CodeGen/ARM/globals.ll
llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
llvm/trunk/test/CodeGen/ARM/hidden-vis.ll
llvm/trunk/test/CodeGen/ARM/ifcvt1.ll
llvm/trunk/test/CodeGen/ARM/ifcvt10.ll
llvm/trunk/test/CodeGen/ARM/ifcvt11.ll
llvm/trunk/test/CodeGen/ARM/ifcvt12.ll
llvm/trunk/test/CodeGen/ARM/ifcvt2.ll
llvm/trunk/test/CodeGen/ARM/ifcvt3.ll
llvm/trunk/test/CodeGen/ARM/ifcvt4.ll
llvm/trunk/test/CodeGen/ARM/ifcvt5.ll
llvm/trunk/test/CodeGen/ARM/indirectbr-2.ll
llvm/trunk/test/CodeGen/ARM/indirectbr.ll
llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll
llvm/trunk/test/CodeGen/ARM/inlineasm4.ll
llvm/trunk/test/CodeGen/ARM/ldm.ll
llvm/trunk/test/CodeGen/ARM/ldr.ll
llvm/trunk/test/CodeGen/ARM/ldrd.ll
llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll
llvm/trunk/test/CodeGen/ARM/ldstrexd.ll
llvm/trunk/test/CodeGen/ARM/load-address-masked.ll
llvm/trunk/test/CodeGen/ARM/load_i1_select.ll
llvm/trunk/test/CodeGen/ARM/long.ll
llvm/trunk/test/CodeGen/ARM/longMAC.ll
llvm/trunk/test/CodeGen/ARM/lsr-icmp-imm.ll
llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
llvm/trunk/test/CodeGen/ARM/machine-licm.ll
llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
llvm/trunk/test/CodeGen/ARM/memset-inline.ll
llvm/trunk/test/CodeGen/ARM/mls.ll
llvm/trunk/test/CodeGen/ARM/movt.ll
llvm/trunk/test/CodeGen/ARM/mul_const.ll
llvm/trunk/test/CodeGen/ARM/mulhi.ll
llvm/trunk/test/CodeGen/ARM/neon-spfp.ll
llvm/trunk/test/CodeGen/ARM/neon_minmax.ll
llvm/trunk/test/CodeGen/ARM/peephole-bitcast.ll
llvm/trunk/test/CodeGen/ARM/popcnt.ll
llvm/trunk/test/CodeGen/ARM/prefetch.ll
llvm/trunk/test/CodeGen/ARM/private.ll
llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
llvm/trunk/test/CodeGen/ARM/ret_sret_vector.ll
llvm/trunk/test/CodeGen/ARM/sbfx.ll
llvm/trunk/test/CodeGen/ARM/select-imm.ll
llvm/trunk/test/CodeGen/ARM/select.ll
llvm/trunk/test/CodeGen/ARM/select_xform.ll
llvm/trunk/test/CodeGen/ARM/spill-q.ll
llvm/trunk/test/CodeGen/ARM/struct_byval.ll
llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
llvm/trunk/test/CodeGen/ARM/tail-dup.ll
llvm/trunk/test/CodeGen/ARM/tail-opts.ll
llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll
llvm/trunk/test/CodeGen/ARM/tls-models.ll
llvm/trunk/test/CodeGen/ARM/tls2.ll
llvm/trunk/test/CodeGen/ARM/trap.ll
llvm/trunk/test/CodeGen/ARM/twoaddrinstr.ll
llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll
llvm/trunk/test/CodeGen/ARM/unaligned_load_store_vector.ll
llvm/trunk/test/CodeGen/ARM/undef-sext.ll
llvm/trunk/test/CodeGen/ARM/unwind-init.ll
llvm/trunk/test/CodeGen/ARM/v1-constant-fold.ll
llvm/trunk/test/CodeGen/ARM/vaba.ll
llvm/trunk/test/CodeGen/ARM/vabd.ll
llvm/trunk/test/CodeGen/ARM/vabs.ll
llvm/trunk/test/CodeGen/ARM/vadd.ll
llvm/trunk/test/CodeGen/ARM/vbits.ll
llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll
llvm/trunk/test/CodeGen/ARM/vbsl.ll
llvm/trunk/test/CodeGen/ARM/vceq.ll
llvm/trunk/test/CodeGen/ARM/vcge.ll
llvm/trunk/test/CodeGen/ARM/vcgt.ll
llvm/trunk/test/CodeGen/ARM/vcnt.ll
llvm/trunk/test/CodeGen/ARM/vcvt-cost.ll
llvm/trunk/test/CodeGen/ARM/vcvt.ll
llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
llvm/trunk/test/CodeGen/ARM/vdup.ll
llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll
llvm/trunk/test/CodeGen/ARM/vfcmp.ll
llvm/trunk/test/CodeGen/ARM/vget_lane.ll
llvm/trunk/test/CodeGen/ARM/vhadd.ll
llvm/trunk/test/CodeGen/ARM/vhsub.ll
llvm/trunk/test/CodeGen/ARM/vicmp.ll
llvm/trunk/test/CodeGen/ARM/vld1.ll
llvm/trunk/test/CodeGen/ARM/vld2.ll
llvm/trunk/test/CodeGen/ARM/vld3.ll
llvm/trunk/test/CodeGen/ARM/vld4.ll
llvm/trunk/test/CodeGen/ARM/vlddup.ll
llvm/trunk/test/CodeGen/ARM/vldlane.ll
llvm/trunk/test/CodeGen/ARM/vminmax.ll
llvm/trunk/test/CodeGen/ARM/vmla.ll
llvm/trunk/test/CodeGen/ARM/vmls.ll
llvm/trunk/test/CodeGen/ARM/vmov.ll
llvm/trunk/test/CodeGen/ARM/vmul.ll
llvm/trunk/test/CodeGen/ARM/vneg.ll
llvm/trunk/test/CodeGen/ARM/vpadal.ll
llvm/trunk/test/CodeGen/ARM/vpadd.ll
llvm/trunk/test/CodeGen/ARM/vpminmax.ll
llvm/trunk/test/CodeGen/ARM/vqadd.ll
llvm/trunk/test/CodeGen/ARM/vqdmul.ll
llvm/trunk/test/CodeGen/ARM/vqshl.ll
llvm/trunk/test/CodeGen/ARM/vqshrn.ll
llvm/trunk/test/CodeGen/ARM/vqsub.ll
llvm/trunk/test/CodeGen/ARM/vrec.ll
llvm/trunk/test/CodeGen/ARM/vselect_imax.ll
llvm/trunk/test/CodeGen/ARM/vshift.ll
llvm/trunk/test/CodeGen/ARM/vshiftins.ll
llvm/trunk/test/CodeGen/ARM/vshl.ll
llvm/trunk/test/CodeGen/ARM/vshll.ll
llvm/trunk/test/CodeGen/ARM/vshrn.ll
llvm/trunk/test/CodeGen/ARM/vsra.ll
llvm/trunk/test/CodeGen/ARM/vst1.ll
llvm/trunk/test/CodeGen/ARM/vst2.ll
llvm/trunk/test/CodeGen/ARM/vst3.ll
llvm/trunk/test/CodeGen/ARM/vst4.ll
llvm/trunk/test/CodeGen/ARM/vstlane.ll
llvm/trunk/test/CodeGen/ARM/vsub.ll
llvm/trunk/test/CodeGen/ARM/vtbl.ll
llvm/trunk/test/CodeGen/ARM/vtrn.ll
llvm/trunk/test/CodeGen/ARM/vuzp.ll
llvm/trunk/test/CodeGen/ARM/vzip.ll
llvm/trunk/test/CodeGen/MBlaze/brind.ll
llvm/trunk/test/CodeGen/MBlaze/callind.ll
llvm/trunk/test/CodeGen/MBlaze/cc.ll
llvm/trunk/test/CodeGen/MBlaze/div.ll
llvm/trunk/test/CodeGen/MBlaze/fpu.ll
llvm/trunk/test/CodeGen/MBlaze/fsl.ll
llvm/trunk/test/CodeGen/MBlaze/imm.ll
llvm/trunk/test/CodeGen/MBlaze/intr.ll
llvm/trunk/test/CodeGen/MBlaze/jumptable.ll
llvm/trunk/test/CodeGen/MBlaze/loop.ll
llvm/trunk/test/CodeGen/MBlaze/mul.ll
llvm/trunk/test/CodeGen/MBlaze/mul64.ll
llvm/trunk/test/CodeGen/MBlaze/select.ll
llvm/trunk/test/CodeGen/MBlaze/shift.ll
llvm/trunk/test/CodeGen/MBlaze/svol.ll
llvm/trunk/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-rx.ll
llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-xr.ll
llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-rx.ll
llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-xr.ll
llvm/trunk/test/CodeGen/MSP430/Inst16mi.ll
llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll
llvm/trunk/test/CodeGen/MSP430/Inst16ri.ll
llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll
llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll
llvm/trunk/test/CodeGen/MSP430/Inst8mi.ll
llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll
llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll
llvm/trunk/test/CodeGen/MSP430/Inst8ri.ll
llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll
llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll
llvm/trunk/test/CodeGen/MSP430/bit.ll
llvm/trunk/test/CodeGen/MSP430/byval.ll
llvm/trunk/test/CodeGen/MSP430/fp.ll
llvm/trunk/test/CodeGen/MSP430/postinc.ll
llvm/trunk/test/CodeGen/MSP430/setcc.ll
llvm/trunk/test/CodeGen/MSP430/shifts.ll
llvm/trunk/test/CodeGen/MSP430/vararg.ll
llvm/trunk/test/CodeGen/Mips/atomic.ll
llvm/trunk/test/CodeGen/Mips/atomicops.ll
llvm/trunk/test/CodeGen/Mips/biggot.ll
llvm/trunk/test/CodeGen/Mips/brdelayslot.ll
llvm/trunk/test/CodeGen/Mips/bswap.ll
llvm/trunk/test/CodeGen/Mips/check-noat.ll
llvm/trunk/test/CodeGen/Mips/cmov.ll
llvm/trunk/test/CodeGen/Mips/const-mult.ll
llvm/trunk/test/CodeGen/Mips/divrem.ll
llvm/trunk/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll
llvm/trunk/test/CodeGen/Mips/ex2.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
llvm/trunk/test/CodeGen/Mips/largefr1.ll
llvm/trunk/test/CodeGen/Mips/mips16fpe.ll
llvm/trunk/test/CodeGen/Mips/mips64-f128.ll
llvm/trunk/test/CodeGen/Mips/mips64-libcall.ll
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
llvm/trunk/test/CodeGen/Mips/misha.ll
llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
llvm/trunk/test/CodeGen/Mips/private.ll
llvm/trunk/test/CodeGen/Mips/return-vector.ll
llvm/trunk/test/CodeGen/Mips/setcc-se.ll
llvm/trunk/test/CodeGen/Mips/sint-fp-store_pattern.ll
llvm/trunk/test/CodeGen/Mips/stackcoloring.ll
llvm/trunk/test/CodeGen/Mips/stchar.ll
llvm/trunk/test/CodeGen/Mips/tls-models.ll
llvm/trunk/test/CodeGen/Mips/tls.ll
llvm/trunk/test/CodeGen/Mips/tnaked.ll
llvm/trunk/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
llvm/trunk/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
llvm/trunk/test/CodeGen/PowerPC/addc.ll
llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll
llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll
llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll
llvm/trunk/test/CodeGen/PowerPC/complex-return.ll
llvm/trunk/test/CodeGen/PowerPC/dbg.ll
llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll
llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
llvm/trunk/test/CodeGen/PowerPC/ppc64-toc.ll
llvm/trunk/test/CodeGen/PowerPC/pr13891.ll
llvm/trunk/test/CodeGen/PowerPC/rounding-ops.ll
llvm/trunk/test/CodeGen/PowerPC/svr4-redzone.ll
llvm/trunk/test/CodeGen/PowerPC/tls-2.ll
llvm/trunk/test/CodeGen/PowerPC/tls.ll
llvm/trunk/test/CodeGen/PowerPC/vec_cmp.ll
llvm/trunk/test/CodeGen/PowerPC/vec_conv.ll
llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll
llvm/trunk/test/CodeGen/PowerPC/vec_rounding.ll
llvm/trunk/test/CodeGen/PowerPC/vec_sqrt.ll
llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
llvm/trunk/test/CodeGen/SPARC/64bit.ll
llvm/trunk/test/CodeGen/SPARC/basictest.ll
llvm/trunk/test/CodeGen/SPARC/blockaddr.ll
llvm/trunk/test/CodeGen/SPARC/float.ll
llvm/trunk/test/CodeGen/SPARC/leafproc.ll
llvm/trunk/test/CodeGen/SystemZ/addr-01.ll
llvm/trunk/test/CodeGen/SystemZ/addr-02.ll
llvm/trunk/test/CodeGen/SystemZ/addr-03.ll
llvm/trunk/test/CodeGen/SystemZ/alloca-01.ll
llvm/trunk/test/CodeGen/SystemZ/alloca-02.ll
llvm/trunk/test/CodeGen/SystemZ/and-01.ll
llvm/trunk/test/CodeGen/SystemZ/and-02.ll
llvm/trunk/test/CodeGen/SystemZ/and-03.ll
llvm/trunk/test/CodeGen/SystemZ/and-04.ll
llvm/trunk/test/CodeGen/SystemZ/and-05.ll
llvm/trunk/test/CodeGen/SystemZ/and-06.ll
llvm/trunk/test/CodeGen/SystemZ/args-01.ll
llvm/trunk/test/CodeGen/SystemZ/args-02.ll
llvm/trunk/test/CodeGen/SystemZ/args-03.ll
llvm/trunk/test/CodeGen/SystemZ/args-04.ll
llvm/trunk/test/CodeGen/SystemZ/args-05.ll
llvm/trunk/test/CodeGen/SystemZ/args-06.ll
llvm/trunk/test/CodeGen/SystemZ/asm-01.ll
llvm/trunk/test/CodeGen/SystemZ/asm-02.ll
llvm/trunk/test/CodeGen/SystemZ/asm-03.ll
llvm/trunk/test/CodeGen/SystemZ/asm-04.ll
llvm/trunk/test/CodeGen/SystemZ/asm-05.ll
llvm/trunk/test/CodeGen/SystemZ/asm-06.ll
llvm/trunk/test/CodeGen/SystemZ/asm-07.ll
llvm/trunk/test/CodeGen/SystemZ/asm-08.ll
llvm/trunk/test/CodeGen/SystemZ/asm-09.ll
llvm/trunk/test/CodeGen/SystemZ/asm-10.ll
llvm/trunk/test/CodeGen/SystemZ/asm-11.ll
llvm/trunk/test/CodeGen/SystemZ/asm-12.ll
llvm/trunk/test/CodeGen/SystemZ/asm-13.ll
llvm/trunk/test/CodeGen/SystemZ/asm-14.ll
llvm/trunk/test/CodeGen/SystemZ/asm-15.ll
llvm/trunk/test/CodeGen/SystemZ/asm-16.ll
llvm/trunk/test/CodeGen/SystemZ/asm-17.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-load-01.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-load-02.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-load-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-load-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-store-01.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-store-02.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-store-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomic-store-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-01.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-02.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-01.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-02.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
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llvm/trunk/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
llvm/trunk/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
llvm/trunk/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
llvm/trunk/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
llvm/trunk/test/CodeGen/X86/2012-04-26-sdglue.ll
llvm/trunk/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
llvm/trunk/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
llvm/trunk/test/CodeGen/X86/2012-08-16-setcc.ll
llvm/trunk/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
llvm/trunk/test/CodeGen/X86/3addr-16bit.ll
llvm/trunk/test/CodeGen/X86/abi-isel.ll
llvm/trunk/test/CodeGen/X86/and-su.ll
llvm/trunk/test/CodeGen/X86/apm.ll
llvm/trunk/test/CodeGen/X86/asm-global-imm.ll
llvm/trunk/test/CodeGen/X86/asm-modifier-P.ll
llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division-64.ll
llvm/trunk/test/CodeGen/X86/atom-bypass-slow-division.ll
llvm/trunk/test/CodeGen/X86/atomic-minmax-i6432.ll
llvm/trunk/test/CodeGen/X86/atomic-or.ll
llvm/trunk/test/CodeGen/X86/atomic_add.ll
llvm/trunk/test/CodeGen/X86/avx-minmax.ll
llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll
llvm/trunk/test/CodeGen/X86/avx-vextractf128.ll
llvm/trunk/test/CodeGen/X86/avx2-logic.ll
llvm/trunk/test/CodeGen/X86/avx2-phaddsub.ll
llvm/trunk/test/CodeGen/X86/avx2-shift.ll
llvm/trunk/test/CodeGen/X86/bmi.ll
llvm/trunk/test/CodeGen/X86/break-sse-dep.ll
llvm/trunk/test/CodeGen/X86/bswap-inline-asm.ll
llvm/trunk/test/CodeGen/X86/bswap.ll
llvm/trunk/test/CodeGen/X86/byval7.ll
llvm/trunk/test/CodeGen/X86/call-push.ll
llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll
llvm/trunk/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
llvm/trunk/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
llvm/trunk/test/CodeGen/X86/clz.ll
llvm/trunk/test/CodeGen/X86/codegen-prepare.ll
llvm/trunk/test/CodeGen/X86/codemodel.ll
llvm/trunk/test/CodeGen/X86/commute-two-addr.ll
llvm/trunk/test/CodeGen/X86/compare-inf.ll
llvm/trunk/test/CodeGen/X86/extractelement-load.ll
llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll
llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll
llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll
llvm/trunk/test/CodeGen/X86/fast-isel-tls.ll
llvm/trunk/test/CodeGen/X86/fold-add.ll
llvm/trunk/test/CodeGen/X86/fold-and-shift.ll
llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-1.ll
llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll
llvm/trunk/test/CodeGen/X86/force-align-stack-alloca.ll
llvm/trunk/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
llvm/trunk/test/CodeGen/X86/fp-elim.ll
llvm/trunk/test/CodeGen/X86/fp_constant_op.ll
llvm/trunk/test/CodeGen/X86/h-registers-0.ll
llvm/trunk/test/CodeGen/X86/h-registers-2.ll
llvm/trunk/test/CodeGen/X86/haddsub.ll
llvm/trunk/test/CodeGen/X86/hidden-vis-4.ll
llvm/trunk/test/CodeGen/X86/hidden-vis.ll
llvm/trunk/test/CodeGen/X86/hipe-prologue.ll
llvm/trunk/test/CodeGen/X86/hoist-common.ll
llvm/trunk/test/CodeGen/X86/i128-sdiv.ll
llvm/trunk/test/CodeGen/X86/inline-asm-R-constraint.ll
llvm/trunk/test/CodeGen/X86/inreg.ll
llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll
llvm/trunk/test/CodeGen/X86/jump_sign.ll
llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll
llvm/trunk/test/CodeGen/X86/loop-blocks.ll
llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll
llvm/trunk/test/CodeGen/X86/lsr-reuse.ll
llvm/trunk/test/CodeGen/X86/lzcnt.ll
llvm/trunk/test/CodeGen/X86/machine-cp.ll
llvm/trunk/test/CodeGen/X86/machine-cse.ll
llvm/trunk/test/CodeGen/X86/mcinst-lowering.ll
llvm/trunk/test/CodeGen/X86/memcmp.ll
llvm/trunk/test/CodeGen/X86/memcpy-2.ll
llvm/trunk/test/CodeGen/X86/memset-2.ll
llvm/trunk/test/CodeGen/X86/mmx-arg-passing.ll
llvm/trunk/test/CodeGen/X86/mmx-shift.ll
llvm/trunk/test/CodeGen/X86/movgs.ll
llvm/trunk/test/CodeGen/X86/movmsk.ll
llvm/trunk/test/CodeGen/X86/ms-inline-asm.ll
llvm/trunk/test/CodeGen/X86/narrow_op-1.ll
llvm/trunk/test/CodeGen/X86/neg_cmp.ll
llvm/trunk/test/CodeGen/X86/non-lazy-bind.ll
llvm/trunk/test/CodeGen/X86/optimize-max-3.ll
llvm/trunk/test/CodeGen/X86/palignr-2.ll
llvm/trunk/test/CodeGen/X86/pass-three.ll
llvm/trunk/test/CodeGen/X86/peep-test-3.ll
llvm/trunk/test/CodeGen/X86/peep-test-4.ll
llvm/trunk/test/CodeGen/X86/phaddsub.ll
llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-3.ll
llvm/trunk/test/CodeGen/X86/popcnt.ll
llvm/trunk/test/CodeGen/X86/postra-licm.ll
llvm/trunk/test/CodeGen/X86/pr12360.ll
llvm/trunk/test/CodeGen/X86/pr13209.ll
llvm/trunk/test/CodeGen/X86/pr16031.ll
llvm/trunk/test/CodeGen/X86/pr2182.ll
llvm/trunk/test/CodeGen/X86/pr3216.ll
llvm/trunk/test/CodeGen/X86/private.ll
llvm/trunk/test/CodeGen/X86/promote-i16.ll
llvm/trunk/test/CodeGen/X86/rdrand.ll
llvm/trunk/test/CodeGen/X86/rdseed.ll
llvm/trunk/test/CodeGen/X86/red-zone.ll
llvm/trunk/test/CodeGen/X86/red-zone2.ll
llvm/trunk/test/CodeGen/X86/remat-mov-0.ll
llvm/trunk/test/CodeGen/X86/ret-mmx.ll
llvm/trunk/test/CodeGen/X86/rot16.ll
llvm/trunk/test/CodeGen/X86/rot32.ll
llvm/trunk/test/CodeGen/X86/rot64.ll
llvm/trunk/test/CodeGen/X86/rounding-ops.ll
llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
llvm/trunk/test/CodeGen/X86/setcc.ll
llvm/trunk/test/CodeGen/X86/sext-i1.ll
llvm/trunk/test/CodeGen/X86/sext-subreg.ll
llvm/trunk/test/CodeGen/X86/shift-and.ll
llvm/trunk/test/CodeGen/X86/shift-codegen.ll
llvm/trunk/test/CodeGen/X86/shl-anyext.ll
llvm/trunk/test/CodeGen/X86/shl_elim.ll
llvm/trunk/test/CodeGen/X86/sibcall-2.ll
llvm/trunk/test/CodeGen/X86/sibcall-3.ll
llvm/trunk/test/CodeGen/X86/sibcall-4.ll
llvm/trunk/test/CodeGen/X86/sibcall-5.ll
llvm/trunk/test/CodeGen/X86/sibcall.ll
llvm/trunk/test/CodeGen/X86/sink-hoist.ll
llvm/trunk/test/CodeGen/X86/splat-scalar-load.ll
llvm/trunk/test/CodeGen/X86/sse-align-12.ll
llvm/trunk/test/CodeGen/X86/sse-align-2.ll
llvm/trunk/test/CodeGen/X86/sse-commute.ll
llvm/trunk/test/CodeGen/X86/sse-minmax.ll
llvm/trunk/test/CodeGen/X86/sse3.ll
llvm/trunk/test/CodeGen/X86/sse41.ll
llvm/trunk/test/CodeGen/X86/sse_partial_update.ll
llvm/trunk/test/CodeGen/X86/stack-protector.ll
llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll
llvm/trunk/test/CodeGen/X86/store_op_load_fold.ll
llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll
llvm/trunk/test/CodeGen/X86/tail-opts.ll
llvm/trunk/test/CodeGen/X86/tailcall-cgp-dup.ll
llvm/trunk/test/CodeGen/X86/tailcallbyval64.ll
llvm/trunk/test/CodeGen/X86/tailcallfp2.ll
llvm/trunk/test/CodeGen/X86/test-shrink.ll
llvm/trunk/test/CodeGen/X86/tls-local-dynamic.ll
llvm/trunk/test/CodeGen/X86/tls-models.ll
llvm/trunk/test/CodeGen/X86/tls-pic.ll
llvm/trunk/test/CodeGen/X86/tls-pie.ll
llvm/trunk/test/CodeGen/X86/tls.ll
llvm/trunk/test/CodeGen/X86/tlv-1.ll
llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll
llvm/trunk/test/CodeGen/X86/unwind-init.ll
llvm/trunk/test/CodeGen/X86/vec-sign.ll
llvm/trunk/test/CodeGen/X86/vec_insert-2.ll
llvm/trunk/test/CodeGen/X86/vec_insert-5.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll
llvm/trunk/test/CodeGen/X86/vec_splat-3.ll
llvm/trunk/test/CodeGen/X86/vector-gep.ll
llvm/trunk/test/CodeGen/X86/vshift-1.ll
llvm/trunk/test/CodeGen/X86/vshift-2.ll
llvm/trunk/test/CodeGen/X86/vshift-3.ll
llvm/trunk/test/CodeGen/X86/vshift-4.ll
llvm/trunk/test/CodeGen/X86/vshift-5.ll
llvm/trunk/test/CodeGen/X86/widen_extract-1.ll
llvm/trunk/test/CodeGen/X86/widen_load-2.ll
llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
llvm/trunk/test/CodeGen/X86/win64_vararg.ll
llvm/trunk/test/CodeGen/X86/x86-64-and-mask.ll
llvm/trunk/test/CodeGen/X86/x86-64-sret-return.ll
llvm/trunk/test/CodeGen/X86/x86-shifts.ll
llvm/trunk/test/CodeGen/X86/xmulo.ll
llvm/trunk/test/CodeGen/X86/xor-icmp.ll
llvm/trunk/test/CodeGen/X86/zero-remat.ll
llvm/trunk/test/CodeGen/X86/zext-extract_subreg.ll
llvm/trunk/test/CodeGen/X86/zext-shl.ll
llvm/trunk/test/CodeGen/X86/zext-trunc.ll
llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
llvm/trunk/test/CodeGen/XCore/addsub64.ll
llvm/trunk/test/CodeGen/XCore/aliases.ll
llvm/trunk/test/CodeGen/XCore/ashr.ll
llvm/trunk/test/CodeGen/XCore/bigstructret.ll
llvm/trunk/test/CodeGen/XCore/constants.ll
llvm/trunk/test/CodeGen/XCore/events.ll
llvm/trunk/test/CodeGen/XCore/float-intrinsics.ll
llvm/trunk/test/CodeGen/XCore/globals.ll
llvm/trunk/test/CodeGen/XCore/indirectbr.ll
llvm/trunk/test/CodeGen/XCore/ladd_lsub_combine.ll
llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll
llvm/trunk/test/CodeGen/XCore/load.ll
llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll
llvm/trunk/test/CodeGen/XCore/mkmsk.ll
llvm/trunk/test/CodeGen/XCore/mul64.ll
llvm/trunk/test/CodeGen/XCore/offset_folding.ll
llvm/trunk/test/CodeGen/XCore/private.ll
llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll
llvm/trunk/test/CodeGen/XCore/resources.ll
llvm/trunk/test/CodeGen/XCore/sext.ll
llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll
llvm/trunk/test/CodeGen/XCore/store.ll
llvm/trunk/test/CodeGen/XCore/threads.ll
llvm/trunk/test/CodeGen/XCore/tls.ll
llvm/trunk/test/CodeGen/XCore/trampoline.ll
llvm/trunk/test/CodeGen/XCore/unaligned_load.ll
llvm/trunk/test/CodeGen/XCore/unaligned_store.ll
llvm/trunk/test/CodeGen/XCore/unaligned_store_combine.ll
Modified: llvm/trunk/test/CodeGen/AArch64/addsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/addsub.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/addsub.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@
; Add pure 12-bit immediates:
define void @add_small() {
-; CHECK: add_small:
+; CHECK-LABEL: add_small:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32
@@ -26,7 +26,7 @@ define void @add_small() {
; Add 12-bit immediates, shifted left by 12 bits
define void @add_med() {
-; CHECK: add_med:
+; CHECK-LABEL: add_med:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32
@@ -43,7 +43,7 @@ define void @add_med() {
; Subtract 12-bit immediates
define void @sub_small() {
-; CHECK: sub_small:
+; CHECK-LABEL: sub_small:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32
@@ -60,7 +60,7 @@ define void @sub_small() {
; Subtract 12-bit immediates, shifted left by 12 bits
define void @sub_med() {
-; CHECK: sub_med:
+; CHECK-LABEL: sub_med:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32
Modified: llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
@var64 = global i64 0
define void @addsub_i8rhs() {
-; CHECK: addsub_i8rhs:
+; CHECK-LABEL: addsub_i8rhs:
%val8_tmp = load i8* @var8
%lhs32 = load i32* @var32
%lhs64 = load i64* @var64
@@ -81,7 +81,7 @@ end:
}
define void @addsub_i16rhs() {
-; CHECK: addsub_i16rhs:
+; CHECK-LABEL: addsub_i16rhs:
%val16_tmp = load i16* @var16
%lhs32 = load i32* @var32
%lhs64 = load i64* @var64
@@ -159,7 +159,7 @@ end:
; example), but the remaining instructions are probably not idiomatic
; in the face of "add/sub (shifted register)" so I don't intend to.
define void @addsub_i32rhs() {
-; CHECK: addsub_i32rhs:
+; CHECK-LABEL: addsub_i32rhs:
%val32_tmp = load i32* @var32
%lhs64 = load i64* @var64
Modified: llvm/trunk/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/atomic-ops-not-barriers.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/atomic-ops-not-barriers.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/atomic-ops-not-barriers.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
define i32 @foo(i32* %var, i1 %cond) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
br i1 %cond, label %atomic_ver, label %simple_ver
simple_ver:
%oldval = load i32* %var
Modified: llvm/trunk/test/CodeGen/AArch64/basic-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/basic-pic.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/basic-pic.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/basic-pic.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
define i32 @get_globalvar() {
-; CHECK: get_globalvar:
+; CHECK-LABEL: get_globalvar:
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -19,7 +19,7 @@ define i32 @get_globalvar() {
}
define i32* @get_globalvaraddr() {
-; CHECK: get_globalvaraddr:
+; CHECK-LABEL: get_globalvaraddr:
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -33,7 +33,7 @@ define i32* @get_globalvaraddr() {
@hiddenvar = hidden global i32 0
define i32 @get_hiddenvar() {
-; CHECK: get_hiddenvar:
+; CHECK-LABEL: get_hiddenvar:
%val = load i32* @hiddenvar
; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
@@ -45,7 +45,7 @@ define i32 @get_hiddenvar() {
}
define i32* @get_hiddenvaraddr() {
-; CHECK: get_hiddenvaraddr:
+; CHECK-LABEL: get_hiddenvaraddr:
%val = load i32* @hiddenvar
; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
@@ -57,7 +57,7 @@ define i32* @get_hiddenvaraddr() {
}
define void()* @get_func() {
-; CHECK: get_func:
+; CHECK-LABEL: get_func:
ret void()* bitcast(void()*()* @get_func to void()*)
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
Modified: llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
%struct.foo = type { i8, [2 x i8], i8 }
define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
-; CHECK: from_clang:
+; CHECK-LABEL: from_clang:
; CHECK: bfi w0, w1, #3, #4
; CHECK-NEXT: ret
Modified: llvm/trunk/test/CodeGen/AArch64/breg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/breg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/breg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/breg.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
@stored_label = global i8* null
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%lab = load i8** @stored_label
indirectbr i8* %lab, [label %otherlab, label %retlab]
; CHECK: adrp {{x[0-9]+}}, stored_label
Modified: llvm/trunk/test/CodeGen/AArch64/callee-save.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/callee-save.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/callee-save.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/callee-save.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
@var = global float 0.0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: stp d14, d15, [sp
; CHECK: stp d12, d13, [sp
Modified: llvm/trunk/test/CodeGen/AArch64/code-model-large-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/code-model-large-abs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/code-model-large-abs.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/code-model-large-abs.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
@var64 = global i64 0
define i8* @global_addr() {
-; CHECK: global_addr:
+; CHECK-LABEL: global_addr:
ret i8* @var8
; The movz/movk calculation should end up returned directly in x0.
; CHECK: movz x0, #:abs_g3:var8
@@ -17,7 +17,7 @@ define i8* @global_addr() {
}
define i8 @global_i8() {
-; CHECK: global_i8:
+; CHECK-LABEL: global_i8:
%val = load i8* @var8
ret i8 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
@@ -28,7 +28,7 @@ define i8 @global_i8() {
}
define i16 @global_i16() {
-; CHECK: global_i16:
+; CHECK-LABEL: global_i16:
%val = load i16* @var16
ret i16 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
@@ -39,7 +39,7 @@ define i16 @global_i16() {
}
define i32 @global_i32() {
-; CHECK: global_i32:
+; CHECK-LABEL: global_i32:
%val = load i32* @var32
ret i32 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
@@ -50,7 +50,7 @@ define i32 @global_i32() {
}
define i64 @global_i64() {
-; CHECK: global_i64:
+; CHECK-LABEL: global_i64:
%val = load i64* @var64
ret i64 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
Modified: llvm/trunk/test/CodeGen/AArch64/compare-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/compare-branch.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/compare-branch.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/compare-branch.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@var64 = global i64 0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%val1 = load volatile i32* @var32
%tst1 = icmp eq i32 %val1, 0
Modified: llvm/trunk/test/CodeGen/AArch64/dp1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/dp1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/dp1.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/dp1.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@var64 = global i64 0
define void @rev_i32() {
-; CHECK: rev_i32:
+; CHECK-LABEL: rev_i32:
%val0_tmp = load i32* @var32
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
@@ -13,7 +13,7 @@ define void @rev_i32() {
}
define void @rev_i64() {
-; CHECK: rev_i64:
+; CHECK-LABEL: rev_i64:
%val0_tmp = load i64* @var64
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
@@ -22,7 +22,7 @@ define void @rev_i64() {
}
define void @rev32_i64() {
-; CHECK: rev32_i64:
+; CHECK-LABEL: rev32_i64:
%val0_tmp = load i64* @var64
%val1_tmp = shl i64 %val0_tmp, 32
%val5_tmp = sub i64 64, 32
@@ -35,7 +35,7 @@ define void @rev32_i64() {
}
define void @rev16_i32() {
-; CHECK: rev16_i32:
+; CHECK-LABEL: rev16_i32:
%val0_tmp = load i32* @var32
%val1_tmp = shl i32 %val0_tmp, 16
%val2_tmp = lshr i32 %val0_tmp, 16
@@ -47,7 +47,7 @@ define void @rev16_i32() {
}
define void @clz_zerodef_i32() {
-; CHECK: clz_zerodef_i32:
+; CHECK-LABEL: clz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
@@ -56,7 +56,7 @@ define void @clz_zerodef_i32() {
}
define void @clz_zerodef_i64() {
-; CHECK: clz_zerodef_i64:
+; CHECK-LABEL: clz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
@@ -65,7 +65,7 @@ define void @clz_zerodef_i64() {
}
define void @clz_zeroundef_i32() {
-; CHECK: clz_zeroundef_i32:
+; CHECK-LABEL: clz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
@@ -74,7 +74,7 @@ define void @clz_zeroundef_i32() {
}
define void @clz_zeroundef_i64() {
-; CHECK: clz_zeroundef_i64:
+; CHECK-LABEL: clz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
@@ -83,7 +83,7 @@ define void @clz_zeroundef_i64() {
}
define void @cttz_zerodef_i32() {
-; CHECK: cttz_zerodef_i32:
+; CHECK-LABEL: cttz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -93,7 +93,7 @@ define void @cttz_zerodef_i32() {
}
define void @cttz_zerodef_i64() {
-; CHECK: cttz_zerodef_i64:
+; CHECK-LABEL: cttz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -103,7 +103,7 @@ define void @cttz_zerodef_i64() {
}
define void @cttz_zeroundef_i32() {
-; CHECK: cttz_zeroundef_i32:
+; CHECK-LABEL: cttz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -113,7 +113,7 @@ define void @cttz_zeroundef_i32() {
}
define void @cttz_zeroundef_i64() {
-; CHECK: cttz_zeroundef_i64:
+; CHECK-LABEL: cttz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -125,7 +125,7 @@ define void @cttz_zeroundef_i64() {
; These two are just compilation tests really: the operation's set to Expand in
; ISelLowering.
define void @ctpop_i32() {
-; CHECK: ctpop_i32:
+; CHECK-LABEL: ctpop_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
store volatile i32 %val4_tmp, i32* @var32
@@ -133,7 +133,7 @@ define void @ctpop_i32() {
}
define void @ctpop_i64() {
-; CHECK: ctpop_i64:
+; CHECK-LABEL: ctpop_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
store volatile i64 %val4_tmp, i64* @var64
Modified: llvm/trunk/test/CodeGen/AArch64/dp2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/dp2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/dp2.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/dp2.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
@var64_1 = global i64 0
define void @rorv_i64() {
-; CHECK: rorv_i64:
+; CHECK-LABEL: rorv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val2_tmp = sub i64 64, %val1_tmp
@@ -19,7 +19,7 @@ define void @rorv_i64() {
}
define void @asrv_i64() {
-; CHECK: asrv_i64:
+; CHECK-LABEL: asrv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = ashr i64 %val0_tmp, %val1_tmp
@@ -29,7 +29,7 @@ define void @asrv_i64() {
}
define void @lsrv_i64() {
-; CHECK: lsrv_i64:
+; CHECK-LABEL: lsrv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@@ -39,7 +39,7 @@ define void @lsrv_i64() {
}
define void @lslv_i64() {
-; CHECK: lslv_i64:
+; CHECK-LABEL: lslv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = shl i64 %val0_tmp, %val1_tmp
@@ -49,7 +49,7 @@ define void @lslv_i64() {
}
define void @udiv_i64() {
-; CHECK: udiv_i64:
+; CHECK-LABEL: udiv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = udiv i64 %val0_tmp, %val1_tmp
@@ -59,7 +59,7 @@ define void @udiv_i64() {
}
define void @sdiv_i64() {
-; CHECK: sdiv_i64:
+; CHECK-LABEL: sdiv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
@@ -70,7 +70,7 @@ define void @sdiv_i64() {
define void @lsrv_i32() {
-; CHECK: lsrv_i32:
+; CHECK-LABEL: lsrv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
@@ -81,7 +81,7 @@ define void @lsrv_i32() {
}
define void @lslv_i32() {
-; CHECK: lslv_i32:
+; CHECK-LABEL: lslv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
@@ -92,7 +92,7 @@ define void @lslv_i32() {
}
define void @rorv_i32() {
-; CHECK: rorv_i32:
+; CHECK-LABEL: rorv_i32:
%val0_tmp = load i32* @var32_0
%val6_tmp = load i32* @var32_1
%val1_tmp = add i32 1, %val6_tmp
@@ -106,7 +106,7 @@ define void @rorv_i32() {
}
define void @asrv_i32() {
-; CHECK: asrv_i32:
+; CHECK-LABEL: asrv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
@@ -117,7 +117,7 @@ define void @asrv_i32() {
}
define void @sdiv_i32() {
-; CHECK: sdiv_i32:
+; CHECK-LABEL: sdiv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
@@ -127,7 +127,7 @@ define void @sdiv_i32() {
}
define void @udiv_i32() {
-; CHECK: udiv_i32:
+; CHECK-LABEL: udiv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val4_tmp = udiv i32 %val0_tmp, %val1_tmp
Modified: llvm/trunk/test/CodeGen/AArch64/extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/extract.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/extract.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/extract.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i64 @ror_i64(i64 %in) {
-; CHECK: ror_i64:
+; CHECK-LABEL: ror_i64:
%left = shl i64 %in, 19
%right = lshr i64 %in, 45
%val5 = or i64 %left, %right
@@ -10,7 +10,7 @@ define i64 @ror_i64(i64 %in) {
}
define i32 @ror_i32(i32 %in) {
-; CHECK: ror_i32:
+; CHECK-LABEL: ror_i32:
%left = shl i32 %in, 9
%right = lshr i32 %in, 23
%val5 = or i32 %left, %right
@@ -19,7 +19,7 @@ define i32 @ror_i32(i32 %in) {
}
define i32 @extr_i32(i32 %lhs, i32 %rhs) {
-; CHECK: extr_i32:
+; CHECK-LABEL: extr_i32:
%left = shl i32 %lhs, 6
%right = lshr i32 %rhs, 26
%val = or i32 %left, %right
@@ -31,7 +31,7 @@ define i32 @extr_i32(i32 %lhs, i32 %rhs)
}
define i64 @extr_i64(i64 %lhs, i64 %rhs) {
-; CHECK: extr_i64:
+; CHECK-LABEL: extr_i64:
%right = lshr i64 %rhs, 40
%left = shl i64 %lhs, 24
%val = or i64 %right, %left
@@ -45,7 +45,7 @@ define i64 @extr_i64(i64 %lhs, i64 %rhs)
; Regression test: a bad experimental pattern crept into git which optimised
; this pattern to a single EXTR.
define i32 @extr_regress(i32 %a, i32 %b) {
-; CHECK: extr_regress:
+; CHECK-LABEL: extr_regress:
%sh1 = shl i32 %a, 14
%sh2 = lshr i32 %b, 14
Modified: llvm/trunk/test/CodeGen/AArch64/fastcc-reserved.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fastcc-reserved.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fastcc-reserved.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fastcc-reserved.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
declare fastcc void @will_pop([8 x i32], i32 %val)
define fastcc void @foo(i32 %in) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%addr = alloca i8, i32 %in
@@ -34,7 +34,7 @@ define fastcc void @foo(i32 %in) {
declare void @wont_pop([8 x i32], i32 %val)
define void @foo1(i32 %in) {
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
%addr = alloca i8, i32 %in
; Normal frame setup again
Modified: llvm/trunk/test/CodeGen/AArch64/fastcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fastcc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fastcc.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fastcc.ll Sun Jul 14 01:24:09 2013
@@ -5,10 +5,10 @@
; stack, so try to make sure this is respected.
define fastcc void @func_stack0() {
-; CHECK: func_stack0:
+; CHECK-LABEL: func_stack0:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack0:
+; CHECK-TAIL-LABEL: func_stack0:
; CHECK-TAIL: sub sp, sp, #48
@@ -45,10 +45,10 @@ define fastcc void @func_stack0() {
}
define fastcc void @func_stack8([8 x i32], i32 %stacked) {
-; CHECK: func_stack8:
+; CHECK-LABEL: func_stack8:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack8:
+; CHECK-TAIL-LABEL: func_stack8:
; CHECK-TAIL: sub sp, sp, #48
@@ -84,10 +84,10 @@ define fastcc void @func_stack8([8 x i32
}
define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
-; CHECK: func_stack32:
+; CHECK-LABEL: func_stack32:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack32:
+; CHECK-TAIL-LABEL: func_stack32:
; CHECK-TAIL: sub sp, sp, #48
Modified: llvm/trunk/test/CodeGen/AArch64/floatdp_1source.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/floatdp_1source.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/floatdp_1source.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/floatdp_1source.ll Sun Jul 14 01:24:09 2013
@@ -26,7 +26,7 @@ declare float @nearbyintf(float) readonl
declare double @nearbyint(double) readonly
define void @simple_float() {
-; CHECK: simple_float:
+; CHECK-LABEL: simple_float:
%val1 = load volatile float* @varfloat
%valabs = call float @fabsf(float %val1)
@@ -65,7 +65,7 @@ define void @simple_float() {
}
define void @simple_double() {
-; CHECK: simple_double:
+; CHECK-LABEL: simple_double:
%val1 = load volatile double* @vardouble
%valabs = call double @fabs(double %val1)
@@ -104,7 +104,7 @@ define void @simple_double() {
}
define void @converts() {
-; CHECK: converts:
+; CHECK-LABEL: converts:
%val16 = load volatile half* @varhalf
%val32 = load volatile float* @varfloat
Modified: llvm/trunk/test/CodeGen/AArch64/fp-dp3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp-dp3.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp-dp3.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp-dp3.ll Sun Jul 14 01:24:09 2013
@@ -46,7 +46,7 @@ define float @test_fnmsub(float %a, floa
define double @testd_fmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmadd:
-; CHECK-NOFAST: testd_fmadd:
+; CHECK-NOFAST-LABEL: testd_fmadd:
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -55,7 +55,7 @@ define double @testd_fmadd(double %a, do
define double @testd_fmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmsub:
-; CHECK-NOFAST: testd_fmsub:
+; CHECK-NOFAST-LABEL: testd_fmsub:
%nega = fsub double -0.0, %a
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -65,7 +65,7 @@ define double @testd_fmsub(double %a, do
define double @testd_fnmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmadd:
-; CHECK-NOFAST: testd_fnmadd:
+; CHECK-NOFAST-LABEL: testd_fnmadd:
%negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -75,7 +75,7 @@ define double @testd_fnmadd(double %a, d
define double @testd_fnmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmsub:
-; CHECK-NOFAST: testd_fnmsub:
+; CHECK-NOFAST-LABEL: testd_fnmsub:
%nega = fsub double -0.0, %a
%negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
Modified: llvm/trunk/test/CodeGen/AArch64/fpimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fpimm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fpimm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fpimm.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@varf64 = global double 0.0
define void @check_float() {
-; CHECK: check_float:
+; CHECK-LABEL: check_float:
%val = load float* @varf32
%newval1 = fadd float %val, 8.5
@@ -19,7 +19,7 @@ define void @check_float() {
}
define void @check_double() {
-; CHECK: check_double:
+; CHECK-LABEL: check_double:
%val = load double* @varf64
%newval1 = fadd double %val, 8.5
Modified: llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
@varstruct = global %myStruct zeroinitializer
define void @take_i8s(i8 %val1, i8 %val2) {
-; CHECK: take_i8s:
+; CHECK-LABEL: take_i8s:
store i8 %val2, i8* @var8
; Not using w1 may be technically allowed, but it would indicate a
; problem in itself.
@@ -20,7 +20,7 @@ define void @take_i8s(i8 %val1, i8 %val2
}
define void @add_floats(float %val1, float %val2) {
-; CHECK: add_floats:
+; CHECK-LABEL: add_floats:
%newval = fadd float %val1, %val2
; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
store float %newval, float* @varfloat
@@ -31,7 +31,7 @@ define void @add_floats(float %val1, flo
; byval pointers should be allocated to the stack and copied as if
; with memcpy.
define void @take_struct(%myStruct* byval %structval) {
-; CHECK: take_struct:
+; CHECK-LABEL: take_struct:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@@ -51,7 +51,7 @@ define void @take_struct(%myStruct* byva
; %structval should be at sp + 16
define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
-; CHECK: check_byval_align:
+; CHECK-LABEL: check_byval_align:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@@ -72,7 +72,7 @@ define void @check_byval_align(i32* byva
}
define i32 @return_int() {
-; CHECK: return_int:
+; CHECK-LABEL: return_int:
%val = load i32* @var32
ret i32 %val
; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
@@ -81,7 +81,7 @@ define i32 @return_int() {
}
define double @return_double() {
-; CHECK: return_double:
+; CHECK-LABEL: return_double:
ret double 3.14
; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
}
@@ -90,7 +90,7 @@ define double @return_double() {
; small enough to go into registers. Not all that pretty, but it
; works.
define [2 x i64] @return_struct() {
-; CHECK: return_struct:
+; CHECK-LABEL: return_struct:
%addr = bitcast %myStruct* @varstruct to [2 x i64]*
%val = load [2 x i64]* %addr
ret [2 x i64] %val
@@ -107,7 +107,7 @@ define [2 x i64] @return_struct() {
; structs larger than 16 bytes, but C semantics can still be provided
; if LLVM does it to %myStruct too. So this is the simplest check
define void @return_large_struct(%myStruct* sret %retval) {
-; CHECK: return_large_struct:
+; CHECK-LABEL: return_large_struct:
%addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
%addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
%addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
@@ -128,7 +128,7 @@ define void @return_large_struct(%myStru
define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
double %notstacked) {
-; CHECK: struct_on_stack:
+; CHECK-LABEL: struct_on_stack:
%addr = getelementptr %myStruct* %struct, i64 0, i32 0
%val64 = load i64* %addr
store i64 %val64, i64* @var64
@@ -148,7 +148,7 @@ define i32 @struct_on_stack(i8 %var0, i1
define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7,
float %var8) {
-; CHECK: stacked_fpu:
+; CHECK-LABEL: stacked_fpu:
store float %var8, float* @varfloat
; Beware as above: the offset would be different on big-endian
; machines if the first ldr were changed to use s-registers.
Modified: llvm/trunk/test/CodeGen/AArch64/func-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-calls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-calls.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-calls.ll Sun Jul 14 01:24:09 2013
@@ -17,7 +17,7 @@ declare void @take_i8s(i8 %val1, i8 %val
declare void @take_floats(float %val1, float %val2)
define void @simple_args() {
-; CHECK: simple_args:
+; CHECK-LABEL: simple_args:
%char1 = load i8* @var8
%char2 = load i8* @var8_2
call void @take_i8s(i8 %char1, i8 %char2)
@@ -41,7 +41,7 @@ declare [2 x i64] @return_smallstruct()
declare void @return_large_struct(%myStruct* sret %retval)
define void @simple_rets() {
-; CHECK: simple_rets:
+; CHECK-LABEL: simple_rets:
%int = call i32 @return_int()
store i32 %int, i32* @var32
@@ -106,7 +106,7 @@ declare void @check_i128_regalign(i32 %v
define void @check_i128_align() {
-; CHECK: check_i128_align:
+; CHECK-LABEL: check_i128_align:
%val = load i128* @var128
call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
i32 4, i32 5, i32 6, i32 7,
@@ -130,7 +130,7 @@ define void @check_i128_align() {
@fptr = global void()* null
define void @check_indirect_call() {
-; CHECK: check_indirect_call:
+; CHECK-LABEL: check_indirect_call:
%func = load void()** @fptr
call void %func()
; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]
Modified: llvm/trunk/test/CodeGen/AArch64/got-abuse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/got-abuse.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/got-abuse.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/got-abuse.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@ declare void @consume(i32)
declare void @func()
define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
entry:
call void @consume(i32 ptrtoint (void ()* @func to i32))
; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func
Modified: llvm/trunk/test/CodeGen/AArch64/i128-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/i128-align.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/i128-align.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/i128-align.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
@var = global %struct zeroinitializer
define i64 @check_size() {
-; CHECK: check_size:
+; CHECK-LABEL: check_size:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 1
@@ -17,7 +17,7 @@ define i64 @check_size() {
}
define i64 @check_field() {
-; CHECK: check_field:
+; CHECK-LABEL: check_field:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 0, i32 1
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-regoffset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-regoffset.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-regoffset.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-regoffset.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@
@var_double = global double 0.0
define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
%addr8_sxtw = getelementptr i8* %base, i32 %off32
%val8_sxtw = load volatile i8* %addr8_sxtw
@@ -37,7 +37,7 @@ define void @ldst_8bit(i8* %base, i32 %o
define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
%addr8_sxtwN = getelementptr i16* %base, i32 %off32
%val8_sxtwN = load volatile i16* %addr8_sxtwN
@@ -91,7 +91,7 @@ define void @ldst_16bit(i16* %base, i32
}
define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
%addr_sxtwN = getelementptr i32* %base, i32 %off32
%val_sxtwN = load volatile i32* %addr_sxtwN
@@ -143,7 +143,7 @@ define void @ldst_32bit(i32* %base, i32
}
define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_64bit:
+; CHECK-LABEL: ldst_64bit:
%addr_sxtwN = getelementptr i64* %base, i32 %off32
%val_sxtwN = load volatile i64* %addr_sxtwN
@@ -191,7 +191,7 @@ define void @ldst_64bit(i64* %base, i32
}
define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%addr_sxtwN = getelementptr float* %base, i32 %off32
%val_sxtwN = load volatile float* %addr_sxtwN
@@ -238,7 +238,7 @@ define void @ldst_float(float* %base, i3
}
define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%addr_sxtwN = getelementptr double* %base, i32 %off32
%val_sxtwN = load volatile double* %addr_sxtwN
@@ -286,7 +286,7 @@ define void @ldst_double(double* %base,
define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_128bit:
+; CHECK-LABEL: ldst_128bit:
%addr_sxtwN = getelementptr fp128* %base, i32 %off32
%val_sxtwN = load volatile fp128* %addr_sxtwN
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-unscaledimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-unscaledimm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-unscaledimm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-unscaledimm.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
@varptr = global i8* null
define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering.
@@ -72,7 +72,7 @@ define void @ldst_8bit() {
}
define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
; No architectural support for loads to 16-bit or 16-bit since we
; promote i16 during lowering.
@@ -140,7 +140,7 @@ define void @ldst_16bit() {
}
define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
%addr_8bit = load i8** @varptr
@@ -186,7 +186,7 @@ define void @ldst_32bit() {
}
define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
@@ -202,7 +202,7 @@ define void @ldst_float() {
}
define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 4
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-unsignedimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-unsignedimm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-unsignedimm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-unsignedimm.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@
@var_double = global double 0.0
define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering.
@@ -63,7 +63,7 @@ define void @ldst_8bit() {
}
define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
; No architectural support for load volatiles to 16-bit promote i16 during
; lowering.
@@ -117,7 +117,7 @@ define void @ldst_16bit() {
}
define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
; Straight 32-bit load/store
%val32_noext = load volatile i32* @var_32bit
@@ -225,7 +225,7 @@ define void @ldst_complex_offsets() {
}
define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%valfp = load volatile float* @var_float
; CHECK: adrp {{x[0-9]+}}, var_float
@@ -238,7 +238,7 @@ define void @ldst_float() {
}
define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%valfp = load volatile double* @var_double
; CHECK: adrp {{x[0-9]+}}, var_double
Modified: llvm/trunk/test/CodeGen/AArch64/literal_pools.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/literal_pools.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/literal_pools.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/literal_pools.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
@var64 = global i64 0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%val32 = load i32* @var32
%val64 = load i64* @var64
@@ -60,7 +60,7 @@ define void @foo() {
@vardouble = global double 0.0
define void @floating_lits() {
-; CHECK: floating_lits:
+; CHECK-LABEL: floating_lits:
%floatval = load float* @varfloat
%newfloat = fadd float %floatval, 128.0
Modified: llvm/trunk/test/CodeGen/AArch64/local_vars.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/local_vars.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/local_vars.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/local_vars.ll Sun Jul 14 01:24:09 2013
@@ -24,7 +24,7 @@ define void @trivial_func() nounwind {
}
define void @trivial_fp_func() {
-; CHECK-WITHFP: trivial_fp_func:
+; CHECK-WITHFP-LABEL: trivial_fp_func:
; CHECK-WITHFP: sub sp, sp, #16
; CHECK-WITHFP: stp x29, x30, [sp]
@@ -43,7 +43,7 @@ define void @trivial_fp_func() {
define void @stack_local() {
%local_var = alloca i64
-; CHECK: stack_local:
+; CHECK-LABEL: stack_local:
; CHECK: sub sp, sp, #16
%val = load i64* @var
Modified: llvm/trunk/test/CodeGen/AArch64/logical_shifted_reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/logical_shifted_reg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/logical_shifted_reg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/logical_shifted_reg.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
@var2_64 = global i64 0
define void @logical_32bit() {
-; CHECK: logical_32bit:
+; CHECK-LABEL: logical_32bit:
%val1 = load i32* @var1_32
%val2 = load i32* @var2_32
@@ -97,7 +97,7 @@ define void @logical_32bit() {
}
define void @logical_64bit() {
-; CHECK: logical_64bit:
+; CHECK-LABEL: logical_64bit:
%val1 = load i64* @var1_64
%val2 = load i64* @var2_64
@@ -190,7 +190,7 @@ define void @logical_64bit() {
}
define void @flag_setting() {
-; CHECK: flag_setting:
+; CHECK-LABEL: flag_setting:
%val1 = load i64* @var1_64
%val2 = load i64* @var2_64
Modified: llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
declare void @bar()
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%func = load void()** @var
; Calling a function encourages @foo to use a callee-saved register,
Modified: llvm/trunk/test/CodeGen/AArch64/sibling-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/sibling-call.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/sibling-call.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/sibling-call.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ declare void @callee_stack8([8 x i32], i
declare void @callee_stack16([8 x i32], i64, i64)
define void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB
tail call void @callee_stack0()
ret void
@@ -13,7 +13,7 @@ define void @caller_to0_from0() nounwind
}
define void @caller_to0_from8([8 x i32], i64) nounwind{
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
; CHECK-NEXT: // BB
tail call void @callee_stack0()
@@ -22,7 +22,7 @@ define void @caller_to0_from8([8 x i32],
}
define void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
; Caller isn't going to clean up any extra stack we allocate, so it
; can't be a tail call.
@@ -32,7 +32,7 @@ define void @caller_to8_from0() {
}
define void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
; CHECK-NOT: sub sp, sp,
; This should reuse our stack area for the 42
@@ -43,7 +43,7 @@ define void @caller_to8_from8([8 x i32],
}
define void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
; Shouldn't be a tail call: we can't use SP+8 because our caller might
; have something there. This may sound obvious but implementation does
@@ -54,7 +54,7 @@ define void @caller_to16_from8([8 x i32]
}
define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
; CHECK-NOT: sub sp, sp
; Reuse our area, putting "42" at incoming sp
@@ -65,7 +65,7 @@ define void @caller_to8_from24([8 x i32]
}
define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
; CHECK-NOT: sub sp, sp,
; Here we want to make sure that both loads happen before the stores:
@@ -85,7 +85,7 @@ define void @caller_to16_from16([8 x i32
@func = global void(i32)* null
define void @indirect_tail() {
-; CHECK: indirect_tail:
+; CHECK-LABEL: indirect_tail:
; CHECK-NOT: sub sp, sp
%fptr = load void(i32)** @func
Modified: llvm/trunk/test/CodeGen/AArch64/tail-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tail-call.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/tail-call.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/tail-call.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ declare fastcc void @callee_stack8([8 x
declare fastcc void @callee_stack16([8 x i32], i64, i64)
define fastcc void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB
tail call fastcc void @callee_stack0()
ret void
@@ -13,7 +13,7 @@ define fastcc void @caller_to0_from0() n
}
define fastcc void @caller_to0_from8([8 x i32], i64) {
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
tail call fastcc void @callee_stack0()
ret void
@@ -22,7 +22,7 @@ define fastcc void @caller_to0_from8([8
}
define fastcc void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
; CHECK: sub sp, sp, #32
; Key point is that the "42" should go #16 below incoming stack
@@ -35,7 +35,7 @@ define fastcc void @caller_to8_from0() {
}
define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at SP on entry.
@@ -47,7 +47,7 @@ define fastcc void @caller_to8_from8([8
}
define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
; CHECK: sub sp, sp, #16
; Important point is that the call reuses the "dead" argument space
@@ -63,7 +63,7 @@ define fastcc void @caller_to16_from8([8
define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at #16 above SP on entry.
@@ -76,7 +76,7 @@ define fastcc void @caller_to8_from24([8
define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
; CHECK: sub sp, sp, #16
; Here we want to make sure that both loads happen before the stores:
Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
-; CHECK: dct_luma_sp:
+; CHECK-LABEL: dct_luma_sp:
define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
entry:
; Make sure to use base-updating stores for saving callee-saved registers.
Modified: llvm/trunk/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; pr4843
define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
-;CHECK: v2regbug:
+;CHECK-LABEL: v2regbug:
;CHECK: vzip.16
%tmp1 = load <4 x i16>* %B
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
Modified: llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
%0 = type { double, double }
define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: bl __aeabi_dadd
; CHECK-NOT: strd
; CHECK: mov
Modified: llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@ entry:
%3 = fmul float %0, %1 ; <float> [#uses=1]
%4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
%5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
%6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
%7 = fsub float %2, undef ; <float> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll Sun Jul 14 01:24:09 2013
@@ -6,10 +6,10 @@
define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: str r2, [r1], r0
-; THUMB: t:
+; THUMB-LABEL: t:
; THUMB-NOT: str r0, [r1], r0
; THUMB: str r1, [r0]
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
define i32* @t(i32* %x) nounwind {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: push
; ARM: mov r7, sp
; ARM: bl _foo
@@ -12,7 +12,7 @@ entry:
; ARM: bl _foo
; ARM: pop {r7, pc}
-; THUMB2: t:
+; THUMB2-LABEL: t:
; THUMB2: push
; THUMB2: mov r7, sp
; THUMB2: blx _foo
Modified: llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
define hidden void @foo() nounwind ssp {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vpush {d10, d11}
Modified: llvm/trunk/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@
@oStruct = external global %struct.Outer, align 4
define void @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK-NOT: ldrd
; CHECK: mul
for.body.lr.ph:
Modified: llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@
; rdar://9172742
define i32 @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
br label %bb2
Modified: llvm/trunk/test/CodeGen/ARM/2011-04-07-schediv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-04-07-schediv.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-04-07-schediv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-04-07-schediv.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@ entry:
; Make sure the scheduler schedules all uses of the preincrement
; induction variable before defining the postincrement value.
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: %bb
; CHECK-NOT: mov
bb: ; preds = %entry, %bb
Modified: llvm/trunk/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; rdar://9266679
define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
br label %for.cond
Modified: llvm/trunk/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@
@infoBlock = external global %struct.InformationBlock
define hidden void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldr.w
; CHECK: ldr.w
; CHECK-NOT: ldm
Modified: llvm/trunk/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll Sun Jul 14 01:24:09 2013
@@ -23,7 +23,7 @@
;
; rdar://11116189
define i64 @t(i64 %aInput) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movs [[REG:(r[0-9]+)]], #0
; CHECK: movt [[REG]], #46540
; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
Modified: llvm/trunk/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; v4i8
;
define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
-;CHECK: sextload_v4i8_c:
+;CHECK-LABEL: sextload_v4i8_c:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
@@ -26,7 +26,7 @@ entry:
; v2i8
;
define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
-;CHECK: sextload_v2i8_c:
+;CHECK-LABEL: sextload_v2i8_c:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
@@ -39,7 +39,7 @@ entry:
; v2i16
;
define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
-;CHECK: sextload_v2i16_c:
+;CHECK-LABEL: sextload_v2i16_c:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
@@ -54,7 +54,7 @@ entry:
; v4i8
;
define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
-;CHECK: sextload_v4i8_v:
+;CHECK-LABEL: sextload_v4i8_v:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
@@ -70,7 +70,7 @@ entry:
; v2i8
;
define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
-;CHECK: sextload_v2i8_v:
+;CHECK-LABEL: sextload_v2i8_v:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
@@ -86,7 +86,7 @@ entry:
; v2i16
;
define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i16_v:
+;CHECK-LABEL: sextload_v2i16_v:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
@@ -104,7 +104,7 @@ entry:
; v4i8 x v4i16
;
define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
-;CHECK: sextload_v4i8_vs:
+;CHECK-LABEL: sextload_v4i8_vs:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
@@ -120,7 +120,7 @@ entry:
; v2i8
; v2i8 x v2i16
define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i8_vs:
+;CHECK-LABEL: sextload_v2i8_vs:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
@@ -136,7 +136,7 @@ entry:
; v2i16
; v2i16 x v2i32
define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
-;CHECK: sextload_v2i16_vs:
+;CHECK-LABEL: sextload_v2i16_vs:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
Modified: llvm/trunk/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; rdar://12300648
define i32 @t(i32 %x) {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: movw
%tmp = add i32 %x, -65535
ret i32 %tmp
Modified: llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll Sun Jul 14 01:24:09 2013
@@ -23,7 +23,7 @@ entry:
ret void
}
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything.
@@ -53,7 +53,7 @@ entry:
ret void
}
-; CHECK: main_fixed_arg:
+; CHECK-LABEL: main_fixed_arg:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything.
Modified: llvm/trunk/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
-; CHECK: main:
+; CHECK-LABEL: main:
define i32 @main() nounwind {
entry:
; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
Modified: llvm/trunk/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
declare void @f(%struct.s* %p);
-; CHECK: t:
+; CHECK-LABEL: t:
define void @t(i32 %a, %struct.s* byval %s) nounwind {
entry:
@@ -20,7 +20,7 @@ entry:
ret void
}
-; CHECK: caller:
+; CHECK-LABEL: caller:
define void @caller() {
; CHECK: ldm r0, {r1, r2, r3}
Modified: llvm/trunk/test/CodeGen/ARM/2013-01-21-PR14992.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-01-21-PR14992.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-01-21-PR14992.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-01-21-PR14992.ll Sun Jul 14 01:24:09 2013
@@ -2,8 +2,8 @@
;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
-;EXPECTED: foo:
-;CHECK: foo:
+;EXPECTED-LABEL: foo:
+;CHECK-LABEL: foo:
define i32 @foo(i32* %a) nounwind optsize {
entry:
%0 = load i32* %a, align 4
Modified: llvm/trunk/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-02-27-expand-vfma.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-02-27-expand-vfma.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-02-27-expand-vfma.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
-; CHECK: muladd:
+; CHECK-LABEL: muladd:
; CHECK: fmaf
; CHECK: fmaf
; CHECK: fmaf
@@ -17,7 +17,7 @@ define <4 x float> @muladd(<4 x float> %
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
-; CHECK: muladd2:
+; CHECK-LABEL: muladd2:
; CHECK: fmaf
; CHECK: fmaf
; CHECK-NOT: fmaf
Modified: llvm/trunk/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
-;CHECK: foo:
+;CHECK-LABEL: foo:
;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8]
@@ -11,7 +11,7 @@
;CHECK: add sp, sp, #8
;CHECK: mov pc, lr
-;CHECK: foo2:
+;CHECK-LABEL: foo2:
;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8]
@@ -24,7 +24,7 @@
;CHECK: add sp, sp, #8
;CHECK: mov pc, lr
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
;CHECK: push {r11, lr}
;CHECK: ldr r0,
;CHECK: ldr r0, [r0]
@@ -33,7 +33,7 @@
;CHECK: mov pc, lr
-;CHECK: doFoo2:
+;CHECK-LABEL: doFoo2:
;CHECK: push {r11, lr}
;CHECK: ldr r0,
;CHECK: mov r1, #0
Modified: llvm/trunk/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll Sun Jul 14 01:24:09 2013
@@ -53,11 +53,11 @@
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
;
-;CHECK: foo:
+;CHECK-LABEL: foo:
;CHECK-NOT: mov r0
;CHECK-NOT: ldr r0
;CHECK: bl fooUseI32
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
;CHECK: movs r0, #43
;CHECK: bl foo
Modified: llvm/trunk/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@
@.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
-;CHECK: printfn:
+;CHECK-LABEL: printfn:
define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
entry:
%conv = sext i16 %b to i32
Modified: llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; rdar://13782395
define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
store i8* blockaddress(@t1, %cond_true), i8** %retaddr
@@ -19,7 +19,7 @@ cond_false:
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: Block address taken
; CHECK: %cond_true
; CHECK: add
@@ -41,7 +41,7 @@ UnifiedReturnBlock:
}
define hidden fastcc void @t3(i8** %retaddr) {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
bb:
Modified: llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll Sun Jul 14 01:24:09 2013
@@ -1,8 +1,8 @@
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
-; CHECK-ENABLED: t1:
-; CHECK-DISABLED: t1:
+; CHECK-ENABLED-LABEL: t1:
+; CHECK-DISABLED-LABEL: t1:
define <2 x float> @t1(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -11,8 +11,8 @@ define <2 x float> @t1(float %f) {
ret <2 x float> %i2
}
-; CHECK-ENABLED: t2:
-; CHECK-DISABLED: t2:
+; CHECK-ENABLED-LABEL: t2:
+; CHECK-DISABLED-LABEL: t2:
define <4 x float> @t2(float %g, float %f) {
; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -21,8 +21,8 @@ define <4 x float> @t2(float %g, float %
ret <4 x float> %i2
}
-; CHECK-ENABLED: t3:
-; CHECK-DISABLED: t3:
+; CHECK-ENABLED-LABEL: t3:
+; CHECK-DISABLED-LABEL: t3:
define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -31,8 +31,8 @@ define arm_aapcs_vfpcc <2 x float> @t3(f
ret <2 x float> %i2
}
-; CHECK-ENABLED: t4:
-; CHECK-DISABLED: t4:
+; CHECK-ENABLED-LABEL: t4:
+; CHECK-DISABLED-LABEL: t4:
define <2 x float> @t4(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup
@@ -45,8 +45,8 @@ b:
ret <2 x float> %i2
}
-; CHECK-ENABLED: t5:
-; CHECK-DISABLED: t5:
+; CHECK-ENABLED-LABEL: t5:
+; CHECK-DISABLED-LABEL: t5:
define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
; CHECK-ENABLED: vadd.f32
Modified: llvm/trunk/test/CodeGen/ARM/a15-partial-update.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/a15-partial-update.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/a15-partial-update.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/a15-partial-update.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
-; CHECK: t1:
+; CHECK-LABEL: t1:
define <2 x float> @t1(float* %A, <2 x float> %B) {
; The generated code for this test uses a vld1.32 instruction
; to write the lane 1 of a D register containing the value of
@@ -15,7 +15,7 @@ define <2 x float> @t1(float* %A, <2 x f
ret <2 x float> %tmp3
}
-; CHECK: t2:
+; CHECK-LABEL: t2:
define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
entry:
br label %loop
Modified: llvm/trunk/test/CodeGen/ARM/arguments.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arguments.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arguments.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arguments.ll Sun Jul 14 01:24:09 2013
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
define i32 @f1(i32 %a, i64 %b) {
-; ELF: f1:
+; ELF-LABEL: f1:
; ELF: mov r0, r2
-; DARWIN: f1:
+; DARWIN-LABEL: f1:
; DARWIN: mov r0, r1
%tmp = call i32 @g1(i64 %b)
ret i32 %tmp
@@ -12,10 +12,10 @@ define i32 @f1(i32 %a, i64 %b) {
; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
define i32 @f2() nounwind optsize {
-; ELF: f2:
+; ELF-LABEL: f2:
; ELF: mov [[REGISTER:(r[0-9]+)]], #128
; ELF: str [[REGISTER]], [
-; DARWIN: f2:
+; DARWIN-LABEL: f2:
; DARWIN: mov r3, #128
entry:
%0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
@@ -26,10 +26,10 @@ entry:
; test that on gnueabi a 64 bit value at this position will cause r3 to go
; unused and the value stored in [sp]
-; ELF: f3:
+; ELF-LABEL: f3:
; ELF: ldr r0, [sp]
; ELF-NEXT: mov pc, lr
-; DARWIN: f3:
+; DARWIN-LABEL: f3:
; DARWIN: mov r0, r3
; DARWIN-NEXT: mov pc, lr
define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
Modified: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Sun Jul 14 01:24:09 2013
@@ -5,10 +5,10 @@
define i8* @t() nounwind {
entry:
-; DARWIN: t:
+; DARWIN-LABEL: t:
; DARWIN: mov r0, r7
-; LINUX: t:
+; LINUX-LABEL: t:
; LINUX: mov r0, r11
%0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0
Modified: llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
define i8* @rt0(i32 %x) nounwind readnone {
entry:
-; CHECK: rt0:
+; CHECK-LABEL: rt0:
; CHECK: {r7, lr}
; CHECK: mov r0, lr
%0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -16,7 +16,7 @@ entry:
define i8* @rt2() nounwind readnone {
entry:
-; CHECK: rt2:
+; CHECK-LABEL: rt2:
; CHECK: {r7, lr}
; CHECK: ldr r[[R0:[0-9]+]], [r7]
; CHECK: ldr r0, [r0]
Modified: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test1:
+; CHECK-THUMB-LABEL: test1:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -37,7 +37,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test2:
+; CHECK-THUMB-LABEL: test2:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -62,7 +62,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test3:
+; CHECK-THUMB-LABEL: test3:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -87,7 +87,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test4:
+; CHECK-THUMB-LABEL: test4:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -112,7 +112,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test5:
+; CHECK-THUMB-LABEL: test5:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -135,7 +135,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test6:
+; CHECK-THUMB-LABEL: test6:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@@ -159,7 +159,7 @@ define i64 @test7(i64* %ptr, i64 %val1,
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test7:
+; CHECK-THUMB-LABEL: test7:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]]
@@ -188,7 +188,7 @@ define i64 @test8(i64* %ptr) {
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test8:
+; CHECK-THUMB-LABEL: test8:
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]]
; CHECK-THUMB: it eq
@@ -214,7 +214,7 @@ define void @test9(i64* %ptr, i64 %val)
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test9:
+; CHECK-THUMB-LABEL: test9:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@@ -238,7 +238,7 @@ define i64 @test10(i64* %ptr, i64 %val)
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test10:
+; CHECK-THUMB-LABEL: test10:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -266,7 +266,7 @@ define i64 @test11(i64* %ptr, i64 %val)
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test11:
+; CHECK-THUMB-LABEL: test11:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -293,7 +293,7 @@ define i64 @test12(i64* %ptr, i64 %val)
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test12:
+; CHECK-THUMB-LABEL: test12:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -320,7 +320,7 @@ define i64 @test13(i64* %ptr, i64 %val)
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test13:
+; CHECK-THUMB-LABEL: test13:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll Sun Jul 14 01:24:09 2013
@@ -3,11 +3,11 @@
; rdar://8964854
define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
-; ARM: t:
+; ARM-LABEL: t:
; ARM: ldrexb
; ARM: strexb
-; T2: t:
+; T2-LABEL: t:
; T2: ldrexb
; T2: strexb
%tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic
Modified: llvm/trunk/test/CodeGen/ARM/atomicrmw_minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomicrmw_minmax.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomicrmw_minmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomicrmw_minmax.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
-; CHECK: max:
+; CHECK-LABEL: max:
define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
{
; CHECK: ldrex
@@ -10,7 +10,7 @@ define i32 @max(i8 %ctx, i32* %ptr, i32
ret i32 %old
}
-; CHECK: min:
+; CHECK-LABEL: min:
define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
{
; CHECK: ldrex
Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
@@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i
; rdar://10357570
define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
%tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body
@@ -54,7 +54,7 @@ while.end:
; rdar://12878928
define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
%tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body
Modified: llvm/trunk/test/CodeGen/ARM/bfc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/bfc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/bfc.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: bfc
%tmp = and i32 %a, 4278190095
ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
; 4286578688 = 0xff800000
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bfc
%tmp = and i32 %a, 4286578688
ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
; 4095 = 0x00000fff
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: bfc
%tmp = and i32 %a, 4095
ret i32 %tmp
Modified: llvm/trunk/test/CodeGen/ARM/bfi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfi.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/bfi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/bfi.ll Sun Jul 14 01:24:09 2013
@@ -52,7 +52,7 @@ define i32 @f4(i32 %a) nounwind {
; rdar://8458663
define i32 @f5(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: bfc
; CHECK: bfi r0, r1, #20, #4
%0 = and i32 %a, -15728641
@@ -65,7 +65,7 @@ entry:
; rdar://9609030
define i32 @f6(i32 %a, i32 %b) nounwind readnone {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: bic
; CHECK: bfi r0, r1, #8, #9
%and = and i32 %a, -130817
Modified: llvm/trunk/test/CodeGen/ARM/bswap-inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bswap-inline-asm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/bswap-inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/bswap-inline-asm.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
define i32 @t1(i32 %x) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK-NOT: InlineAsm
; CHECK: rev
%asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
Modified: llvm/trunk/test/CodeGen/ARM/call-noret-minsize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-noret-minsize.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/call-noret-minsize.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/call-noret-minsize.ll Sun Jul 14 01:24:09 2013
@@ -4,10 +4,10 @@
define void @t1() noreturn minsize nounwind ssp {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: bl _bar
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: bl _bar
tail call void @bar() noreturn nounwind
unreachable
@@ -15,10 +15,10 @@ entry:
define void @t2() noreturn minsize nounwind ssp {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: bl _t1
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
; SWIFT: bl _t1
tail call void @t1() noreturn nounwind
unreachable
Modified: llvm/trunk/test/CodeGen/ARM/call-noret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-noret.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/call-noret.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/call-noret.ll Sun Jul 14 01:24:09 2013
@@ -4,11 +4,11 @@
define void @t1() noreturn nounwind ssp {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: mov lr, pc
; ARM: b _bar
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: mov lr, pc
; SWIFT: b _bar
tail call void @bar() noreturn nounwind
@@ -17,11 +17,11 @@ entry:
define void @t2() noreturn nounwind ssp {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: mov lr, pc
; ARM: b _t1
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
; SWIFT: mov lr, pc
; SWIFT: b _t1
tail call void @t1() noreturn nounwind
Modified: llvm/trunk/test/CodeGen/ARM/call-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/call-tc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/call-tc.ll Sun Jul 14 01:24:09 2013
@@ -11,16 +11,16 @@
declare void @g(i32, i32, i32, i32)
define void @t1() {
-; CHECKELF: t1:
+; CHECKELF-LABEL: t1:
; CHECKELF: bl g(PLT)
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
define void @t2() {
-; CHECKV6: t2:
+; CHECKV6-LABEL: t2:
; CHECKV6: bx r0
-; CHECKT2D: t2:
+; CHECKT2D-LABEL: t2:
; CHECKT2D: ldr
; CHECKT2D-NEXT: ldr
; CHECKT2D-NEXT: bx r0
@@ -30,11 +30,11 @@ define void @t2() {
}
define void @t3() {
-; CHECKV6: t3:
+; CHECKV6-LABEL: t3:
; CHECKV6: b _t2
-; CHECKELF: t3:
+; CHECKELF-LABEL: t3:
; CHECKELF: b t2(PLT)
-; CHECKT2D: t3:
+; CHECKT2D-LABEL: t3:
; CHECKT2D: b.w _t2
tail call void @t2( ) ; <i32> [#uses=0]
@@ -44,9 +44,9 @@ define void @t3() {
; Sibcall optimization of expanded libcalls. rdar://8707777
define double @t4(double %a) nounwind readonly ssp {
entry:
-; CHECKV6: t4:
+; CHECKV6-LABEL: t4:
; CHECKV6: b _sin
-; CHECKELF: t4:
+; CHECKELF-LABEL: t4:
; CHECKELF: b sin(PLT)
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0
@@ -54,9 +54,9 @@ entry:
define float @t5(float %a) nounwind readonly ssp {
entry:
-; CHECKV6: t5:
+; CHECKV6-LABEL: t5:
; CHECKV6: b _sinf
-; CHECKELF: t5:
+; CHECKELF-LABEL: t5:
; CHECKELF: b sinf(PLT)
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0
@@ -68,9 +68,9 @@ declare double @sin(double) nounwind rea
define i32 @t6(i32 %a, i32 %b) nounwind readnone {
entry:
-; CHECKV6: t6:
+; CHECKV6-LABEL: t6:
; CHECKV6: b ___divsi3
-; CHECKELF: t6:
+; CHECKELF-LABEL: t6:
; CHECKELF: b __aeabi_idiv(PLT)
%0 = sdiv i32 %a, %b
ret i32 %0
@@ -82,7 +82,7 @@ declare void @foo() nounwind
define void @t7() nounwind {
entry:
-; CHECKT2D: t7:
+; CHECKT2D-LABEL: t7:
; CHECKT2D: blxeq _foo
; CHECKT2D-NEXT: pop.w
; CHECKT2D-NEXT: b.w _foo
@@ -101,7 +101,7 @@ bb:
; rdar://11140249
define i32 @t8(i32 %x) nounwind ssp {
entry:
-; CHECKT2D: t8:
+; CHECKT2D-LABEL: t8:
; CHECKT2D-NOT: push
%and = and i32 %x, 1
%tobool = icmp eq i32 %and, 0
@@ -147,7 +147,7 @@ declare i32 @c(i32)
@x = external global i32, align 4
define i32 @t9() nounwind {
-; CHECKT2D: t9:
+; CHECKT2D-LABEL: t9:
; CHECKT2D: blx __ZN9MutexLockC1Ev
; CHECKT2D: blx __ZN9MutexLockD1Ev
; CHECKT2D: b.w ___divsi3
@@ -167,7 +167,7 @@ declare %class.MutexLock* @_ZN9MutexLock
; Correctly preserve the input chain for the tailcall node in the bitcast case,
; otherwise the call to floorf is lost.
define float @libcall_tc_test2(float* nocapture %a, float %b) {
-; CHECKT2D: libcall_tc_test2:
+; CHECKT2D-LABEL: libcall_tc_test2:
; CHECKT2D: blx _floorf
; CHECKT2D: b.w _truncf
%1 = load float* %a, align 4
Modified: llvm/trunk/test/CodeGen/ARM/call_nolink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call_nolink.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/call_nolink.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/call_nolink.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
@numi = external global i32 ; <i32*> [#uses=1]
@counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
-; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
+; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
; CHECK-NOT: bx lr
define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
@@ -56,7 +56,7 @@ define void @PR15520(void ()* %fn) {
call void %fn()
ret void
-; CHECK: PR15520:
+; CHECK-LABEL: PR15520:
; CHECK: mov lr, pc
; CHECK: mov pc, r0
}
Modified: llvm/trunk/test/CodeGen/ARM/carry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/carry.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/carry.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs r
; CHECK: sbc r
entry:
@@ -10,7 +10,7 @@ entry:
}
define i64 @f2(i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adc r
; CHECK: subs r
; CHECK: sbc r
@@ -22,7 +22,7 @@ entry:
; add with live carry
define i64 @f3(i32 %al, i32 %bl) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: adds r
; CHECK: adc r
entry:
@@ -39,7 +39,7 @@ entry:
; rdar://10073745
define i64 @f4(i64 %x) nounwind readnone {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rsbs r
; CHECK: rsc r
%0 = sub nsw i64 0, %x
@@ -49,7 +49,7 @@ entry:
; rdar://12559385
define i64 @f5(i32 %vi) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64
Modified: llvm/trunk/test/CodeGen/ARM/code-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/code-placement.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/code-placement.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/code-placement.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
%0 = icmp eq %struct.list_head* %list, null
br i1 %0, label %bb2, label %bb
@@ -33,7 +33,7 @@ bb2:
; rdar://8117827
define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: beq LBB1_[[RET:.]]
%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb.nph15
Modified: llvm/trunk/test/CodeGen/ARM/ctz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ctz.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ctz.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ctz.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
declare i32 @llvm.cttz.i32(i32, i1)
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rbit
; CHECK: clz
%tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
Modified: llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-; CHECK: f:
+; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) {
; CHECK: vldr
; CHECK: vmovl.u16
Modified: llvm/trunk/test/CodeGen/ARM/data-in-code-annotations.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/data-in-code-annotations.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/data-in-code-annotations.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/data-in-code-annotations.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
define double @f1() nounwind {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .data_region
; CHECK: .long 1413754129
; CHECK: .long 1074340347
@@ -11,7 +11,7 @@ define double @f1() nounwind {
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .data_region jt32
; CHECK: .end_data_region
Modified: llvm/trunk/test/CodeGen/ARM/divmod.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/divmod.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/divmod.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/divmod.ll Sun Jul 14 01:24:09 2013
@@ -5,11 +5,11 @@
define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry:
-; A8: foo:
+; A8-LABEL: foo:
; A8: bl ___divmodsi4
; A8-NOT: bl ___divmodsi4
-; SWIFT: foo:
+; SWIFT-LABEL: foo:
; SWIFT: sdiv
; SWIFT: mls
; SWIFT-NOT: bl __divmodsi4
@@ -23,11 +23,11 @@ entry:
define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry:
-; A8: bar:
+; A8-LABEL: bar:
; A8: bl ___udivmodsi4
; A8-NOT: bl ___udivmodsi4
-; SWIFT: bar:
+; SWIFT-LABEL: bar:
; SWIFT: udiv
; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4
@@ -45,8 +45,8 @@ entry:
define void @do_indent(i32 %cols) nounwind {
entry:
-; A8: do_indent:
-; SWIFT: do_indent:
+; A8-LABEL: do_indent:
+; SWIFT-LABEL: do_indent:
%0 = load i32* @flags, align 4
%1 = and i32 %0, 67108864
%2 = icmp eq i32 %1, 0
@@ -77,11 +77,11 @@ declare i8* @__memset_chk(i8*, i32, i32,
; rdar://11714607
define i32 @howmany(i32 %x, i32 %y) nounwind {
entry:
-; A8: howmany:
+; A8-LABEL: howmany:
; A8: bl ___udivmodsi4
; A8-NOT: ___udivsi3
-; SWIFT: howmany:
+; SWIFT-LABEL: howmany:
; SWIFT: udiv
; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4
Modified: llvm/trunk/test/CodeGen/ARM/ehabi-filters.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ehabi-filters.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ehabi-filters.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ehabi-filters.ll Sun Jul 14 01:24:09 2013
@@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*)
declare void @__cxa_call_unexpected(i8*)
define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
entry:
%exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
%0 = bitcast i8* %exception.i to i32*
Modified: llvm/trunk/test/CodeGen/ARM/ehabi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ehabi.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ehabi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ehabi.ll Sun Jul 14 01:24:09 2013
@@ -112,7 +112,7 @@ declare void @__cxa_end_catch()
declare void @_ZSt9terminatev()
-; CHECK-FP: _Z4testiiiiiddddd:
+; CHECK-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -124,7 +124,7 @@ declare void @_ZSt9terminatev()
; CHECK-FP: .handlerdata
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -134,7 +134,7 @@ declare void @_ZSt9terminatev()
; CHECK-FP-ELIM: .handlerdata
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: _Z4testiiiiiddddd:
+; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r11, lr}
; CHECK-V7-FP: push {r4, r11, lr}
@@ -148,7 +148,7 @@ declare void @_ZSt9terminatev()
; CHECK-V7-FP: .handlerdata
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, lr}
; CHECK-V7-FP-ELIM: push {r4, lr}
@@ -173,7 +173,7 @@ entry:
ret void
}
-; CHECK-FP: test2:
+; CHECK-FP-LABEL: test2:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r11, lr}
; CHECK-FP: push {r11, lr}
@@ -183,7 +183,7 @@ entry:
; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test2:
+; CHECK-FP-ELIM-LABEL: test2:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r11, lr}
; CHECK-FP-ELIM: push {r11, lr}
@@ -191,7 +191,7 @@ entry:
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test2:
+; CHECK-V7-FP-LABEL: test2:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r11, lr}
; CHECK-V7-FP: push {r11, lr}
@@ -200,7 +200,7 @@ entry:
; CHECK-V7-FP: pop {r11, pc}
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test2:
+; CHECK-V7-FP-ELIM-LABEL: test2:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r11, lr}
; CHECK-V7-FP-ELIM: push {r11, lr}
@@ -229,7 +229,7 @@ entry:
ret i32 %add6
}
-; CHECK-FP: test3:
+; CHECK-FP-LABEL: test3:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r11, lr}
; CHECK-FP: push {r4, r5, r11, lr}
@@ -239,7 +239,7 @@ entry:
; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test3:
+; CHECK-FP-ELIM-LABEL: test3:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r11, lr}
@@ -247,7 +247,7 @@ entry:
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test3:
+; CHECK-V7-FP-LABEL: test3:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r5, r11, lr}
; CHECK-V7-FP: push {r4, r5, r11, lr}
@@ -256,7 +256,7 @@ entry:
; CHECK-V7-FP: pop {r4, r5, r11, pc}
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test3:
+; CHECK-V7-FP-ELIM-LABEL: test3:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr}
@@ -273,25 +273,25 @@ entry:
ret void
}
-; CHECK-FP: test4:
+; CHECK-FP-LABEL: test4:
; CHECK-FP: .fnstart
; CHECK-FP: mov pc, lr
; CHECK-FP: .cantunwind
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test4:
+; CHECK-FP-ELIM-LABEL: test4:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .cantunwind
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test4:
+; CHECK-V7-FP-LABEL: test4:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: bx lr
; CHECK-V7-FP: .cantunwind
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test4:
+; CHECK-V7-FP-ELIM-LABEL: test4:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: bx lr
; CHECK-V7-FP-ELIM: .cantunwind
Modified: llvm/trunk/test/CodeGen/ARM/extload-knownzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/extload-knownzero.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/extload-knownzero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/extload-knownzero.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll Sun Jul 14 01:24:09 2013
@@ -4,8 +4,8 @@
define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
entry:
-; THUMB: t1:
-; ARM: t1:
+; THUMB-LABEL: t1:
+; ARM-LABEL: t1:
%x = add i32 %a, %b
br i1 1, label %if.then, label %if.else
; THUMB-NOT: b {{\.?}}LBB0_1
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ext.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ext.ll Sun Jul 14 01:24:09 2013
@@ -17,54 +17,54 @@
; zext
define i8 @zext_1_8(i1 %a) nounwind ssp {
-; v7: zext_1_8:
+; v7-LABEL: zext_1_8:
; v7: and r0, r0, #1
-; prev6: zext_1_8:
+; prev6-LABEL: zext_1_8:
; prev6: and r0, r0, #1
%r = zext i1 %a to i8
ret i8 %r
}
define i16 @zext_1_16(i1 %a) nounwind ssp {
-; v7: zext_1_16:
+; v7-LABEL: zext_1_16:
; v7: and r0, r0, #1
-; prev6: zext_1_16:
+; prev6-LABEL: zext_1_16:
; prev6: and r0, r0, #1
%r = zext i1 %a to i16
ret i16 %r
}
define i32 @zext_1_32(i1 %a) nounwind ssp {
-; v7: zext_1_32:
+; v7-LABEL: zext_1_32:
; v7: and r0, r0, #1
-; prev6: zext_1_32:
+; prev6-LABEL: zext_1_32:
; prev6: and r0, r0, #1
%r = zext i1 %a to i32
ret i32 %r
}
define i16 @zext_8_16(i8 %a) nounwind ssp {
-; v7: zext_8_16:
+; v7-LABEL: zext_8_16:
; v7: and r0, r0, #255
-; prev6: zext_8_16:
+; prev6-LABEL: zext_8_16:
; prev6: and r0, r0, #255
%r = zext i8 %a to i16
ret i16 %r
}
define i32 @zext_8_32(i8 %a) nounwind ssp {
-; v7: zext_8_32:
+; v7-LABEL: zext_8_32:
; v7: and r0, r0, #255
-; prev6: zext_8_32:
+; prev6-LABEL: zext_8_32:
; prev6: and r0, r0, #255
%r = zext i8 %a to i32
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind ssp {
-; v7: zext_16_32:
+; v7-LABEL: zext_16_32:
; v7: uxth r0, r0
-; prev6: zext_16_32:
+; prev6-LABEL: zext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: lsr{{s?}} r0, r0, #16
%r = zext i16 %a to i32
@@ -74,10 +74,10 @@ define i32 @zext_16_32(i16 %a) nounwind
; sext
define i8 @sext_1_8(i1 %a) nounwind ssp {
-; v7: sext_1_8:
+; v7-LABEL: sext_1_8:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_8:
+; prev6-LABEL: sext_1_8:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i8
@@ -85,10 +85,10 @@ define i8 @sext_1_8(i1 %a) nounwind ssp
}
define i16 @sext_1_16(i1 %a) nounwind ssp {
-; v7: sext_1_16:
+; v7-LABEL: sext_1_16:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_16:
+; prev6-LABEL: sext_1_16:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i16
@@ -96,10 +96,10 @@ define i16 @sext_1_16(i1 %a) nounwind ss
}
define i32 @sext_1_32(i1 %a) nounwind ssp {
-; v7: sext_1_32:
+; v7-LABEL: sext_1_32:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_32:
+; prev6-LABEL: sext_1_32:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i32
@@ -107,9 +107,9 @@ define i32 @sext_1_32(i1 %a) nounwind ss
}
define i16 @sext_8_16(i8 %a) nounwind ssp {
-; v7: sext_8_16:
+; v7-LABEL: sext_8_16:
; v7: sxtb r0, r0
-; prev6: sext_8_16:
+; prev6-LABEL: sext_8_16:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i16
@@ -117,9 +117,9 @@ define i16 @sext_8_16(i8 %a) nounwind ss
}
define i32 @sext_8_32(i8 %a) nounwind ssp {
-; v7: sext_8_32:
+; v7-LABEL: sext_8_32:
; v7: sxtb r0, r0
-; prev6: sext_8_32:
+; prev6-LABEL: sext_8_32:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i32
@@ -127,9 +127,9 @@ define i32 @sext_8_32(i8 %a) nounwind ss
}
define i32 @sext_16_32(i16 %a) nounwind ssp {
-; v7: sext_16_32:
+; v7-LABEL: sext_16_32:
; v7: sxth r0, r0
-; prev6: sext_16_32:
+; prev6-LABEL: sext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: asr{{s?}} r0, r0, #16
%r = sext i16 %a to i32
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-frameaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-frameaddr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-frameaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-frameaddr.ll Sun Jul 14 01:24:09 2013
@@ -5,22 +5,22 @@
define i8* @frameaddr_index0() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index0:
+; DARWIN-ARM-LABEL: frameaddr_index0:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
-; DARWIN-THUMB2: frameaddr_index0:
+; DARWIN-THUMB2-LABEL: frameaddr_index0:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
-; LINUX-ARM: frameaddr_index0:
+; LINUX-ARM-LABEL: frameaddr_index0:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: mov r0, r11
-; LINUX-THUMB2: frameaddr_index0:
+; LINUX-THUMB2-LABEL: frameaddr_index0:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
@@ -31,24 +31,24 @@ entry:
define i8* @frameaddr_index1() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index1:
+; DARWIN-ARM-LABEL: frameaddr_index1:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
; DARWIN-ARM: ldr r0, [r0]
-; DARWIN-THUMB2: frameaddr_index1:
+; DARWIN-THUMB2-LABEL: frameaddr_index1:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
; DARWIN-THUMB2: ldr r0, [r0]
-; LINUX-ARM: frameaddr_index1:
+; LINUX-ARM-LABEL: frameaddr_index1:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11]
-; LINUX-THUMB2: frameaddr_index1:
+; LINUX-THUMB2-LABEL: frameaddr_index1:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
@@ -60,7 +60,7 @@ entry:
define i8* @frameaddr_index3() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index3:
+; DARWIN-ARM-LABEL: frameaddr_index3:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
@@ -68,7 +68,7 @@ entry:
; DARWIN-ARM: ldr r0, [r0]
; DARWIN-ARM: ldr r0, [r0]
-; DARWIN-THUMB2: frameaddr_index3:
+; DARWIN-THUMB2-LABEL: frameaddr_index3:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
@@ -76,14 +76,14 @@ entry:
; DARWIN-THUMB2: ldr r0, [r0]
; DARWIN-THUMB2: ldr r0, [r0]
-; LINUX-ARM: frameaddr_index3:
+; LINUX-ARM-LABEL: frameaddr_index3:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11]
; LINUX-ARM: ldr r0, [r0]
; LINUX-ARM: ldr r0, [r0]
-; LINUX-THUMB2: frameaddr_index3:
+; LINUX-THUMB2-LABEL: frameaddr_index3:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
Modified: llvm/trunk/test/CodeGen/ARM/fmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmacs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fmacs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fmacs.ll Sun Jul 14 01:24:09 2013
@@ -6,13 +6,13 @@
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vmla.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vmla.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vadd.f32
%0 = fmul float %a, %b
@@ -22,13 +22,13 @@ entry:
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vmla.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vmla.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vadd.f64
%0 = fmul double %a, %b
@@ -38,13 +38,13 @@ entry:
define float @t3(float %acc, float %a, float %b) {
entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
; VFP2: vmla.f32
-; NEON: t3:
+; NEON-LABEL: t3:
; NEON: vmla.f32
-; A8: t3:
+; A8-LABEL: t3:
; A8: vmul.f32
; A8: vadd.f32
%0 = fmul float %a, %b
@@ -56,18 +56,18 @@ entry:
; rdar://8659675
define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
entry:
-; A8: t4:
+; A8-LABEL: t4:
; A8: vmul.f32
; A8: vmul.f32
; A8: vadd.f32
; A8: vadd.f32
; Two vmla with now RAW hazard
-; A9: t4:
+; A9-LABEL: t4:
; A9: vmla.f32
; A9: vmla.f32
-; HARD: t4:
+; HARD-LABEL: t4:
; HARD: vmla.f32 s0, s1, s2
; HARD: vmla.f32 s3, s1, s4
%0 = fmul float %a, %b
@@ -81,18 +81,18 @@ entry:
define float @t5(float %a, float %b, float %c, float %d, float %e) {
entry:
-; A8: t5:
+; A8-LABEL: t5:
; A8: vmul.f32
; A8: vmul.f32
; A8: vadd.f32
; A8: vadd.f32
-; A9: t5:
+; A9-LABEL: t5:
; A9: vmla.f32
; A9: vmul.f32
; A9: vadd.f32
-; HARD: t5:
+; HARD-LABEL: t5:
; HARD: vmla.f32 s4, s0, s1
; HARD: vmul.f32 s0, s2, s3
; HARD: vadd.f32 s0, s4, s0
Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Sun Jul 14 01:24:09 2013
@@ -4,13 +4,13 @@
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vnmls.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vnmls.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vsub.f32
%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vnmls.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vnmls.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vsub.f64
%0 = fmul double %a, %b
Modified: llvm/trunk/test/CodeGen/ARM/fnmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmacs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnmacs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnmacs.ll Sun Jul 14 01:24:09 2013
@@ -4,13 +4,13 @@
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vmls.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vmls.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vsub.f32
%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vmls.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vmls.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vsub.f64
%0 = fmul double %a, %b
Modified: llvm/trunk/test/CodeGen/ARM/fnmscs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmscs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnmscs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnmscs.ll Sun Jul 14 01:24:09 2013
@@ -7,17 +7,17 @@
define float @t1(float %acc, float %a, float %b) nounwind {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vnmla.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vnmla.f32
-; A8U: t1:
+; A8U-LABEL: t1:
; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
-; A8: t1:
+; A8-LABEL: t1:
; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b
@@ -28,17 +28,17 @@ entry:
define float @t2(float %acc, float %a, float %b) nounwind {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vnmla.f32
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vnmla.f32
-; A8U: t2:
+; A8U-LABEL: t2:
; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
-; A8: t2:
+; A8-LABEL: t2:
; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b
@@ -49,17 +49,17 @@ entry:
define double @t3(double %acc, double %a, double %b) nounwind {
entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
; VFP2: vnmla.f64
-; NEON: t3:
+; NEON-LABEL: t3:
; NEON: vnmla.f64
-; A8U: t3:
+; A8U-LABEL: t3:
; A8U: vnmul.f64 d
; A8U: vsub.f64 d
-; A8: t3:
+; A8-LABEL: t3:
; A8: vnmul.f64 d
; A8: vsub.f64 d
%0 = fmul double %a, %b
@@ -70,17 +70,17 @@ entry:
define double @t4(double %acc, double %a, double %b) nounwind {
entry:
-; VFP2: t4:
+; VFP2-LABEL: t4:
; VFP2: vnmla.f64
-; NEON: t4:
+; NEON-LABEL: t4:
; NEON: vnmla.f64
-; A8U: t4:
+; A8U-LABEL: t4:
; A8U: vnmul.f64 d
; A8U: vsub.f64 d
-; A8: t4:
+; A8-LABEL: t4:
; A8: vnmul.f64 d
; A8: vsub.f64 d
%0 = fmul double %a, %b
Modified: llvm/trunk/test/CodeGen/ARM/fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f(i32 %a) {
-;CHECK: f:
+;CHECK-LABEL: f:
;CHECK: vmov
;CHECK-NEXT: vcvt.f32.s32
;CHECK-NEXT: vmov
@@ -11,7 +11,7 @@ entry:
}
define double @g(i32 %a) {
-;CHECK: g:
+;CHECK-LABEL: g:
;CHECK: vmov
;CHECK-NEXT: vcvt.f64.s32
;CHECK-NEXT: vmov
@@ -21,7 +21,7 @@ entry:
}
define double @uint_to_double(i32 %a) {
-;CHECK: uint_to_double:
+;CHECK-LABEL: uint_to_double:
;CHECK: vmov
;CHECK-NEXT: vcvt.f64.u32
;CHECK-NEXT: vmov
@@ -31,7 +31,7 @@ entry:
}
define float @uint_to_float(i32 %a) {
-;CHECK: uint_to_float:
+;CHECK-LABEL: uint_to_float:
;CHECK: vmov
;CHECK-NEXT: vcvt.f32.u32
;CHECK-NEXT: vmov
@@ -41,7 +41,7 @@ entry:
}
define double @h(double* %v) {
-;CHECK: h:
+;CHECK-LABEL: h:
;CHECK: vldr
;CHECK-NEXT: vmov
entry:
@@ -50,20 +50,20 @@ entry:
}
define float @h2() {
-;CHECK: h2:
+;CHECK-LABEL: h2:
;CHECK: mov r0, #1065353216
entry:
ret float 1.000000e+00
}
define double @f2(double %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK-NOT: vmov
ret double %a
}
define void @f3() {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK-NOT: vmov
;CHECK: f4
entry:
Modified: llvm/trunk/test/CodeGen/ARM/fp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16.ll Sun Jul 14 01:24:09 2013
@@ -8,8 +8,8 @@ target triple = "armv7-eabi"
@z = common global i16 0
define arm_aapcs_vfpcc void @foo() nounwind {
-; CHECK: foo:
-; CHECK-FP6: foo:
+; CHECK-LABEL: foo:
+; CHECK-FP6-LABEL: foo:
entry:
%0 = load i16* @x, align 2
%1 = load i16* @y, align 2
Modified: llvm/trunk/test/CodeGen/ARM/fparith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fparith.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fparith.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fparith.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
define float @f1(float %a, float %b) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: vadd.f32
entry:
%tmp = fadd float %a, %b ; <float> [#uses=1]
@@ -9,7 +9,7 @@ entry:
}
define double @f2(double %a, double %b) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: vadd.f64
entry:
%tmp = fadd double %a, %b ; <double> [#uses=1]
@@ -17,7 +17,7 @@ entry:
}
define float @f3(float %a, float %b) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: vmul.f32
entry:
%tmp = fmul float %a, %b ; <float> [#uses=1]
@@ -25,7 +25,7 @@ entry:
}
define double @f4(double %a, double %b) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: vmul.f64
entry:
%tmp = fmul double %a, %b ; <double> [#uses=1]
@@ -33,7 +33,7 @@ entry:
}
define float @f5(float %a, float %b) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: vsub.f32
entry:
%tmp = fsub float %a, %b ; <float> [#uses=1]
@@ -41,7 +41,7 @@ entry:
}
define double @f6(double %a, double %b) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: vsub.f64
entry:
%tmp = fsub double %a, %b ; <double> [#uses=1]
@@ -49,7 +49,7 @@ entry:
}
define float @f7(float %a) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: eor
entry:
%tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
@@ -57,7 +57,7 @@ entry:
}
define double @f8(double %a) {
-;CHECK: f8:
+;CHECK-LABEL: f8:
;CHECK: vneg.f64
entry:
%tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1]
@@ -65,7 +65,7 @@ entry:
}
define float @f9(float %a, float %b) {
-;CHECK: f9:
+;CHECK-LABEL: f9:
;CHECK: vdiv.f32
entry:
%tmp1 = fdiv float %a, %b ; <float> [#uses=1]
@@ -73,7 +73,7 @@ entry:
}
define double @f10(double %a, double %b) {
-;CHECK: f10:
+;CHECK-LABEL: f10:
;CHECK: vdiv.f64
entry:
%tmp1 = fdiv double %a, %b ; <double> [#uses=1]
@@ -81,7 +81,7 @@ entry:
}
define float @f11(float %a) {
-;CHECK: f11:
+;CHECK-LABEL: f11:
;CHECK: bic
entry:
%tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
@@ -91,7 +91,7 @@ entry:
declare float @fabsf(float)
define double @f12(double %a) {
-;CHECK: f12:
+;CHECK-LABEL: f12:
;CHECK: vabs.f64
entry:
%tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Disable this optimization unless we know one of them is zero.
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vldr [[S0:s[0-9]+]],
; CHECK: vldr [[S1:s[0-9]+]],
; CHECK: vcmpe.f32 [[S1]], [[S0]]
@@ -29,7 +29,7 @@ bb2:
; +0.0 == -0.0
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK-NOT: vldr
; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
@@ -55,7 +55,7 @@ bb2:
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK-NOT: vldr
; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
Modified: llvm/trunk/test/CodeGen/ARM/fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define i32 @f1(float %a) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: vcmpe.f32
;CHECK: movmi
entry:
@@ -11,7 +11,7 @@ entry:
}
define i32 @f2(float %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: vcmpe.f32
;CHECK: moveq
entry:
@@ -21,7 +21,7 @@ entry:
}
define i32 @f3(float %a) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: vcmpe.f32
;CHECK: movgt
entry:
@@ -31,7 +31,7 @@ entry:
}
define i32 @f4(float %a) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: vcmpe.f32
;CHECK: movge
entry:
@@ -41,7 +41,7 @@ entry:
}
define i32 @f5(float %a) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: vcmpe.f32
;CHECK: movls
entry:
@@ -51,7 +51,7 @@ entry:
}
define i32 @f6(float %a) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: vcmpe.f32
;CHECK: movne
entry:
@@ -61,7 +61,7 @@ entry:
}
define i32 @g1(double %a) {
-;CHECK: g1:
+;CHECK-LABEL: g1:
;CHECK: vcmpe.f64
;CHECK: movmi
entry:
Modified: llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
define i32 @f7(float %a, float %b) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: vcmpe.f32
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: movweq
Modified: llvm/trunk/test/CodeGen/ARM/fpconsts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpconsts.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpconsts.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpconsts.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define float @t1(float %x) nounwind readnone optsize {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
%0 = fadd float %x, 4.000000e+00
ret float %0
@@ -10,7 +10,7 @@ entry:
define double @t2(double %x) nounwind readnone optsize {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
%0 = fadd double %x, 3.000000e+00
ret double %0
@@ -18,7 +18,7 @@ entry:
define double @t3(double %x) nounwind readnone optsize {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
%0 = fmul double %x, -1.300000e+01
ret double %0
@@ -26,7 +26,7 @@ entry:
define float @t4(float %x) nounwind readnone optsize {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
%0 = fmul float %x, -2.400000e+01
ret float %0
Modified: llvm/trunk/test/CodeGen/ARM/fpconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpconv.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpconv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpconv.ll Sun Jul 14 01:24:09 2013
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
define float @f1(double %x) {
-;CHECK-VFP: f1:
+;CHECK-VFP-LABEL: f1:
;CHECK-VFP: vcvt.f32.f64
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: truncdfsf2
entry:
%tmp1 = fptrunc double %x to float ; <float> [#uses=1]
@@ -12,9 +12,9 @@ entry:
}
define double @f2(float %x) {
-;CHECK-VFP: f2:
+;CHECK-VFP-LABEL: f2:
;CHECK-VFP: vcvt.f64.f32
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: extendsfdf2
entry:
%tmp1 = fpext float %x to double ; <double> [#uses=1]
@@ -22,9 +22,9 @@ entry:
}
define i32 @f3(float %x) {
-;CHECK-VFP: f3:
+;CHECK-VFP-LABEL: f3:
;CHECK-VFP: vcvt.s32.f32
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: fixsfsi
entry:
%tmp = fptosi float %x to i32 ; <i32> [#uses=1]
@@ -32,9 +32,9 @@ entry:
}
define i32 @f4(float %x) {
-;CHECK-VFP: f4:
+;CHECK-VFP-LABEL: f4:
;CHECK-VFP: vcvt.u32.f32
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: fixunssfsi
entry:
%tmp = fptoui float %x to i32 ; <i32> [#uses=1]
@@ -42,9 +42,9 @@ entry:
}
define i32 @f5(double %x) {
-;CHECK-VFP: f5:
+;CHECK-VFP-LABEL: f5:
;CHECK-VFP: vcvt.s32.f64
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: fixdfsi
entry:
%tmp = fptosi double %x to i32 ; <i32> [#uses=1]
@@ -52,9 +52,9 @@ entry:
}
define i32 @f6(double %x) {
-;CHECK-VFP: f6:
+;CHECK-VFP-LABEL: f6:
;CHECK-VFP: vcvt.u32.f64
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: fixunsdfsi
entry:
%tmp = fptoui double %x to i32 ; <i32> [#uses=1]
@@ -62,9 +62,9 @@ entry:
}
define float @f7(i32 %a) {
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vcvt.f32.s32
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: floatsisf
entry:
%tmp = sitofp i32 %a to float ; <float> [#uses=1]
@@ -72,9 +72,9 @@ entry:
}
define double @f8(i32 %a) {
-;CHECK-VFP: f8:
+;CHECK-VFP-LABEL: f8:
;CHECK-VFP: vcvt.f64.s32
-;CHECK: f8:
+;CHECK-LABEL: f8:
;CHECK: floatsidf
entry:
%tmp = sitofp i32 %a to double ; <double> [#uses=1]
@@ -82,9 +82,9 @@ entry:
}
define float @f9(i32 %a) {
-;CHECK-VFP: f9:
+;CHECK-VFP-LABEL: f9:
;CHECK-VFP: vcvt.f32.u32
-;CHECK: f9:
+;CHECK-LABEL: f9:
;CHECK: floatunsisf
entry:
%tmp = uitofp i32 %a to float ; <float> [#uses=1]
@@ -92,9 +92,9 @@ entry:
}
define double @f10(i32 %a) {
-;CHECK-VFP: f10:
+;CHECK-VFP-LABEL: f10:
;CHECK-VFP: vcvt.f64.u32
-;CHECK: f10:
+;CHECK-LABEL: f10:
;CHECK: floatunsidf
entry:
%tmp = uitofp i32 %a to double ; <double> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/fpmem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpmem.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpmem.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpmem.ll Sun Jul 14 01:24:09 2013
@@ -1,13 +1,13 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mov r0, #0
ret float 0.000000e+00
}
define float @f2(float* %v, float %u) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: vldr{{.*}}[
%tmp = load float* %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
@@ -15,7 +15,7 @@ define float @f2(float* %v, float %u) {
}
define float @f2offset(float* %v, float %u) {
-; CHECK: f2offset:
+; CHECK-LABEL: f2offset:
; CHECK: vldr{{.*}}, #4]
%addr = getelementptr float* %v, i32 1
%tmp = load float* %addr
@@ -24,7 +24,7 @@ define float @f2offset(float* %v, float
}
define float @f2noffset(float* %v, float %u) {
-; CHECK: f2noffset:
+; CHECK-LABEL: f2noffset:
; CHECK: vldr{{.*}}, #-4]
%addr = getelementptr float* %v, i32 -1
%tmp = load float* %addr
@@ -33,7 +33,7 @@ define float @f2noffset(float* %v, float
}
define void @f3(float %a, float %b, float* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: vstr{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1]
store float %tmp, float* %v
Modified: llvm/trunk/test/CodeGen/ARM/fptoint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fptoint.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fptoint.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fptoint.ll Sun Jul 14 01:24:09 2013
@@ -44,6 +44,6 @@ define void @foo9(double %x) {
store i16 %tmp, i16* null
ret void
}
-; CHECK: foo9:
+; CHECK-LABEL: foo9:
; CHECK: vmov r0, s0
Modified: llvm/trunk/test/CodeGen/ARM/fusedMAC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fusedMAC.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fusedMAC.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fusedMAC.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; Check generated fused MAC and MLS.
define double @fusedMACTest1(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest1:
+;CHECK-LABEL: fusedMACTest1:
;CHECK: vfma.f64
%1 = fmul double %d1, %d2
%2 = fadd double %1, %d3
@@ -10,7 +10,7 @@ define double @fusedMACTest1(double %d1,
}
define float @fusedMACTest2(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest2:
+;CHECK-LABEL: fusedMACTest2:
;CHECK: vfma.f32
%1 = fmul float %f1, %f2
%2 = fadd float %1, %f3
@@ -18,7 +18,7 @@ define float @fusedMACTest2(float %f1, f
}
define double @fusedMACTest3(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest3:
+;CHECK-LABEL: fusedMACTest3:
;CHECK: vfms.f64
%1 = fmul double %d2, %d3
%2 = fsub double %d1, %1
@@ -26,7 +26,7 @@ define double @fusedMACTest3(double %d1,
}
define float @fusedMACTest4(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest4:
+;CHECK-LABEL: fusedMACTest4:
;CHECK: vfms.f32
%1 = fmul float %f2, %f3
%2 = fsub float %f1, %1
@@ -34,7 +34,7 @@ define float @fusedMACTest4(float %f1, f
}
define double @fusedMACTest5(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest5:
+;CHECK-LABEL: fusedMACTest5:
;CHECK: vfnma.f64
%1 = fmul double %d1, %d2
%2 = fsub double -0.0, %1
@@ -43,7 +43,7 @@ define double @fusedMACTest5(double %d1,
}
define float @fusedMACTest6(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest6:
+;CHECK-LABEL: fusedMACTest6:
;CHECK: vfnma.f32
%1 = fmul float %f1, %f2
%2 = fsub float -0.0, %1
@@ -52,7 +52,7 @@ define float @fusedMACTest6(float %f1, f
}
define double @fusedMACTest7(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest7:
+;CHECK-LABEL: fusedMACTest7:
;CHECK: vfnms.f64
%1 = fmul double %d1, %d2
%2 = fsub double %1, %d3
@@ -60,7 +60,7 @@ define double @fusedMACTest7(double %d1,
}
define float @fusedMACTest8(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest8:
+;CHECK-LABEL: fusedMACTest8:
;CHECK: vfnms.f32
%1 = fmul float %f1, %f2
%2 = fsub float %1, %f3
@@ -68,7 +68,7 @@ define float @fusedMACTest8(float %f1, f
}
define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest9:
+;CHECK-LABEL: fusedMACTest9:
;CHECK: vfma.f32
%mul = fmul <2 x float> %a, %b
%add = fadd <2 x float> %mul, %a
@@ -76,7 +76,7 @@ define <2 x float> @fusedMACTest9(<2 x f
}
define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest10:
+;CHECK-LABEL: fusedMACTest10:
;CHECK: vfms.f32
%mul = fmul <2 x float> %a, %b
%sub = fsub <2 x float> %a, %mul
@@ -84,7 +84,7 @@ define <2 x float> @fusedMACTest10(<2 x
}
define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest11:
+;CHECK-LABEL: fusedMACTest11:
;CHECK: vfma.f32
%mul = fmul <4 x float> %a, %b
%add = fadd <4 x float> %mul, %a
@@ -92,7 +92,7 @@ define <4 x float> @fusedMACTest11(<4 x
}
define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest12:
+;CHECK-LABEL: fusedMACTest12:
;CHECK: vfms.f32
%mul = fmul <4 x float> %a, %b
%sub = fsub <4 x float> %a, %mul
Modified: llvm/trunk/test/CodeGen/ARM/globals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/globals.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/globals.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/globals.ll Sun Jul 14 01:24:09 2013
@@ -57,7 +57,7 @@ define i32 @test1() {
-; LinuxPIC: test1:
+; LinuxPIC-LABEL: test1:
; LinuxPIC: ldr r0, .LCPI0_0
; LinuxPIC: ldr r1, .LCPI0_1
Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
define i32 @t() nounwind readonly {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: ldr
; CHECK-NEXT: ldr
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/hidden-vis.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/hidden-vis.ll Sun Jul 14 01:24:09 2013
@@ -6,18 +6,18 @@
define weak hidden void @t1() nounwind {
; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
ret void
}
define weak void @t2() nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
; LINUX: .hidden a
-; DARWIN: t2:
+; DARWIN-LABEL: t2:
; DARWIN: .private_extern _a
ret void
}
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt1.ll Sun Jul 14 01:24:09 2013
@@ -2,8 +2,8 @@
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT
define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
-; SWIFT: t1:
+; A8-LABEL: t1:
+; SWIFT-LABEL: t1:
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: vpop {d8}
; CHECK-NOT: vpopne
; CHECK: pop {r7, pc}
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt11.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt11.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt11.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
%struct.xyz_t = type { double, double, double }
define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
-; CHECK: effie:
+; CHECK-LABEL: effie:
entry:
%0 = icmp sgt i32 %tsets, 0
br i1 %0, label %bb.nph, label %bb6
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt12.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt12.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt12.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt12.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mlsne r0, r0, r1, r2
%tmp1 = icmp eq i32 %a, 0
br i1 %tmp1, label %cond_false, label %cond_true
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt2.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: bxlt lr
%tmp2 = icmp sgt i32 %c, 10
%tmp5 = icmp slt i32 %d, 4
@@ -19,7 +19,7 @@ UnifiedReturnBlock:
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: bxgt lr
; CHECK: cmp
; CHECK: addge
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt3.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt3.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: cmp r2, #1
; CHECK: cmpne r2, #7
switch i32 %c, label %cond_next [
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt4.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt4.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm | FileCheck %s
; Do not if-convert when branches go to the different loops.
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: subgt
; CHECK-NOT: suble
; Don't use
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Sun Jul 14 01:24:09 2013
@@ -12,10 +12,10 @@ entry:
}
define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
+; A8-LABEL: t1:
; A8: poplt {r7, pc}
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: pop {r7, pc}
; SWIFT: pop {r7, pc}
entry:
Modified: llvm/trunk/test/CodeGen/ARM/indirectbr-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/indirectbr-2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/indirectbr-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/indirectbr-2.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@
; The indirect branch has the two destinations as successors. The lone PHI
; statement shouldn't be implicitly defined.
-; CHECK: func:
+; CHECK-LABEL: func:
; CHECK: Ltmp1: @ Block address taken
; CHECK-NOT: @ implicit-def: R0
; CHECK: @ 4-byte Reload
Modified: llvm/trunk/test/CodeGen/ARM/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/indirectbr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/indirectbr.ll Sun Jul 14 01:24:09 2013
@@ -6,9 +6,9 @@
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
-; ARM: foo:
-; THUMB: foo:
-; THUMB2: foo:
+; ARM-LABEL: foo:
+; THUMB-LABEL: foo:
+; THUMB2-LABEL: foo:
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
; check if regs are passing correctly
define void @i64_write(i64* %p, i64 %val) nounwind {
-; CHECK: i64_write:
+; CHECK-LABEL: i64_write:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
@@ -12,7 +12,7 @@ define void @i64_write(i64* %p, i64 %val
; check if register allocation can reuse the registers
define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
entry:
-; CHECK: multi_writes:
+; CHECK-LABEL: multi_writes:
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
@@ -44,7 +44,7 @@ entry:
; check if callee-saved registers used by inline asm are saved/restored
define void @foo(i64* %p, i64 %i) nounwind {
-; CHECK:foo:
+; CHECK-LABEL:foo:
; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
@@ -55,20 +55,20 @@ define void @foo(i64* %p, i64 %i) nounwi
; return *p;
define i64 @ldrd_test(i64* %p) nounwind {
-; CHECK: ldrd_test:
+; CHECK-LABEL: ldrd_test:
%1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
ret i64 %1
}
define i64 @QR_test(i64* %p) nounwind {
-; CHECK: QR_test:
+; CHECK-LABEL: QR_test:
; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
ret i64 %1
}
define i64 @defuse_test(i64 %p) nounwind {
-; CHECK: defuse_test:
+; CHECK-LABEL: defuse_test:
; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
%1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
ret i64 %1
@@ -76,7 +76,7 @@ define i64 @defuse_test(i64 %p) nounwind
; *p = (hi << 32) | lo;
define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
-; CHECK: strd_test:
+; CHECK-LABEL: strd_test:
; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = zext i32 %hi to i64
%2 = shl nuw i64 %1, 32
Modified: llvm/trunk/test/CodeGen/ARM/inlineasm4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm4.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm4.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@ define double @f(double %x) {
entry:
%0 = tail call double asm "mov ${0:R}, #4\0A", "=&r"()
ret double %0
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: mov r1, #4
}
@@ -12,6 +12,6 @@ define double @g(double %x) {
entry:
%0 = tail call double asm "mov ${0:Q}, #4\0A", "=&r"()
ret double %0
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: mov r0, #4
}
Modified: llvm/trunk/test/CodeGen/ARM/ldm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldm.ll Sun Jul 14 01:24:09 2013
@@ -4,9 +4,9 @@
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: pop
-; V4T: t1:
+; V4T-LABEL: t1:
; V4T: pop
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
@@ -15,9 +15,9 @@ define i32 @t1() {
}
define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: pop
-; V4T: t2:
+; V4T-LABEL: t2:
; V4T: pop
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
@@ -27,10 +27,10 @@ define i32 @t2() {
}
define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: ldmib
; CHECK: pop
-; V4T: t3:
+; V4T-LABEL: t3:
; V4T: ldmib
; V4T: pop
; V4T-NEXT: bx lr
Modified: llvm/trunk/test/CodeGen/ARM/ldr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldr.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm | FileCheck %s
define i32 @f1(i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldr r0
entry:
%tmp = load i32* %v
@@ -9,7 +9,7 @@ entry:
}
define i32 @f2(i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldr r0
entry:
%tmp2 = getelementptr i32* %v, i32 1023
@@ -18,7 +18,7 @@ entry:
}
define i32 @f3(i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov
; CHECK: ldr r0
entry:
@@ -28,7 +28,7 @@ entry:
}
define i32 @f4(i32 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: mvn
; CHECK: ldr r0
entry:
@@ -39,7 +39,7 @@ entry:
}
define i32 @f5(i32 %base, i32 %offset) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldr r0
entry:
%tmp1 = add i32 %base, %offset
@@ -49,7 +49,7 @@ entry:
}
define i32 @f6(i32 %base, i32 %offset) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldr r0{{.*}}lsl{{.*}}
entry:
%tmp1 = shl i32 %offset, 2
@@ -60,7 +60,7 @@ entry:
}
define i32 @f7(i32 %base, i32 %offset) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ldr r0{{.*}}lsr{{.*}}
entry:
%tmp1 = lshr i32 %offset, 2
Modified: llvm/trunk/test/CodeGen/ARM/ldrd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldrd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldrd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldrd.ll Sun Jul 14 01:24:09 2013
@@ -13,10 +13,10 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
-; A8: t:
+; A8-LABEL: t:
; A8: ldrd r2, r3, [r2]
-; M3: t:
+; M3-LABEL: t:
; M3-NOT: ldrd
%0 = load i64** @b, align 4
Modified: llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; rdar://8944252
define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
%src6 = bitcast float* %src to i8*
%0 = icmp eq i32 %width, 0
Modified: llvm/trunk/test/CodeGen/ARM/ldstrexd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldstrexd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldstrexd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldstrexd.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
%0 = type { i32, i32 }
-; CHECK: f0:
+; CHECK-LABEL: f0:
; CHECK: ldrexd
define i64 @f0(i8* %p) nounwind readonly {
entry:
@@ -17,7 +17,7 @@ entry:
ret i64 %4
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strexd
define i32 @f1(i8* %ptr, i64 %val) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/ARM/load-address-masked.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/load-address-masked.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/load-address-masked.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/load-address-masked.ll Sun Jul 14 01:24:09 2013
@@ -10,5 +10,5 @@ entry:
ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255)
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldrb r0, .LCPI0_0
Modified: llvm/trunk/test/CodeGen/ARM/load_i1_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/load_i1_select.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/load_i1_select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/load_i1_select.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios0.0.0"
; Codegen should only compare one bit of the loaded value.
; rdar://10887484
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldrb r[[R0:[0-9]+]], [r0]
; CHECK: tst.w r[[R0]], #1
define void @foo(i8* %call, double* %p) nounwind {
Modified: llvm/trunk/test/CodeGen/ARM/long.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/long.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/long.ll Sun Jul 14 01:24:09 2013
@@ -1,33 +1,33 @@
; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
entry:
ret i64 0
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
entry:
ret i64 1
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvn r0, #-2147483648
entry:
ret i64 2147483647
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mov r0, #-2147483648
entry:
ret i64 2147483648
}
define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvn r0, #0
; CHECK: mvn r1, #-2147483648
entry:
@@ -35,7 +35,7 @@ entry:
}
define i64 @f6(i64 %x, i64 %y) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: adds
; CHECK: adc
entry:
@@ -44,7 +44,7 @@ entry:
}
define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
entry:
%tmp = call i64 @f8( ) ; <i64> [#uses=0]
ret void
@@ -53,7 +53,7 @@ entry:
declare i64 @f8()
define i64 @f9(i64 %a, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: subs r
; CHECK: sbc
entry:
@@ -62,7 +62,7 @@ entry:
}
define i64 @f(i32 %a, i32 %b) {
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: smull
entry:
%tmp = sext i32 %a to i64 ; <i64> [#uses=1]
@@ -72,7 +72,7 @@ entry:
}
define i64 @g(i32 %a, i32 %b) {
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: umull
entry:
%tmp = zext i32 %a to i64 ; <i64> [#uses=1]
@@ -82,7 +82,7 @@ entry:
}
define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
entry:
%a = alloca i64, align 8 ; <i64*> [#uses=1]
%retval = load i64* %a ; <i64> [#uses=1]
Modified: llvm/trunk/test/CodeGen/ARM/longMAC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/longMAC.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/longMAC.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/longMAC.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; Check generated signed and unsigned multiply accumulate long.
define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
;CHECK: umlal
%conv = zext i32 %a to i64
%conv1 = zext i32 %b to i64
@@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b,
}
define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
;CHECK: smlal
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
@@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b,
}
define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
;CHECK: umlal
%conv = zext i32 %b to i64
%conv1 = zext i32 %a to i64
@@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b,
}
define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
;CHECK: smlal
%conv = sext i32 %b to i64
%conv1 = sext i32 %a to i64
Modified: llvm/trunk/test/CodeGen/ARM/lsr-icmp-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-icmp-imm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-icmp-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lsr-icmp-imm.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; LSR should compare against the post-incremented induction variable.
; In this case, the immediate value is -2 which requires a cmn instruction.
;
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: %for.body
; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2
; CHECK: cmn{{.*}}[[IV]], #2
Modified: llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmp
; CHECK: moveq
; CHECK-NOT: cmp
@@ -25,7 +25,7 @@ entry:
; rdar://10660865
define void @f2() nounwind ssp {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmp
; CHECK: poplt
; CHECK-NOT: cmp
@@ -49,7 +49,7 @@ declare void @llvm.memset.p0i8.i32(i8* n
; rdar://12462006
define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: sub
; CHECK: cmp
; CHECK: blt
Modified: llvm/trunk/test/CodeGen/ARM/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/machine-licm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-licm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/machine-licm.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@
define void @t(i32* nocapture %vals, i32 %c) nounwind {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
@@ -23,14 +23,14 @@ entry:
; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
-; MOVT: t:
+; MOVT-LABEL: t:
; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
; MOVT: LPC0_0:
; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
-; THUMB: t:
+; THUMB-LABEL: t:
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
Modified: llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll Sun Jul 14 01:24:09 2013
@@ -15,7 +15,7 @@
define i32 @t0() {
entry:
-; CHECK: t0:
+; CHECK-LABEL: t0:
; CHECK: vldr [[REG1:d[0-9]+]],
; CHECK: vstr [[REG1]],
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
@@ -24,7 +24,7 @@ entry:
define void @t1(i8* nocapture %C) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
; CHECK: adds r0, #15
@@ -37,7 +37,7 @@ entry:
define void @t2(i8* nocapture %C) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32]
; CHECK: str [[REG2]], [r0, #32]
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
@@ -52,7 +52,7 @@ entry:
define void @t3(i8* nocapture %C) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
; CHECK: adds r0, #16
@@ -65,7 +65,7 @@ entry:
define void @t4(i8* nocapture %C) nounwind {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
@@ -74,7 +74,7 @@ entry:
define void @t5(i8* nocapture %C) nounwind {
entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: movs [[REG5:r[0-9]+]], #0
; CHECK: strb [[REG5]], [r0, #6]
; CHECK: movw [[REG6:r[0-9]+]], #21587
@@ -87,7 +87,7 @@ entry:
define void @t6() nounwind {
entry:
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: vld1.8 {[[REG8:d[0-9]+]]}, [r0]
; CHECK: vstr [[REG8]], [r1]
; CHECK: adds r1, #6
Modified: llvm/trunk/test/CodeGen/ARM/memset-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/memset-inline.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/memset-inline.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/memset-inline.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define void @t1(i8* nocapture %c) nounwind optsize {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movs r1, #0
; CHECK: str r1, [r0]
; CHECK: str r1, [r0, #4]
@@ -13,7 +13,7 @@ entry:
define void @t2() nounwind ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: add.w r1, r0, #10
; CHECK: vmov.i32 {{q[0-9]+}}, #0x0
; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
Modified: llvm/trunk/test/CodeGen/ARM/mls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/mls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/mls.ll Sun Jul 14 01:24:09 2013
@@ -14,15 +14,15 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mls r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
; NO_MULOPS: mul r0, r0, r1
; NO_MULOPS-NEXT: sub r0, r2, r0
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mul r0, r0, r1
; CHECK-NEXT: sub r0, r0, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
; NO_MULOPS: mul r0, r0, r1
; NO_MULOPS-NEXT: sub r0, r0, r2
Modified: llvm/trunk/test/CodeGen/ARM/movt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/movt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/movt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/movt.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; rdar://7317664
define i32 @t(i32 %X) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movt r0, #65535
entry:
%0 = or i32 %X, -65536
@@ -10,7 +10,7 @@ entry:
}
define i32 @t2(i32 %X) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movt r0, #65534
entry:
%0 = or i32 %X, -131072
Modified: llvm/trunk/test/CodeGen/ARM/mul_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mul_const.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/mul_const.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/mul_const.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define i32 @t9(i32 %v) nounwind readnone {
entry:
-; CHECK: t9:
+; CHECK-LABEL: t9:
; CHECK: add r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
@@ -10,7 +10,7 @@ entry:
define i32 @t7(i32 %v) nounwind readnone {
entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
@@ -18,7 +18,7 @@ entry:
define i32 @t5(i32 %v) nounwind readnone {
entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: add r0, r0, r0, lsl #2
%0 = mul i32 %v, 5
ret i32 %0
@@ -26,7 +26,7 @@ entry:
define i32 @t3(i32 %v) nounwind readnone {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: add r0, r0, r0, lsl #1
%0 = mul i32 %v, 3
ret i32 %0
@@ -34,7 +34,7 @@ entry:
define i32 @t12288(i32 %v) nounwind readnone {
entry:
-; CHECK: t12288:
+; CHECK-LABEL: t12288:
; CHECK: add r0, r0, r0, lsl #1
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, 12288
@@ -43,7 +43,7 @@ entry:
define i32 @tn9(i32 %v) nounwind readnone {
entry:
-; CHECK: tn9:
+; CHECK-LABEL: tn9:
; CHECK: add r0, r0, r0, lsl #3
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -9
@@ -52,7 +52,7 @@ entry:
define i32 @tn7(i32 %v) nounwind readnone {
entry:
-; CHECK: tn7:
+; CHECK-LABEL: tn7:
; CHECK: sub r0, r0, r0, lsl #3
%0 = mul i32 %v, -7
ret i32 %0
@@ -60,7 +60,7 @@ entry:
define i32 @tn5(i32 %v) nounwind readnone {
entry:
-; CHECK: tn5:
+; CHECK-LABEL: tn5:
; CHECK: add r0, r0, r0, lsl #2
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -5
@@ -69,7 +69,7 @@ entry:
define i32 @tn3(i32 %v) nounwind readnone {
entry:
-; CHECK: tn3:
+; CHECK-LABEL: tn3:
; CHECK: sub r0, r0, r0, lsl #2
%0 = mul i32 %v, -3
ret i32 %0
@@ -77,7 +77,7 @@ entry:
define i32 @tn12288(i32 %v) nounwind readnone {
entry:
-; CHECK: tn12288:
+; CHECK-LABEL: tn12288:
; CHECK: sub r0, r0, r0, lsl #2
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, -12288
Modified: llvm/trunk/test/CodeGen/ARM/mulhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mulhi.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/mulhi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/mulhi.ll Sun Jul 14 01:24:09 2013
@@ -3,13 +3,13 @@
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
define i32 @smulhi(i32 %x, i32 %y) nounwind {
-; V6: smulhi:
+; V6-LABEL: smulhi:
; V6: smmul
-; V4: smulhi:
+; V4-LABEL: smulhi:
; V4: smull
-; M3: smulhi:
+; M3-LABEL: smulhi:
; M3: smull
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
@@ -20,13 +20,13 @@ define i32 @smulhi(i32 %x, i32 %y) nounw
}
define i32 @umulhi(i32 %x, i32 %y) nounwind {
-; V6: umulhi:
+; V6-LABEL: umulhi:
; V6: umull
-; V4: umulhi:
+; V4-LABEL: umulhi:
; V4: umull
-; M3: umulhi:
+; M3-LABEL: umulhi:
; M3: umull
%tmp = zext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
@@ -38,13 +38,13 @@ define i32 @umulhi(i32 %x, i32 %y) nounw
; rdar://r10152911
define i32 @t3(i32 %a) nounwind {
-; V6: t3:
+; V6-LABEL: t3:
; V6: smmla
-; V4: t3:
+; V4-LABEL: t3:
; V4: smull
-; M3: t3:
+; M3-LABEL: t3:
; M3-NOT: smmla
; M3: smull
entry:
Modified: llvm/trunk/test/CodeGen/ARM/neon-spfp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon-spfp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/neon-spfp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/neon-spfp.ll Sun Jul 14 01:24:09 2013
@@ -21,21 +21,21 @@
@.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1
-; CHECK-LINUXA5: main:
-; CHECK-LINUXA8: main:
-; CHECK-LINUXA9: main:
-; CHECK-LINUXA15: main:
-; CHECK-LINUXSWIFT: main:
-; CHECK-UNSAFEA5: main:
-; CHECK-UNSAFEA8: main:
-; CHECK-UNSAFEA9: main:
-; CHECK-UNSAFEA15: main:
-; CHECK-UNSAFESWIFT: main:
-; CHECK-DARWINA5: main:
-; CHECK-DARWINA8: main:
-; CHECK-DARWINA9: main:
-; CHECK-DARWINA15: main:
-; CHECK-DARWINSWIFT: main:
+; CHECK-LINUXA5-LABEL: main:
+; CHECK-LINUXA8-LABEL: main:
+; CHECK-LINUXA9-LABEL: main:
+; CHECK-LINUXA15-LABEL: main:
+; CHECK-LINUXSWIFT-LABEL: main:
+; CHECK-UNSAFEA5-LABEL: main:
+; CHECK-UNSAFEA8-LABEL: main:
+; CHECK-UNSAFEA9-LABEL: main:
+; CHECK-UNSAFEA15-LABEL: main:
+; CHECK-UNSAFESWIFT-LABEL: main:
+; CHECK-DARWINA5-LABEL: main:
+; CHECK-DARWINA8-LABEL: main:
+; CHECK-DARWINA9-LABEL: main:
+; CHECK-DARWINA15-LABEL: main:
+; CHECK-DARWINSWIFT-LABEL: main:
define i32 @main() {
entry:
br label %for.body
Modified: llvm/trunk/test/CodeGen/ARM/neon_minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon_minmax.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/neon_minmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/neon_minmax.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
define float @fmin_ole(float %x) nounwind {
-;CHECK: fmin_ole:
+;CHECK-LABEL: fmin_ole:
;CHECK: vmin.f32
%cond = fcmp ole float 1.0, %x
%min1 = select i1 %cond, float 1.0, float %x
@@ -9,7 +9,7 @@ define float @fmin_ole(float %x) nounwin
}
define float @fmin_ole_zero(float %x) nounwind {
-;CHECK: fmin_ole_zero:
+;CHECK-LABEL: fmin_ole_zero:
;CHECK-NOT: vmin.f32
%cond = fcmp ole float 0.0, %x
%min1 = select i1 %cond, float 0.0, float %x
@@ -17,7 +17,7 @@ define float @fmin_ole_zero(float %x) no
}
define float @fmin_ult(float %x) nounwind {
-;CHECK: fmin_ult:
+;CHECK-LABEL: fmin_ult:
;CHECK: vmin.f32
%cond = fcmp ult float %x, 1.0
%min1 = select i1 %cond, float %x, float 1.0
@@ -25,7 +25,7 @@ define float @fmin_ult(float %x) nounwin
}
define float @fmax_ogt(float %x) nounwind {
-;CHECK: fmax_ogt:
+;CHECK-LABEL: fmax_ogt:
;CHECK: vmax.f32
%cond = fcmp ogt float 1.0, %x
%max1 = select i1 %cond, float 1.0, float %x
@@ -33,7 +33,7 @@ define float @fmax_ogt(float %x) nounwin
}
define float @fmax_uge(float %x) nounwind {
-;CHECK: fmax_uge:
+;CHECK-LABEL: fmax_uge:
;CHECK: vmax.f32
%cond = fcmp uge float %x, 1.0
%max1 = select i1 %cond, float %x, float 1.0
@@ -41,7 +41,7 @@ define float @fmax_uge(float %x) nounwin
}
define float @fmax_uge_zero(float %x) nounwind {
-;CHECK: fmax_uge_zero:
+;CHECK-LABEL: fmax_uge_zero:
;CHECK-NOT: vmax.f32
%cond = fcmp uge float %x, 0.0
%max1 = select i1 %cond, float %x, float 0.0
@@ -49,7 +49,7 @@ define float @fmax_uge_zero(float %x) no
}
define float @fmax_olt_reverse(float %x) nounwind {
-;CHECK: fmax_olt_reverse:
+;CHECK-LABEL: fmax_olt_reverse:
;CHECK: vmax.f32
%cond = fcmp olt float %x, 1.0
%max1 = select i1 %cond, float 1.0, float %x
@@ -57,7 +57,7 @@ define float @fmax_olt_reverse(float %x)
}
define float @fmax_ule_reverse(float %x) nounwind {
-;CHECK: fmax_ule_reverse:
+;CHECK-LABEL: fmax_ule_reverse:
;CHECK: vmax.f32
%cond = fcmp ult float 1.0, %x
%max1 = select i1 %cond, float %x, float 1.0
@@ -65,7 +65,7 @@ define float @fmax_ule_reverse(float %x)
}
define float @fmin_oge_reverse(float %x) nounwind {
-;CHECK: fmin_oge_reverse:
+;CHECK-LABEL: fmin_oge_reverse:
;CHECK: vmin.f32
%cond = fcmp oge float %x, 1.0
%min1 = select i1 %cond, float 1.0, float %x
@@ -73,7 +73,7 @@ define float @fmin_oge_reverse(float %x)
}
define float @fmin_ugt_reverse(float %x) nounwind {
-;CHECK: fmin_ugt_reverse:
+;CHECK-LABEL: fmin_ugt_reverse:
;CHECK: vmin.f32
%cond = fcmp ugt float 1.0, %x
%min1 = select i1 %cond, float %x, float 1.0
Modified: llvm/trunk/test/CodeGen/ARM/peephole-bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/peephole-bitcast.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/peephole-bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/peephole-bitcast.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@
define void @t(float %x) nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: vmov
; CHECK: bl
%0 = bitcast float %x to i32
Modified: llvm/trunk/test/CodeGen/ARM/popcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/popcnt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/popcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/popcnt.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; Implement ctpop with vcnt
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nou
}
define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -18,7 +18,7 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A)
}
define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
-; CHECK: vcnt16:
+; CHECK-LABEL: vcnt16:
; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -30,7 +30,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A)
}
define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
-; CHECK: vcntQ16:
+; CHECK-LABEL: vcntQ16:
; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -42,7 +42,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A)
}
define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
-; CHECK: vcnt32:
+; CHECK-LABEL: vcnt32:
; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -57,7 +57,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A)
}
define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
-; CHECK: vcntQ32:
+; CHECK-LABEL: vcntQ32:
; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -79,7 +79,7 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -87,7 +87,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nou
}
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -95,7 +95,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A)
}
define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -103,7 +103,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A)
}
define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -111,7 +111,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A)
}
define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -119,7 +119,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A)
}
define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -135,7 +135,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
;CHECK: vcls.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -143,7 +143,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) no
}
define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
;CHECK: vcls.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -151,7 +151,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A)
}
define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
;CHECK: vcls.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -159,7 +159,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A)
}
define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
;CHECK: vcls.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -167,7 +167,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A)
}
define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
;CHECK: vcls.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -175,7 +175,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A
}
define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
;CHECK: vcls.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Sun Jul 14 01:24:09 2013
@@ -6,15 +6,15 @@
define void @t1(i8* %ptr) nounwind {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM-NOT: pldw [r0]
; ARM: pld [r0]
-; ARM-MP: t1:
+; ARM-MP-LABEL: t1:
; ARM-MP: pldw [r0]
; ARM-MP: pld [r0]
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
; THUMB2-NOT: pldw [r0]
; THUMB2: pld [r0]
tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
@@ -24,10 +24,10 @@ entry:
define void @t2(i8* %ptr) nounwind {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: pld [r0, #1023]
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
; THUMB2: pld [r0, #1023]
%tmp = getelementptr i8* %ptr, i32 1023
tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
@@ -36,10 +36,10 @@ entry:
define void @t3(i32 %base, i32 %offset) nounwind {
entry:
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: pld [r0, r1, lsr #2]
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
; THUMB2: lsrs r1, r1, #2
; THUMB2: pld [r0, r1]
%tmp1 = lshr i32 %offset, 2
@@ -51,10 +51,10 @@ entry:
define void @t4(i32 %base, i32 %offset) nounwind {
entry:
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: pld [r0, r1, lsl #2]
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
; THUMB2: pld [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
@@ -67,10 +67,10 @@ declare void @llvm.prefetch(i8*, i32, i3
define void @t5(i8* %ptr) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM: pli [r0]
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
; THUMB2: pli [r0]
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
ret void
Modified: llvm/trunk/test/CodeGen/ARM/private.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/private.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/private.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/private.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
;
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
; CHECK: .Lfoo:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: bl .Lfoo
; CHECK: .long .Lbaz
; CHECK: .Lbaz:
Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vld1.16
; CHECK-NOT: vmov d
; CHECK: vmovl.s16
@@ -44,7 +44,7 @@ entry:
define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: vld1.16
; CHECK-NOT: vmov
; CHECK: vmul.i16
@@ -73,7 +73,7 @@ entry:
}
define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vld3.8
; CHECK: vmul.i8
; CHECK: vmov r
@@ -92,7 +92,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) noun
define void @t4(i32* %in, i32* %out) nounwind {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vld2.32
; CHECK-NOT: vmov
; CHECK: vld2.32
@@ -135,7 +135,7 @@ return2:
}
define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: vld1.32
; How can FileCheck match Q and D registers? We need a lisp interpreter.
; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -153,7 +153,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>*
}
define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: vldr
; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}
@@ -167,7 +167,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B
define void @t7(i32* %iptr, i32* %optr) nounwind {
entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: vld2.32
; CHECK: vst2.32
; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},
@@ -189,7 +189,7 @@ entry:
; PR7156
define arm_aapcs_vfpcc i32 @t8() nounwind {
-; CHECK: t8:
+; CHECK-LABEL: t8:
; CHECK: vrsqrte.f32 q8, q8
bb.nph55.bb.nph55.split_crit_edge:
br label %bb3
@@ -238,7 +238,7 @@ bb14:
; PR7157
define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
-; CHECK: t9:
+; CHECK-LABEL: t9:
; CHECK: vldr
; CHECK-NOT: vmov d{{.*}}, d16
; CHECK: vmov.i32 d17
@@ -270,7 +270,7 @@ define arm_aapcs_vfpcc float @t9(%0* noc
; PR7162
define arm_aapcs_vfpcc i32 @t10() nounwind {
entry:
-; CHECK: t10:
+; CHECK-LABEL: t10:
; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000
; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]
; CHECK: vadd.f32 q8, q8, q8
Modified: llvm/trunk/test/CodeGen/ARM/ret_sret_vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ret_sret_vector.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ret_sret_vector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ret_sret_vector.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios3.0.0"
define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) {
%foo = fadd <4 x double> %a, %b
ret <4 x double> %foo
-; CHECK: PR14337:
+; CHECK-LABEL: PR14337:
; CHECK: vst1.64
; CHECK: vst1.64
}
Modified: llvm/trunk/test/CodeGen/ARM/sbfx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sbfx.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sbfx.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sbfx.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define i32 @f1(i32 %a) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sbfx r0, r0, #0, #20
%tmp = shl i32 %a, 12
%tmp2 = ashr i32 %tmp, 12
@@ -11,7 +11,7 @@ entry:
define i32 @f2(i32 %a) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bfc r0, #20, #12
%tmp = shl i32 %a, 12
%tmp2 = lshr i32 %tmp, 12
@@ -20,7 +20,7 @@ entry:
define i32 @f3(i32 %a) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sbfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = ashr i32 %tmp, 29
@@ -29,7 +29,7 @@ entry:
define i32 @f4(i32 %a) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ubfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = lshr i32 %tmp, 29
@@ -38,7 +38,7 @@ entry:
define i32 @f5(i32 %a) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: sbfx
; CHECK: bx
%tmp = shl i32 %a, 3
Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Sun Jul 14 01:24:09 2013
@@ -4,16 +4,16 @@
define i32 @t1(i32 %c) nounwind readnone {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: mov [[R1:r[0-9]+]], #101
; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
; ARM: movgt r0, #123
-; ARMT2: t1:
+; ARMT2-LABEL: t1:
; ARMT2: movw r0, #357
; ARMT2: movgt r0, #123
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
; THUMB2: movw r0, #357
; THUMB2: movgt r0, #123
@@ -24,16 +24,16 @@ entry:
define i32 @t2(i32 %c) nounwind readnone {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: mov r0, #123
; ARM: movgt r0, #101
; ARM: orrgt r0, r0, #256
-; ARMT2: t2:
+; ARMT2-LABEL: t2:
; ARMT2: mov r0, #123
; ARMT2: movwgt r0, #357
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
; THUMB2: mov{{(s|\.w)}} r0, #123
; THUMB2: movwgt r0, #357
@@ -44,15 +44,15 @@ entry:
define i32 @t3(i32 %a) nounwind readnone {
entry:
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: mov r0, #0
; ARM: moveq r0, #1
-; ARMT2: t3:
+; ARMT2-LABEL: t3:
; ARMT2: mov r0, #0
; ARMT2: moveq r0, #1
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
; THUMB2: mov{{(s|\.w)}} r0, #0
; THUMB2: moveq r0, #1
%0 = icmp eq i32 %a, 160
@@ -62,15 +62,15 @@ entry:
define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
entry:
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: ldr
; ARM: mov{{lt|ge}}
-; ARMT2: t4:
+; ARMT2-LABEL: t4:
; ARMT2: movwlt [[R0:r[0-9]+]], #65365
; ARMT2: movtlt [[R0]], #65365
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
%0 = icmp slt i32 %a, %b
%1 = select i1 %0, i32 4283826005, i32 %x
@@ -80,13 +80,13 @@ entry:
; rdar://9758317
define i32 @t5(i32 %a) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM-NOT: mov
; ARM: cmp r0, #1
; ARM-NOT: mov
; ARM: movne r0, #0
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
; THUMB2-NOT: mov
; THUMB2: cmp r0, #1
; THUMB2: it ne
@@ -98,12 +98,12 @@ entry:
define i32 @t6(i32 %a) nounwind {
entry:
-; ARM: t6:
+; ARM-LABEL: t6:
; ARM-NOT: mov
; ARM: cmp r0, #0
; ARM: movne r0, #1
-; THUMB2: t6:
+; THUMB2-LABEL: t6:
; THUMB2-NOT: mov
; THUMB2: cmp r0, #0
; THUMB2: it ne
Modified: llvm/trunk/test/CodeGen/ARM/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
define i32 @f1(i32 %a.s) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: moveq
entry:
%tmp = icmp eq i32 %a.s, 4
@@ -12,7 +12,7 @@ entry:
}
define i32 @f2(i32 %a.s) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: movgt
entry:
%tmp = icmp sgt i32 %a.s, 4
@@ -21,7 +21,7 @@ entry:
}
define i32 @f3(i32 %a.s, i32 %b.s) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: movlt
entry:
%tmp = icmp slt i32 %a.s, %b.s
@@ -30,7 +30,7 @@ entry:
}
define i32 @f4(i32 %a.s, i32 %b.s) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: movle
entry:
%tmp = icmp sle i32 %a.s, %b.s
@@ -39,7 +39,7 @@ entry:
}
define i32 @f5(i32 %a.u, i32 %b.u) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: movls
entry:
%tmp = icmp ule i32 %a.u, %b.u
@@ -48,7 +48,7 @@ entry:
}
define i32 @f6(i32 %a.u, i32 %b.u) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: movhi
entry:
%tmp = icmp ugt i32 %a.u, %b.u
@@ -57,10 +57,10 @@ entry:
}
define double @f7(double %a, double %b) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: movlt
;CHECK: movlt
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vmovmi
%tmp = fcmp olt double %a, 1.234e+00
%tmp1 = select i1 %tmp, double -1.000e+00, double %b
@@ -94,7 +94,7 @@ define arm_apcscc float @f8(i32 %a) noun
; Glue values can only have a single use, but the following test exposed a
; case where a SELECT was lowered with 2 uses of a comparison, causing the
; scheduler to assert.
-; CHECK-VFP: f9:
+; CHECK-VFP-LABEL: f9:
declare i8* @objc_msgSend(i8*, i8*, ...)
define void @f9() optsize {
Modified: llvm/trunk/test/CodeGen/ARM/select_xform.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select_xform.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select_xform.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select_xform.ll Sun Jul 14 01:24:09 2013
@@ -3,11 +3,11 @@
; rdar://8662825
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: suble r1, r1, #-2147483647
; ARM: mov r0, r1
-; T2: t1:
+; T2-LABEL: t1:
; T2: mvn r0, #-2147483648
; T2: addle r1, r0
; T2: mov r0, r1
@@ -18,11 +18,11 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) n
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: suble r1, r1, #10
; ARM: mov r0, r1
-; T2: t2:
+; T2-LABEL: t2:
; T2: suble r1, #10
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
@@ -32,11 +32,11 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i
}
define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: andge r3, r3, r2
; ARM: mov r0, r3
-; T2: t3:
+; T2-LABEL: t3:
; T2: andge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
@@ -46,11 +46,11 @@ define i32 @t3(i32 %a, i32 %b, i32 %x, i
}
define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: orrge r3, r3, r2
; ARM: mov r0, r3
-; T2: t4:
+; T2-LABEL: t4:
; T2: orrge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
@@ -61,11 +61,11 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i
define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM-NOT: moveq
; ARM: orreq r2, r2, #1
-; T2: t5:
+; T2-LABEL: t5:
; T2-NOT: moveq
; T2: orreq r2, r2, #1
%tmp1 = icmp eq i32 %a, %b
@@ -75,11 +75,11 @@ entry:
}
define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t6:
+; ARM-LABEL: t6:
; ARM-NOT: movge
; ARM: eorlt r3, r3, r2
-; T2: t6:
+; T2-LABEL: t6:
; T2-NOT: movge
; T2: eorlt r3, r2
%cond = icmp slt i32 %a, %b
@@ -90,11 +90,11 @@ define i32 @t6(i32 %a, i32 %b, i32 %c, i
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
entry:
-; ARM: t7:
+; ARM-LABEL: t7:
; ARM-NOT: lsleq
; ARM: andeq r2, r2, r2, lsl #1
-; T2: t7:
+; T2-LABEL: t7:
; T2-NOT: lsleq.w
; T2: andeq.w r2, r2, r2, lsl #1
%tmp1 = shl i32 %c, 1
@@ -106,11 +106,11 @@ entry:
; Fold ORRri into movcc.
define i32 @t8(i32 %a, i32 %b) nounwind {
-; ARM: t8:
+; ARM-LABEL: t8:
; ARM: cmp r0, r1
; ARM: orrge r0, r1, #1
-; T2: t8:
+; T2-LABEL: t8:
; T2: cmp r0, r1
; T2: orrge r0, r1, #1
%x = or i32 %b, 1
@@ -121,11 +121,11 @@ define i32 @t8(i32 %a, i32 %b) nounwind
; Fold ANDrr into movcc.
define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t9:
+; ARM-LABEL: t9:
; ARM: cmp r0, r1
; ARM: andge r0, r1, r2
-; T2: t9:
+; T2-LABEL: t9:
; T2: cmp r0, r1
; T2: andge.w r0, r1, r2
%x = and i32 %b, %c
@@ -136,11 +136,11 @@ define i32 @t9(i32 %a, i32 %b, i32 %c) n
; Fold EORrs into movcc.
define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t10:
+; ARM-LABEL: t10:
; ARM: cmp r0, r1
; ARM: eorge r0, r1, r2, lsl #7
-; T2: t10:
+; T2-LABEL: t10:
; T2: cmp r0, r1
; T2: eorge.w r0, r1, r2, lsl #7
%s = shl i32 %c, 7
@@ -152,11 +152,11 @@ define i32 @t10(i32 %a, i32 %b, i32 %c,
; Fold ORRri into movcc, reversing the condition.
define i32 @t11(i32 %a, i32 %b) nounwind {
-; ARM: t11:
+; ARM-LABEL: t11:
; ARM: cmp r0, r1
; ARM: orrlt r0, r1, #1
-; T2: t11:
+; T2-LABEL: t11:
; T2: cmp r0, r1
; T2: orrlt r0, r1, #1
%x = or i32 %b, 1
@@ -167,11 +167,11 @@ define i32 @t11(i32 %a, i32 %b) nounwind
; Fold ADDri12 into movcc
define i32 @t12(i32 %a, i32 %b) nounwind {
-; ARM: t12:
+; ARM-LABEL: t12:
; ARM: cmp r0, r1
; ARM: addge r0, r1,
-; T2: t12:
+; T2-LABEL: t12:
; T2: cmp r0, r1
; T2: addwge r0, r1, #3000
%x = add i32 %b, 3000
Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/spill-q.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/spill-q.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/spill-q.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@
declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
; CHECK: bic {{.*}}, #15
; CHECK: vst1.64 {{.*}}sp:128
; CHECK: vld1.64 {{.*}}sp:128
Modified: llvm/trunk/test/CodeGen/ARM/struct_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/struct_byval.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/struct_byval.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/struct_byval.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
define i32 @f() nounwind ssp {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldr
; CHECK: str
; CHECK-NOT:bne
@@ -18,7 +18,7 @@ entry:
; Generate a loop for large struct byval
define i32 @g() nounwind ssp {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: ldr
; CHECK: sub
; CHECK: str
@@ -31,7 +31,7 @@ entry:
; Generate a loop using NEON instructions
define i32 @h() nounwind ssp {
entry:
-; CHECK: h:
+; CHECK-LABEL: h:
; CHECK: vld1
; CHECK: sub
; CHECK: vst1
Modified: llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b
@@ -13,7 +13,7 @@ entry:
define i32 @g(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp slt i32 %a, %b
@@ -24,7 +24,7 @@ entry:
define i32 @h(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: h:
+; CHECK-LABEL: h:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, 3
@@ -36,7 +36,7 @@ entry:
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
entry:
-; CHECK: i:
+; CHECK-LABEL: i:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp ult i32 %a, %b
@@ -48,7 +48,7 @@ entry:
; a swapped sub.
define i32 @j(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: j:
+; CHECK-LABEL: j:
; CHECK: sub
; CHECK: cmp
%cmp = icmp eq i32 %b, %a
Modified: llvm/trunk/test/CodeGen/ARM/tail-dup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-dup.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tail-dup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/tail-dup.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; We should be able to tail-duplicate the basic block containing the indirectbr
; into all of its predecessors.
-; CHECK: fn:
+; CHECK-LABEL: fn:
; CHECK: mov pc
; CHECK: mov pc
; CHECK: mov pc
Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Sun Jul 14 01:24:09 2013
@@ -14,7 +14,7 @@ declare i8* @choose(i8*, i8*)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
; CHECK: qux
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
Modified: llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll Sun Jul 14 01:24:09 2013
@@ -14,7 +14,7 @@
; rdar://10674430
define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
entry:
-; CHECK: sharedidx:
+; CHECK-LABEL: sharedidx:
%cmp8 = icmp eq i32 %len, 0
br i1 %cmp8, label %for.end, label %for.body
Modified: llvm/trunk/test/CodeGen/ARM/tls-models.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tls-models.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tls-models.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/tls-models.ll Sun Jul 14 01:24:09 2013
@@ -21,9 +21,9 @@ entry:
ret i32* @external_gd
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
- ; CHECK-NONPIC: f1:
+ ; CHECK-NONPIC-LABEL: f1:
; CHECK-NONPIC: external_gd(gottpoff)
- ; CHECK-PIC: f1:
+ ; CHECK-PIC-LABEL: f1:
; CHECK-PIC: external_gd(tlsgd)
}
@@ -33,9 +33,9 @@ entry:
; Non-PIC code can use local exec, PIC code can use local dynamic,
; but that is not implemented, so falls back to general dynamic.
- ; CHECK-NONPIC: f2:
+ ; CHECK-NONPIC-LABEL: f2:
; CHECK-NONPIC: internal_gd(tpoff)
- ; CHECK-PIC: f2:
+ ; CHECK-PIC-LABEL: f2:
; CHECK-PIC: internal_gd(tlsgd)
}
@@ -48,9 +48,9 @@ entry:
; Non-PIC code can use initial exec, PIC should use local dynamic,
; but that is not implemented, so falls back to general dynamic.
- ; CHECK-NONPIC: f3:
+ ; CHECK-NONPIC-LABEL: f3:
; CHECK-NONPIC: external_ld(gottpoff)
- ; CHECK-PIC: f3:
+ ; CHECK-PIC-LABEL: f3:
; CHECK-PIC: external_ld(tlsgd)
}
@@ -60,9 +60,9 @@ entry:
; Non-PIC code can use local exec, PIC code can use local dynamic,
; but that is not implemented, so it falls back to general dynamic.
- ; CHECK-NONPIC: f4:
+ ; CHECK-NONPIC-LABEL: f4:
; CHECK-NONPIC: internal_ld(tpoff)
- ; CHECK-PIC: f4:
+ ; CHECK-PIC-LABEL: f4:
; CHECK-PIC: internal_ld(tlsgd)
}
@@ -74,9 +74,9 @@ entry:
ret i32* @external_ie
; Non-PIC and PIC code will use initial exec as specified.
- ; CHECK-NONPIC: f5:
+ ; CHECK-NONPIC-LABEL: f5:
; CHECK-NONPIC: external_ie(gottpoff)
- ; CHECK-PIC: f5:
+ ; CHECK-PIC-LABEL: f5:
; CHECK-PIC: external_ie(gottpoff)
}
@@ -85,9 +85,9 @@ entry:
ret i32* @internal_ie
; Non-PIC code can use local exec, PIC code use initial exec as specified.
- ; CHECK-NONPIC: f6:
+ ; CHECK-NONPIC-LABEL: f6:
; CHECK-NONPIC: internal_ie(tpoff)
- ; CHECK-PIC: f6:
+ ; CHECK-PIC-LABEL: f6:
; CHECK-PIC: internal_ie(gottpoff)
}
@@ -99,9 +99,9 @@ entry:
ret i32* @external_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f7:
+ ; CHECK-NONPIC-LABEL: f7:
; CHECK-NONPIC: external_le(tpoff)
- ; CHECK-PIC: f7:
+ ; CHECK-PIC-LABEL: f7:
; CHECK-PIC: external_le(tpoff)
}
@@ -110,8 +110,8 @@ entry:
ret i32* @internal_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f8:
+ ; CHECK-NONPIC-LABEL: f8:
; CHECK-NONPIC: internal_le(tpoff)
- ; CHECK-PIC: f8:
+ ; CHECK-PIC-LABEL: f8:
; CHECK-PIC: internal_le(tpoff)
}
Modified: llvm/trunk/test/CodeGen/ARM/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tls2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tls2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/tls2.ll Sun Jul 14 01:24:09 2013
@@ -6,10 +6,10 @@
@i = external thread_local global i32 ; <i32*> [#uses=2]
define i32 @f() {
-; CHECK-NONPIC: f:
+; CHECK-NONPIC-LABEL: f:
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
; CHECK-PIC: __tls_get_addr
entry:
%tmp1 = load i32* @i ; <i32> [#uses=1]
@@ -17,10 +17,10 @@ entry:
}
define i32* @g() {
-; CHECK-NONPIC: g:
+; CHECK-NONPIC-LABEL: g:
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
; CHECK-PIC: __tls_get_addr
entry:
ret i32* @i
Modified: llvm/trunk/test/CodeGen/ARM/trap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/trap.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/trap.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/trap.ll Sun Jul 14 01:24:09 2013
@@ -23,10 +23,10 @@
define void @t() nounwind {
entry:
-; INSTR: t:
+; INSTR-LABEL: t:
; INSTR: trap
-; FUNC: t:
+; FUNC-LABEL: t:
; FUNC: bl __trap
; ENCODING-NACL: f0 de fe e7
@@ -39,10 +39,10 @@ entry:
define void @t2() nounwind {
entry:
-; INSTR: t2:
+; INSTR-LABEL: t2:
; INSTR: trap
-; FUNC: t2:
+; FUNC-LABEL: t2:
; FUNC: bl __trap
; ENCODING-NACL: f0 de fe e7
Modified: llvm/trunk/test/CodeGen/ARM/twoaddrinstr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/twoaddrinstr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/twoaddrinstr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/twoaddrinstr.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
define void @PR13378() nounwind {
; This was orriginally a crasher trying to schedule the instructions.
-; CHECK: PR13378:
+; CHECK-LABEL: PR13378:
; CHECK: vld1.32
; CHECK-NEXT: vst1.32
; CHECK-NEXT: vst1.32
Modified: llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
-; EXPANDED: t:
+; EXPANDED-LABEL: t:
; EXPANDED: ldrb [[R2:r[0-9]+]]
; EXPANDED: ldrb [[R3:r[0-9]+]]
; EXPANDED: ldrb [[R12:r[0-9]+]]
@@ -17,7 +17,7 @@ entry:
; EXPANDED: strb [[R3]]
; EXPANDED: strb [[R2]]
-; UNALIGNED: t:
+; UNALIGNED-LABEL: t:
; UNALIGNED: ldr r1
; UNALIGNED: str r1
@@ -30,13 +30,13 @@ entry:
define void @hword(double* %a, double* %b) nounwind {
entry:
-; EXPANDED: hword:
+; EXPANDED-LABEL: hword:
; EXPANDED-NOT: vld1
; EXPANDED: ldrh
; EXPANDED-NOT: str1
; EXPANDED: strh
-; UNALIGNED: hword:
+; UNALIGNED-LABEL: hword:
; UNALIGNED: vld1.16
; UNALIGNED: vst1.16
%tmp = load double* %a, align 2
@@ -46,13 +46,13 @@ entry:
define void @byte(double* %a, double* %b) nounwind {
entry:
-; EXPANDED: byte:
+; EXPANDED-LABEL: byte:
; EXPANDED-NOT: vld1
; EXPANDED: ldrb
; EXPANDED-NOT: str1
; EXPANDED: strb
-; UNALIGNED: byte:
+; UNALIGNED-LABEL: byte:
; UNALIGNED: vld1.8
; UNALIGNED: vst1.8
%tmp = load double* %a, align 1
@@ -62,11 +62,11 @@ entry:
define void @byte_word_ops(i32* %a, i32* %b) nounwind {
entry:
-; EXPANDED: byte_word_ops:
+; EXPANDED-LABEL: byte_word_ops:
; EXPANDED: ldrb
; EXPANDED: strb
-; UNALIGNED: byte_word_ops:
+; UNALIGNED-LABEL: byte_word_ops:
; UNALIGNED-NOT: ldrb
; UNALIGNED: ldr
; UNALIGNED-NOT: strb
Modified: llvm/trunk/test/CodeGen/ARM/unaligned_load_store_vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unaligned_load_store_vector.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/unaligned_load_store_vector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/unaligned_load_store_vector.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_1:
+;CHECK-LABEL: v64_v8i8_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -22,7 +22,7 @@ entry:
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_1:
+;CHECK-LABEL: v64_v4i16_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -40,7 +40,7 @@ entry:
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_1:
+;CHECK-LABEL: v64_v2i32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -58,7 +58,7 @@ entry:
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_1:
+;CHECK-LABEL: v64_v2f32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -76,7 +76,7 @@ entry:
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_1:
+;CHECK-LABEL: v128_v16i8_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -94,7 +94,7 @@ entry:
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_1:
+;CHECK-LABEL: v128_v8i16_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -112,7 +112,7 @@ entry:
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_1:
+;CHECK-LABEL: v128_v4i32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -130,7 +130,7 @@ entry:
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_1:
+;CHECK-LABEL: v128_v2i64_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -148,7 +148,7 @@ entry:
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_1:
+;CHECK-LABEL: v128_v4f32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -166,7 +166,7 @@ entry:
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_2:
+;CHECK-LABEL: v64_v8i8_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -184,7 +184,7 @@ entry:
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_2:
+;CHECK-LABEL: v64_v4i16_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -202,7 +202,7 @@ entry:
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_2:
+;CHECK-LABEL: v64_v2i32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -220,7 +220,7 @@ entry:
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_2:
+;CHECK-LABEL: v64_v2f32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -238,7 +238,7 @@ entry:
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_2:
+;CHECK-LABEL: v128_v16i8_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -256,7 +256,7 @@ entry:
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_2:
+;CHECK-LABEL: v128_v8i16_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -274,7 +274,7 @@ entry:
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_2:
+;CHECK-LABEL: v128_v4i32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -292,7 +292,7 @@ entry:
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_2:
+;CHECK-LABEL: v128_v2i64_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -310,7 +310,7 @@ entry:
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_2:
+;CHECK-LABEL: v128_v4f32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -328,7 +328,7 @@ entry:
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_4:
+;CHECK-LABEL: v64_v8i8_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -346,7 +346,7 @@ entry:
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_4:
+;CHECK-LABEL: v64_v4i16_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -364,7 +364,7 @@ entry:
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_4:
+;CHECK-LABEL: v64_v2i32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -382,7 +382,7 @@ entry:
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_4:
+;CHECK-LABEL: v64_v2f32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -400,7 +400,7 @@ entry:
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_4:
+;CHECK-LABEL: v128_v16i8_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -418,7 +418,7 @@ entry:
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_4:
+;CHECK-LABEL: v128_v8i16_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -436,7 +436,7 @@ entry:
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_4:
+;CHECK-LABEL: v128_v4i32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -454,7 +454,7 @@ entry:
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_4:
+;CHECK-LABEL: v128_v2i64_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
@@ -472,7 +472,7 @@ entry:
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_4:
+;CHECK-LABEL: v128_v4f32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
Modified: llvm/trunk/test/CodeGen/ARM/undef-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/undef-sext.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/undef-sext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/undef-sext.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
define i32 @t(i32* %a) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
%0 = sext i16 undef to i32
Modified: llvm/trunk/test/CodeGen/ARM/unwind-init.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unwind-init.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/unwind-init.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/unwind-init.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@ define void @calls_unwind_init() {
ret void
}
-; CHECK: calls_unwind_init:
+; CHECK-LABEL: calls_unwind_init:
; CHECK: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
Modified: llvm/trunk/test/CodeGen/ARM/v1-constant-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/v1-constant-fold.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/v1-constant-fold.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/v1-constant-fold.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; PR15611. Check that we don't crash when constant folding v1i32 types.
-; CHECK: foo:
+; CHECK-LABEL: foo:
define void @foo(i32 %arg) {
bb:
%tmp = insertelement <4 x i32> undef, i32 %arg, i32 0
Modified: llvm/trunk/test/CodeGen/ARM/vaba.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaba.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vaba.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vaba.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabas8:
+;CHECK-LABEL: vabas8:
;CHECK: vaba.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8
}
define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabas16:
+;CHECK-LABEL: vabas16:
;CHECK: vaba.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vabas16(<4 x i16>* %A,
}
define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabas32:
+;CHECK-LABEL: vabas32:
;CHECK: vaba.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vabas32(<2 x i32>* %A,
}
define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabau8:
+;CHECK-LABEL: vabau8:
;CHECK: vaba.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -45,7 +45,7 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8
}
define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabau16:
+;CHECK-LABEL: vabau16:
;CHECK: vaba.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -56,7 +56,7 @@ define <4 x i16> @vabau16(<4 x i16>* %A,
}
define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabau32:
+;CHECK-LABEL: vabau32:
;CHECK: vaba.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -67,7 +67,7 @@ define <2 x i32> @vabau32(<2 x i32>* %A,
}
define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQs8:
+;CHECK-LABEL: vabaQs8:
;CHECK: vaba.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A,
}
define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQs16:
+;CHECK-LABEL: vabaQs16:
;CHECK: vaba.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -89,7 +89,7 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A
}
define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQs32:
+;CHECK-LABEL: vabaQs32:
;CHECK: vaba.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A
}
define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQu8:
+;CHECK-LABEL: vabaQu8:
;CHECK: vaba.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A,
}
define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQu16:
+;CHECK-LABEL: vabaQu16:
;CHECK: vaba.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A
}
define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQu32:
+;CHECK-LABEL: vabaQu32:
;CHECK: vaba.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -149,7 +149,7 @@ declare <8 x i16> @llvm.arm.neon.vabdu.v
declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabals8:
+;CHECK-LABEL: vabals8:
;CHECK: vabal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i16> @vabals8(<8 x i16>* %A,
}
define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabals16:
+;CHECK-LABEL: vabals16:
;CHECK: vabal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -173,7 +173,7 @@ define <4 x i32> @vabals16(<4 x i32>* %A
}
define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabals32:
+;CHECK-LABEL: vabals32:
;CHECK: vabal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -185,7 +185,7 @@ define <2 x i64> @vabals32(<2 x i64>* %A
}
define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabalu8:
+;CHECK-LABEL: vabalu8:
;CHECK: vabal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vabalu8(<8 x i16>* %A,
}
define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabalu16:
+;CHECK-LABEL: vabalu16:
;CHECK: vabal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -209,7 +209,7 @@ define <4 x i32> @vabalu16(<4 x i32>* %A
}
define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabalu32:
+;CHECK-LABEL: vabalu32:
;CHECK: vabal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vabd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vabd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vabd.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabds8:
+;CHECK-LABEL: vabds8:
;CHECK: vabd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8
}
define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabds16:
+;CHECK-LABEL: vabds16:
;CHECK: vabd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vabds16(<4 x i16>* %A,
}
define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabds32:
+;CHECK-LABEL: vabds32:
;CHECK: vabd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vabds32(<2 x i32>* %A,
}
define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdu8:
+;CHECK-LABEL: vabdu8:
;CHECK: vabd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8
}
define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdu16:
+;CHECK-LABEL: vabdu16:
;CHECK: vabd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vabdu16(<4 x i16>* %A,
}
define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdu32:
+;CHECK-LABEL: vabdu32:
;CHECK: vabd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vabdu32(<2 x i32>* %A,
}
define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vabdf32:
+;CHECK-LABEL: vabdf32:
;CHECK: vabd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vabdf32(<2 x float>*
}
define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQs8:
+;CHECK-LABEL: vabdQs8:
;CHECK: vabd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A,
}
define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQs16:
+;CHECK-LABEL: vabdQs16:
;CHECK: vabd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A
}
define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQs32:
+;CHECK-LABEL: vabdQs32:
;CHECK: vabd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A
}
define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQu8:
+;CHECK-LABEL: vabdQu8:
;CHECK: vabd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A,
}
define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQu16:
+;CHECK-LABEL: vabdQu16:
;CHECK: vabd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A
}
define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQu32:
+;CHECK-LABEL: vabdQu32:
;CHECK: vabd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A
}
define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vabdQf32:
+;CHECK-LABEL: vabdQf32:
;CHECK: vabd.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v
declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdls8:
+;CHECK-LABEL: vabdls8:
;CHECK: vabdl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -157,7 +157,7 @@ define <8 x i16> @vabdls8(<8 x i8>* %A,
}
define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdls16:
+;CHECK-LABEL: vabdls16:
;CHECK: vabdl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -167,7 +167,7 @@ define <4 x i32> @vabdls16(<4 x i16>* %A
}
define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdls32:
+;CHECK-LABEL: vabdls32:
;CHECK: vabdl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -177,7 +177,7 @@ define <2 x i64> @vabdls32(<2 x i32>* %A
}
define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdlu8:
+;CHECK-LABEL: vabdlu8:
;CHECK: vabdl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -187,7 +187,7 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A,
}
define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdlu16:
+;CHECK-LABEL: vabdlu16:
;CHECK: vabdl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -197,7 +197,7 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A
}
define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdlu32:
+;CHECK-LABEL: vabdlu32:
;CHECK: vabdl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vabs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vabs.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
-;CHECK: vabss8:
+;CHECK-LABEL: vabss8:
;CHECK: vabs.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
@@ -9,7 +9,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) no
}
define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
-;CHECK: vabss16:
+;CHECK-LABEL: vabss16:
;CHECK: vabs.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A)
}
define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
-;CHECK: vabss32:
+;CHECK-LABEL: vabss32:
;CHECK: vabs.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
@@ -25,7 +25,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A)
}
define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
-;CHECK: vabsf32:
+;CHECK-LABEL: vabsf32:
;CHECK: vabs.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
@@ -33,7 +33,7 @@ define <2 x float> @vabsf32(<2 x float>*
}
define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vabsQs8:
+;CHECK-LABEL: vabsQs8:
;CHECK: vabs.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
@@ -41,7 +41,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A)
}
define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vabsQs16:
+;CHECK-LABEL: vabsQs16:
;CHECK: vabs.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
@@ -49,7 +49,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A
}
define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vabsQs32:
+;CHECK-LABEL: vabsQs32:
;CHECK: vabs.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
@@ -57,7 +57,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A
}
define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
-;CHECK: vabsQf32:
+;CHECK-LABEL: vabsQf32:
;CHECK: vabs.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
@@ -75,7 +75,7 @@ declare <4 x i32> @llvm.arm.neon.vabs.v4
declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
-;CHECK: vqabss8:
+;CHECK-LABEL: vqabss8:
;CHECK: vqabs.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
@@ -83,7 +83,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) n
}
define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
-;CHECK: vqabss16:
+;CHECK-LABEL: vqabss16:
;CHECK: vqabs.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
@@ -91,7 +91,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A
}
define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
-;CHECK: vqabss32:
+;CHECK-LABEL: vqabss32:
;CHECK: vqabs.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
@@ -99,7 +99,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A
}
define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqabsQs8:
+;CHECK-LABEL: vqabsQs8:
;CHECK: vqabs.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
@@ -107,7 +107,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A
}
define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqabsQs16:
+;CHECK-LABEL: vqabsQs16:
;CHECK: vqabs.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
@@ -115,7 +115,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %
}
define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqabsQs32:
+;CHECK-LABEL: vqabsQs32:
;CHECK: vqabs.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
Modified: llvm/trunk/test/CodeGen/ARM/vadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vadd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vadd.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddi8:
+;CHECK-LABEL: vaddi8:
;CHECK: vadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8
}
define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddi16:
+;CHECK-LABEL: vaddi16:
;CHECK: vadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vaddi16(<4 x i16>* %A,
}
define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddi32:
+;CHECK-LABEL: vaddi32:
;CHECK: vadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vaddi32(<2 x i32>* %A,
}
define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vaddi64:
+;CHECK-LABEL: vaddi64:
;CHECK: vadd.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vaddi64(<1 x i64>* %A,
}
define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vaddf32:
+;CHECK-LABEL: vaddf32:
;CHECK: vadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vaddf32(<2 x float>*
}
define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vaddQi8:
+;CHECK-LABEL: vaddQi8:
;CHECK: vadd.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A,
}
define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddQi16:
+;CHECK-LABEL: vaddQi16:
;CHECK: vadd.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A
}
define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddQi32:
+;CHECK-LABEL: vaddQi32:
;CHECK: vadd.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A
}
define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddQi64:
+;CHECK-LABEL: vaddQi64:
;CHECK: vadd.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A
}
define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vaddQf32:
+;CHECK-LABEL: vaddQf32:
;CHECK: vadd.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vaddQf32(<4 x float>
}
define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddhni16:
+;CHECK-LABEL: vaddhni16:
;CHECK: vaddhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vaddhni16(<8 x i16>* %A
}
define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddhni32:
+;CHECK-LABEL: vaddhni32:
;CHECK: vaddhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vaddhni32(<4 x i32>* %
}
define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddhni64:
+;CHECK-LABEL: vaddhni64:
;CHECK: vaddhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vaddhn.
declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vraddhni16:
+;CHECK-LABEL: vraddhni16:
;CHECK: vraddhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vraddhni16(<8 x i16>* %
}
define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vraddhni32:
+;CHECK-LABEL: vraddhni32:
;CHECK: vraddhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vraddhni32(<4 x i32>*
}
define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vraddhni64:
+;CHECK-LABEL: vraddhni64:
;CHECK: vraddhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vraddhn
declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddls8:
+;CHECK-LABEL: vaddls8:
;CHECK: vaddl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vaddls8(<8 x i8>* %A,
}
define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddls16:
+;CHECK-LABEL: vaddls16:
;CHECK: vaddl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vaddls16(<4 x i16>* %A
}
define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddls32:
+;CHECK-LABEL: vaddls32:
;CHECK: vaddl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vaddls32(<2 x i32>* %A
}
define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddlu8:
+;CHECK-LABEL: vaddlu8:
;CHECK: vaddl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A,
}
define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddlu16:
+;CHECK-LABEL: vaddlu16:
;CHECK: vaddl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A
}
define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddlu32:
+;CHECK-LABEL: vaddlu32:
;CHECK: vaddl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A
}
define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddws8:
+;CHECK-LABEL: vaddws8:
;CHECK: vaddw.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vaddws8(<8 x i16>* %A,
}
define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddws16:
+;CHECK-LABEL: vaddws16:
;CHECK: vaddw.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vaddws16(<4 x i32>* %A
}
define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddws32:
+;CHECK-LABEL: vaddws32:
;CHECK: vaddw.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vaddws32(<2 x i64>* %A
}
define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddwu8:
+;CHECK-LABEL: vaddwu8:
;CHECK: vaddw.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A,
}
define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddwu16:
+;CHECK-LABEL: vaddwu16:
;CHECK: vaddw.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A
}
define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddwu32:
+;CHECK-LABEL: vaddwu32:
;CHECK: vaddw.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vbits.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vbits.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_andi8:
+;CHECK-LABEL: v_andi8:
;CHECK: vand
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <
}
define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_andi16:
+;CHECK-LABEL: v_andi16:
;CHECK: vand
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A
}
define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_andi32:
+;CHECK-LABEL: v_andi32:
;CHECK: vand
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A
}
define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_andi64:
+;CHECK-LABEL: v_andi64:
;CHECK: vand
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A
}
define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_andQi8:
+;CHECK-LABEL: v_andQi8:
;CHECK: vand
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A
}
define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_andQi16:
+;CHECK-LABEL: v_andQi16:
;CHECK: vand
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %
}
define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_andQi32:
+;CHECK-LABEL: v_andQi32:
;CHECK: vand
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %
}
define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_andQi64:
+;CHECK-LABEL: v_andQi64:
;CHECK: vand
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %
}
define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_bici8:
+;CHECK-LABEL: v_bici8:
;CHECK: vbic
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <
}
define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_bici16:
+;CHECK-LABEL: v_bici16:
;CHECK: vbic
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A
}
define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_bici32:
+;CHECK-LABEL: v_bici32:
;CHECK: vbic
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -103,7 +103,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A
}
define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_bici64:
+;CHECK-LABEL: v_bici64:
;CHECK: vbic
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -113,7 +113,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A
}
define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_bicQi8:
+;CHECK-LABEL: v_bicQi8:
;CHECK: vbic
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -123,7 +123,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A
}
define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_bicQi16:
+;CHECK-LABEL: v_bicQi16:
;CHECK: vbic
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -133,7 +133,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %
}
define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_bicQi32:
+;CHECK-LABEL: v_bicQi32:
;CHECK: vbic
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -143,7 +143,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %
}
define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_bicQi64:
+;CHECK-LABEL: v_bicQi64:
;CHECK: vbic
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %
}
define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_eori8:
+;CHECK-LABEL: v_eori8:
;CHECK: veor
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -162,7 +162,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <
}
define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_eori16:
+;CHECK-LABEL: v_eori16:
;CHECK: veor
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -171,7 +171,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A
}
define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_eori32:
+;CHECK-LABEL: v_eori32:
;CHECK: veor
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -180,7 +180,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A
}
define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_eori64:
+;CHECK-LABEL: v_eori64:
;CHECK: veor
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -189,7 +189,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A
}
define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_eorQi8:
+;CHECK-LABEL: v_eorQi8:
;CHECK: veor
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -198,7 +198,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A
}
define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_eorQi16:
+;CHECK-LABEL: v_eorQi16:
;CHECK: veor
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -207,7 +207,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %
}
define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_eorQi32:
+;CHECK-LABEL: v_eorQi32:
;CHECK: veor
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -216,7 +216,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %
}
define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_eorQi64:
+;CHECK-LABEL: v_eorQi64:
;CHECK: veor
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -225,7 +225,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %
}
define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
-;CHECK: v_mvni8:
+;CHECK-LABEL: v_mvni8:
;CHECK: vmvn
%tmp1 = load <8 x i8>* %A
%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -233,7 +233,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) n
}
define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
-;CHECK: v_mvni16:
+;CHECK-LABEL: v_mvni16:
;CHECK: vmvn
%tmp1 = load <4 x i16>* %A
%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -241,7 +241,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A
}
define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
-;CHECK: v_mvni32:
+;CHECK-LABEL: v_mvni32:
;CHECK: vmvn
%tmp1 = load <2 x i32>* %A
%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
@@ -249,7 +249,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A
}
define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
-;CHECK: v_mvni64:
+;CHECK-LABEL: v_mvni64:
;CHECK: vmvn
%tmp1 = load <1 x i64>* %A
%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
@@ -257,7 +257,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A
}
define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
-;CHECK: v_mvnQi8:
+;CHECK-LABEL: v_mvnQi8:
;CHECK: vmvn
%tmp1 = load <16 x i8>* %A
%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -265,7 +265,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A
}
define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
-;CHECK: v_mvnQi16:
+;CHECK-LABEL: v_mvnQi16:
;CHECK: vmvn
%tmp1 = load <8 x i16>* %A
%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -273,7 +273,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %
}
define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
-;CHECK: v_mvnQi32:
+;CHECK-LABEL: v_mvnQi32:
;CHECK: vmvn
%tmp1 = load <4 x i32>* %A
%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
@@ -281,7 +281,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %
}
define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
-;CHECK: v_mvnQi64:
+;CHECK-LABEL: v_mvnQi64:
;CHECK: vmvn
%tmp1 = load <2 x i64>* %A
%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
@@ -289,7 +289,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %
}
define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orri8:
+;CHECK-LABEL: v_orri8:
;CHECK: vorr
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -298,7 +298,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <
}
define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orri16:
+;CHECK-LABEL: v_orri16:
;CHECK: vorr
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -307,7 +307,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A
}
define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orri32:
+;CHECK-LABEL: v_orri32:
;CHECK: vorr
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -316,7 +316,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A
}
define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orri64:
+;CHECK-LABEL: v_orri64:
;CHECK: vorr
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -325,7 +325,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A
}
define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_orrQi8:
+;CHECK-LABEL: v_orrQi8:
;CHECK: vorr
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -334,7 +334,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A
}
define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_orrQi16:
+;CHECK-LABEL: v_orrQi16:
;CHECK: vorr
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -343,7 +343,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %
}
define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_orrQi32:
+;CHECK-LABEL: v_orrQi32:
;CHECK: vorr
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -352,7 +352,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %
}
define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_orrQi64:
+;CHECK-LABEL: v_orrQi64:
;CHECK: vorr
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -361,7 +361,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %
}
define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orni8:
+;CHECK-LABEL: v_orni8:
;CHECK: vorn
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <
}
define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orni16:
+;CHECK-LABEL: v_orni16:
;CHECK: vorn
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -381,7 +381,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A
}
define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orni32:
+;CHECK-LABEL: v_orni32:
;CHECK: vorn
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -391,7 +391,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A
}
define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orni64:
+;CHECK-LABEL: v_orni64:
;CHECK: vorn
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -401,7 +401,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A
}
define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_ornQi8:
+;CHECK-LABEL: v_ornQi8:
;CHECK: vorn
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -411,7 +411,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A
}
define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_ornQi16:
+;CHECK-LABEL: v_ornQi16:
;CHECK: vorn
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -421,7 +421,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %
}
define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_ornQi32:
+;CHECK-LABEL: v_ornQi32:
;CHECK: vorn
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -431,7 +431,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %
}
define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_ornQi64:
+;CHECK-LABEL: v_ornQi64:
;CHECK: vorn
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %
}
define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtsti8:
+;CHECK-LABEL: vtsti8:
;CHECK: vtst.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -452,7 +452,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8
}
define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtsti16:
+;CHECK-LABEL: vtsti16:
;CHECK: vtst.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -463,7 +463,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A,
}
define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtsti32:
+;CHECK-LABEL: vtsti32:
;CHECK: vtst.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -474,7 +474,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A,
}
define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtstQi8:
+;CHECK-LABEL: vtstQi8:
;CHECK: vtst.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -485,7 +485,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A,
}
define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtstQi16:
+;CHECK-LABEL: vtstQi16:
;CHECK: vtst.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -496,7 +496,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A
}
define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtstQi32:
+;CHECK-LABEL: vtstQi32:
;CHECK: vtst.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -507,7 +507,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A
}
define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
-; CHECK: v_orrimm:
+; CHECK-LABEL: v_orrimm:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vorr
@@ -527,7 +527,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %
}
define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
-; CHECK: v_bicimm:
+; CHECK-LABEL: v_bicimm:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vbic
@@ -537,7 +537,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A)
}
define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
-; CHECK: v_bicimmQ:
+; CHECK-LABEL: v_bicimmQ:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vbic
Modified: llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
@@ -15,7 +15,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <
}
define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A
}
define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
@@ -43,7 +43,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A
}
define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
;CHECK: vldr
;CHECK: vldr
;CHECK: vldr
@@ -58,7 +58,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A
}
define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
@@ -72,7 +72,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A
}
define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
@@ -86,7 +86,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %
}
define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
@@ -100,7 +100,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %
}
define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vld1.64
Modified: llvm/trunk/test/CodeGen/ARM/vbsl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbsl.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vbsl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vbsl.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; rdar://12471808
define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
;CHECK: vbsl
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -16,7 +16,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <
}
define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
;CHECK: vbsl
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A
}
define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
;CHECK: vbsl
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A
}
define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
;CHECK: vbsl
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A
}
define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
;CHECK: vbsl
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A
}
define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
;CHECK: vbsl
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -81,7 +81,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %
}
define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
;CHECK: vbsl
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -94,7 +94,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %
}
define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
;CHECK: vbsl
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -107,56 +107,56 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %
}
define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: vbsl
%vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
ret <8 x i8> %vbsl.i
}
define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: vbsl
%vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
ret <4 x i16> %vbsl3.i
}
define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: vbsl
%vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
ret <2 x i32> %vbsl3.i
}
define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: vbsl
%vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
ret <2 x float> %vbsl4.i
}
define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: g1:
+; CHECK-LABEL: g1:
; CHECK: vbsl
%vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
ret <16 x i8> %vbsl.i
}
define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: g2:
+; CHECK-LABEL: g2:
; CHECK: vbsl
%vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
ret <8 x i16> %vbsl3.i
}
define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: g3:
+; CHECK-LABEL: g3:
; CHECK: vbsl
%vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
ret <4 x i32> %vbsl3.i
}
define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
-; CHECK: g4:
+; CHECK-LABEL: g4:
; CHECK: vbsl
%vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
ret <4 x float> %vbsl4.i
Modified: llvm/trunk/test/CodeGen/ARM/vceq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vceq.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vceq.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vceq.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vceqi8:
+;CHECK-LABEL: vceqi8:
;CHECK: vceq.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8
}
define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vceqi16:
+;CHECK-LABEL: vceqi16:
;CHECK: vceq.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vceqi16(<4 x i16>* %A,
}
define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vceqi32:
+;CHECK-LABEL: vceqi32:
;CHECK: vceq.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vceqi32(<2 x i32>* %A,
}
define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vceqf32:
+;CHECK-LABEL: vceqf32:
;CHECK: vceq.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -41,7 +41,7 @@ define <2 x i32> @vceqf32(<2 x float>* %
}
define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vceqQi8:
+;CHECK-LABEL: vceqQi8:
;CHECK: vceq.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A,
}
define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vceqQi16:
+;CHECK-LABEL: vceqQi16:
;CHECK: vceq.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A
}
define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vceqQi32:
+;CHECK-LABEL: vceqQi32:
;CHECK: vceq.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A
}
define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vceqQf32:
+;CHECK-LABEL: vceqQf32:
;CHECK: vceq.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -81,7 +81,7 @@ define <4 x i32> @vceqQf32(<4 x float>*
}
define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
-;CHECK: vceqi8Z:
+;CHECK-LABEL: vceqi8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vceq.i8
Modified: llvm/trunk/test/CodeGen/ARM/vcge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcge.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcge.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcges8:
+;CHECK-LABEL: vcges8:
;CHECK: vcge.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8
}
define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcges16:
+;CHECK-LABEL: vcges16:
;CHECK: vcge.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vcges16(<4 x i16>* %A,
}
define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcges32:
+;CHECK-LABEL: vcges32:
;CHECK: vcge.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vcges32(<2 x i32>* %A,
}
define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgeu8:
+;CHECK-LABEL: vcgeu8:
;CHECK: vcge.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -41,7 +41,7 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8
}
define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgeu16:
+;CHECK-LABEL: vcgeu16:
;CHECK: vcge.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -51,7 +51,7 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A,
}
define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgeu32:
+;CHECK-LABEL: vcgeu32:
;CHECK: vcge.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -61,7 +61,7 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A,
}
define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgef32:
+;CHECK-LABEL: vcgef32:
;CHECK: vcge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -71,7 +71,7 @@ define <2 x i32> @vcgef32(<2 x float>* %
}
define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQs8:
+;CHECK-LABEL: vcgeQs8:
;CHECK: vcge.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -81,7 +81,7 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A,
}
define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQs16:
+;CHECK-LABEL: vcgeQs16:
;CHECK: vcge.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A
}
define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQs32:
+;CHECK-LABEL: vcgeQs32:
;CHECK: vcge.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -101,7 +101,7 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A
}
define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQu8:
+;CHECK-LABEL: vcgeQu8:
;CHECK: vcge.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A,
}
define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQu16:
+;CHECK-LABEL: vcgeQu16:
;CHECK: vcge.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -121,7 +121,7 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A
}
define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQu32:
+;CHECK-LABEL: vcgeQu32:
;CHECK: vcge.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -131,7 +131,7 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A
}
define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgeQf32:
+;CHECK-LABEL: vcgeQf32:
;CHECK: vcge.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -141,7 +141,7 @@ define <4 x i32> @vcgeQf32(<4 x float>*
}
define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgef32:
+;CHECK-LABEL: vacgef32:
;CHECK: vacge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -150,7 +150,7 @@ define <2 x i32> @vacgef32(<2 x float>*
}
define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgeQf32:
+;CHECK-LABEL: vacgeQf32:
;CHECK: vacge.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -162,7 +162,7 @@ declare <2 x i32> @llvm.arm.neon.vacged(
declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgei8Z:
+;CHECK-LABEL: vcgei8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcge.s8
@@ -173,7 +173,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) n
}
define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclei8Z:
+;CHECK-LABEL: vclei8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcle.s8
Modified: llvm/trunk/test/CodeGen/ARM/vcgt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcgt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcgt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcgt.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgts8:
+;CHECK-LABEL: vcgts8:
;CHECK: vcgt.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8
}
define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgts16:
+;CHECK-LABEL: vcgts16:
;CHECK: vcgt.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vcgts16(<4 x i16>* %A,
}
define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgts32:
+;CHECK-LABEL: vcgts32:
;CHECK: vcgt.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vcgts32(<2 x i32>* %A,
}
define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgtu8:
+;CHECK-LABEL: vcgtu8:
;CHECK: vcgt.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -42,7 +42,7 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8
}
define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgtu16:
+;CHECK-LABEL: vcgtu16:
;CHECK: vcgt.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -52,7 +52,7 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A,
}
define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgtu32:
+;CHECK-LABEL: vcgtu32:
;CHECK: vcgt.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -62,7 +62,7 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A,
}
define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgtf32:
+;CHECK-LABEL: vcgtf32:
;CHECK: vcgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -72,7 +72,7 @@ define <2 x i32> @vcgtf32(<2 x float>* %
}
define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQs8:
+;CHECK-LABEL: vcgtQs8:
;CHECK: vcgt.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A,
}
define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQs16:
+;CHECK-LABEL: vcgtQs16:
;CHECK: vcgt.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -92,7 +92,7 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A
}
define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQs32:
+;CHECK-LABEL: vcgtQs32:
;CHECK: vcgt.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -102,7 +102,7 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A
}
define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQu8:
+;CHECK-LABEL: vcgtQu8:
;CHECK: vcgt.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -112,7 +112,7 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A,
}
define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQu16:
+;CHECK-LABEL: vcgtQu16:
;CHECK: vcgt.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A
}
define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQu32:
+;CHECK-LABEL: vcgtQu32:
;CHECK: vcgt.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -132,7 +132,7 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A
}
define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgtQf32:
+;CHECK-LABEL: vcgtQf32:
;CHECK: vcgt.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -142,7 +142,7 @@ define <4 x i32> @vcgtQf32(<4 x float>*
}
define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgtf32:
+;CHECK-LABEL: vacgtf32:
;CHECK: vacgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -151,7 +151,7 @@ define <2 x i32> @vacgtf32(<2 x float>*
}
define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgtQf32:
+;CHECK-LABEL: vacgtQf32:
;CHECK: vacgt.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -161,7 +161,7 @@ define <4 x i32> @vacgtQf32(<4 x float>*
; rdar://7923010
define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgt_zext:
+;CHECK-LABEL: vcgt_zext:
;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
@@ -176,7 +176,7 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(
declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgti8Z:
+;CHECK-LABEL: vcgti8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcgt.s8
@@ -187,7 +187,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) n
}
define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclti8Z:
+;CHECK-LABEL: vclti8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vclt.s8
Modified: llvm/trunk/test/CodeGen/ARM/vcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcnt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcnt.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; NB: this tests vcnt, vclz, and vcls
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nou
}
define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -21,7 +21,7 @@ declare <8 x i8> @llvm.ctpop.v8i8(<8 x
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -29,7 +29,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nou
}
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -37,7 +37,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A)
}
define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -45,7 +45,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A)
}
define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -53,7 +53,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A)
}
define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -61,7 +61,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A)
}
define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -77,7 +77,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
;CHECK: vcls.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -85,7 +85,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) no
}
define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
;CHECK: vcls.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -93,7 +93,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A)
}
define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
;CHECK: vcls.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -101,7 +101,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A)
}
define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
;CHECK: vcls.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -109,7 +109,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A)
}
define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
;CHECK: vcls.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -117,7 +117,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A
}
define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
;CHECK: vcls.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
Modified: llvm/trunk/test/CodeGen/ARM/vcvt-cost.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt-cost.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcvt-cost.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcvt-cost.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
%T0_5 = type <8 x i8>
%T1_5 = type <8 x i32>
-; CHECK: func_cvt5:
+; CHECK-LABEL: func_cvt5:
define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
; CHECK: vmovl.s8
; CHECK: vmovl.s16
@@ -20,7 +20,7 @@ define void @func_cvt5(%T0_5* %loadaddr,
;; is improved the cost needs to change.
%TA0_5 = type <8 x i8>
%TA1_5 = type <8 x i32>
-; CHECK: func_cvt1:
+; CHECK-LABEL: func_cvt1:
define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
; CHECK: vmovl.u8
; CHECK: vmovl.u16
@@ -35,7 +35,7 @@ define void @func_cvt1(%TA0_5* %loadaddr
%T0_51 = type <8 x i32>
%T1_51 = type <8 x i8>
-; CHECK: func_cvt51:
+; CHECK-LABEL: func_cvt51:
define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
@@ -50,7 +50,7 @@ define void @func_cvt51(%T0_51* %loadadd
%TT0_5 = type <16 x i8>
%TT1_5 = type <16 x i32>
-; CHECK: func_cvt52:
+; CHECK-LABEL: func_cvt52:
define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
; CHECK: vmovl.s16
; CHECK: vmovl.s16
@@ -67,7 +67,7 @@ define void @func_cvt52(%TT0_5* %loadadd
;; is improved the cost needs to change.
%TTA0_5 = type <16 x i8>
%TTA1_5 = type <16 x i32>
-; CHECK: func_cvt12:
+; CHECK-LABEL: func_cvt12:
define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
; CHECK: vmovl.u16
; CHECK: vmovl.u16
@@ -83,7 +83,7 @@ define void @func_cvt12(%TTA0_5* %loadad
%TT0_51 = type <16 x i32>
%TT1_51 = type <16 x i8>
-; CHECK: func_cvt512:
+; CHECK-LABEL: func_cvt512:
define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
@@ -99,7 +99,7 @@ define void @func_cvt512(%TT0_51* %loada
ret void
}
-; CHECK: sext_v4i16_v4i64:
+; CHECK-LABEL: sext_v4i16_v4i64:
define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
@@ -111,7 +111,7 @@ define void @sext_v4i16_v4i64(<4 x i16>*
ret void
}
-; CHECK: zext_v4i16_v4i64:
+; CHECK-LABEL: zext_v4i16_v4i64:
define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
@@ -123,7 +123,7 @@ define void @zext_v4i16_v4i64(<4 x i16>*
ret void
}
-; CHECK: sext_v8i16_v8i64:
+; CHECK-LABEL: sext_v8i16_v8i64:
define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
@@ -137,7 +137,7 @@ define void @sext_v8i16_v8i64(<8 x i16>*
ret void
}
-; CHECK: zext_v8i16_v8i64:
+; CHECK-LABEL: zext_v8i16_v8i64:
define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
Modified: llvm/trunk/test/CodeGen/ARM/vcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcvt.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tos32:
+;CHECK-LABEL: vcvt_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
@@ -9,7 +9,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x flo
}
define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tou32:
+;CHECK-LABEL: vcvt_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
@@ -17,7 +17,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x flo
}
define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_s32tof32:
+;CHECK-LABEL: vcvt_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
@@ -25,7 +25,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i
}
define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_u32tof32:
+;CHECK-LABEL: vcvt_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
@@ -33,7 +33,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i
}
define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tos32:
+;CHECK-LABEL: vcvtQ_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
@@ -41,7 +41,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x fl
}
define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tou32:
+;CHECK-LABEL: vcvtQ_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
@@ -49,7 +49,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x fl
}
define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_s32tof32:
+;CHECK-LABEL: vcvtQ_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
@@ -57,7 +57,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x
}
define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_u32tof32:
+;CHECK-LABEL: vcvtQ_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
@@ -65,7 +65,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x
}
define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tos32:
+;CHECK-LABEL: vcvt_n_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -73,7 +73,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x f
}
define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tou32:
+;CHECK-LABEL: vcvt_n_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -81,7 +81,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x f
}
define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_s32tof32:
+;CHECK-LABEL: vcvt_n_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -89,7 +89,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x
}
define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_u32tof32:
+;CHECK-LABEL: vcvt_n_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -102,7 +102,7 @@ declare <2 x float> @llvm.arm.neon.vcvtf
declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tos32:
+;CHECK-LABEL: vcvtQ_n_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -110,7 +110,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x
}
define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tou32:
+;CHECK-LABEL: vcvtQ_n_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -118,7 +118,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x
}
define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_s32tof32:
+;CHECK-LABEL: vcvtQ_n_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -126,7 +126,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4
}
define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_u32tof32:
+;CHECK-LABEL: vcvtQ_n_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -139,7 +139,7 @@ declare <4 x float> @llvm.arm.neon.vcvtf
declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
-;CHECK: vcvt_f16tof32:
+;CHECK-LABEL: vcvt_f16tof32:
;CHECK: vcvt.f32.f16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
@@ -147,7 +147,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i
}
define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
-;CHECK: vcvt_f32tof16:
+;CHECK-LABEL: vcvt_f32tof16:
;CHECK: vcvt.f16.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
@@ -159,7 +159,7 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2
define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
-; CHECK: fix_float_to_i16:
+; CHECK-LABEL: fix_float_to_i16:
; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1
; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]]
@@ -169,7 +169,7 @@ define <4 x i16> @fix_float_to_i16(<4 x
}
define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
-; CHECK: fix_float_to_i64:
+; CHECK-LABEL: fix_float_to_i64:
; CHECK: bl
; CHECK: bl
@@ -179,7 +179,7 @@ define <2 x i64> @fix_float_to_i64(<2 x
}
define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
-; CHECK: fix_double_to_i16:
+; CHECK-LABEL: fix_double_to_i16:
; CHECK: vcvt.s32.f64
; CHECK: vcvt.s32.f64
@@ -189,7 +189,7 @@ define <4 x i16> @fix_double_to_i16(<4 x
}
define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
-; CHECK: fix_double_to_i64:
+; CHECK-LABEL: fix_double_to_i64:
; CHECK: bl
; CHECK: bl
%scale = fmul <2 x double> %in, <double 2.0, double 2.0>
Modified: llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll Sun Jul 14 01:24:09 2013
@@ -97,7 +97,7 @@ entry:
declare void @foo_float32x4_t(<4 x float>)
define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_unsigned_i16_to_float:
+; CHECK-LABEL: fix_unsigned_i16_to_float:
; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
@@ -107,7 +107,7 @@ define <4 x float> @fix_unsigned_i16_to_
}
define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_signed_i16_to_float:
+; CHECK-LABEL: fix_signed_i16_to_float:
; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
@@ -117,7 +117,7 @@ define <4 x float> @fix_signed_i16_to_fl
}
define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
-; CHECK: fix_i64_to_float:
+; CHECK-LABEL: fix_i64_to_float:
; CHECK: bl
; CHECK: bl
@@ -127,7 +127,7 @@ define <2 x float> @fix_i64_to_float(<2
}
define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
-; CHECK: fix_i64_to_double:
+; CHECK-LABEL: fix_i64_to_double:
; CHECK: bl
; CHECK: bl
Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vdup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vdup.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK: v_dup8:
+;CHECK-LABEL: v_dup8:
;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
@@ -15,7 +15,7 @@ define <8 x i8> @v_dup8(i8 %A) nounwind
}
define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK: v_dup16:
+;CHECK-LABEL: v_dup16:
;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
@@ -25,7 +25,7 @@ define <4 x i16> @v_dup16(i16 %A) nounwi
}
define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK: v_dup32:
+;CHECK-LABEL: v_dup32:
;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
@@ -33,7 +33,7 @@ define <2 x i32> @v_dup32(i32 %A) nounwi
}
define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK: v_dupfloat:
+;CHECK-LABEL: v_dupfloat:
;CHECK: vdup.32
%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
@@ -41,7 +41,7 @@ define <2 x float> @v_dupfloat(float %A)
}
define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK: v_dupQ8:
+;CHECK-LABEL: v_dupQ8:
;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
@@ -63,7 +63,7 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwin
}
define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK: v_dupQ16:
+;CHECK-LABEL: v_dupQ16:
;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
@@ -77,7 +77,7 @@ define <8 x i16> @v_dupQ16(i16 %A) nounw
}
define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK: v_dupQ32:
+;CHECK-LABEL: v_dupQ32:
;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
@@ -87,7 +87,7 @@ define <4 x i32> @v_dupQ32(i32 %A) nounw
}
define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK: v_dupQfloat:
+;CHECK-LABEL: v_dupQfloat:
;CHECK: vdup.32
%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
@@ -99,7 +99,7 @@ define <4 x float> @v_dupQfloat(float %A
; Check to make sure it works with shuffles, too.
define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK: v_shuffledup8:
+;CHECK-LABEL: v_shuffledup8:
;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -107,7 +107,7 @@ define <8 x i8> @v_shuffledup8(i8 %A) no
}
define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK: v_shuffledup16:
+;CHECK-LABEL: v_shuffledup16:
;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -115,7 +115,7 @@ define <4 x i16> @v_shuffledup16(i16 %A)
}
define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK: v_shuffledup32:
+;CHECK-LABEL: v_shuffledup32:
;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -123,7 +123,7 @@ define <2 x i32> @v_shuffledup32(i32 %A)
}
define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK: v_shuffledupfloat:
+;CHECK-LABEL: v_shuffledupfloat:
;CHECK: vdup.32
%tmp1 = insertelement <2 x float> undef, float %A, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -131,7 +131,7 @@ define <2 x float> @v_shuffledupfloat(fl
}
define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK: v_shuffledupQ8:
+;CHECK-LABEL: v_shuffledupQ8:
;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -139,7 +139,7 @@ define <16 x i8> @v_shuffledupQ8(i8 %A)
}
define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK: v_shuffledupQ16:
+;CHECK-LABEL: v_shuffledupQ16:
;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -147,7 +147,7 @@ define <8 x i16> @v_shuffledupQ16(i16 %A
}
define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK: v_shuffledupQ32:
+;CHECK-LABEL: v_shuffledupQ32:
;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -155,7 +155,7 @@ define <4 x i32> @v_shuffledupQ32(i32 %A
}
define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK: v_shuffledupQfloat:
+;CHECK-LABEL: v_shuffledupQfloat:
;CHECK: vdup.32
%tmp1 = insertelement <4 x float> undef, float %A, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
@@ -163,7 +163,7 @@ define <4 x float> @v_shuffledupQfloat(f
}
define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK: vduplane8:
+;CHECK-LABEL: vduplane8:
;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -171,7 +171,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A)
}
define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK: vduplane16:
+;CHECK-LABEL: vduplane16:
;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -179,7 +179,7 @@ define <4 x i16> @vduplane16(<4 x i16>*
}
define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK: vduplane32:
+;CHECK-LABEL: vduplane32:
;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
@@ -187,7 +187,7 @@ define <2 x i32> @vduplane32(<2 x i32>*
}
define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK: vduplanefloat:
+;CHECK-LABEL: vduplanefloat:
;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
@@ -195,7 +195,7 @@ define <2 x float> @vduplanefloat(<2 x f
}
define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK: vduplaneQ8:
+;CHECK-LABEL: vduplaneQ8:
;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -203,7 +203,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %
}
define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK: vduplaneQ16:
+;CHECK-LABEL: vduplaneQ16:
;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -211,7 +211,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>*
}
define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK: vduplaneQ32:
+;CHECK-LABEL: vduplaneQ32:
;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -219,7 +219,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>*
}
define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK: vduplaneQfloat:
+;CHECK-LABEL: vduplaneQfloat:
;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -251,7 +251,7 @@ entry:
}
; Radar 7373643
-;CHECK: redundantVdup:
+;CHECK-LABEL: redundantVdup:
;CHECK: vmov.i8
;CHECK-NOT: vdup.8
;CHECK: vstr
@@ -297,7 +297,7 @@ define <4 x i32> @tduplane(<4 x i32> %in
}
define <2 x float> @check_f32(<4 x float> %v) nounwind {
-;CHECK: check_f32:
+;CHECK-LABEL: check_f32:
;CHECK: vdup.32 {{.*}}, d{{..}}[1]
%x = extractelement <4 x float> %v, i32 3
%1 = insertelement <2 x float> undef, float %x, i32 0
@@ -306,7 +306,7 @@ define <2 x float> @check_f32(<4 x float
}
define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
-;CHECK: check_i32:
+;CHECK-LABEL: check_i32:
;CHECK: vdup.32 {{.*}}, d{{..}}[1]
%x = extractelement <4 x i32> %v, i32 3
%1 = insertelement <2 x i32> undef, i32 %x, i32 0
@@ -315,7 +315,7 @@ define <2 x i32> @check_i32(<4 x i32> %v
}
define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
-;CHECK: check_i16:
+;CHECK-LABEL: check_i16:
;CHECK: vdup.16 {{.*}}, d{{..}}[3]
%x = extractelement <8 x i16> %v, i32 3
%1 = insertelement <4 x i16> undef, i16 %x, i32 0
@@ -324,7 +324,7 @@ define <4 x i16> @check_i16(<8 x i16> %v
}
define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
-;CHECK: check_i8:
+;CHECK-LABEL: check_i8:
;CHECK: vdup.8 {{.*}}, d{{..}}[3]
%x = extractelement <16 x i8> %v, i32 3
%1 = insertelement <8 x i8> undef, i8 %x, i32 0
Modified: llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-; CHECK: f:
+; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) {
; CHECK: vldr
; CHECK: vmovl.u16
@@ -18,7 +18,7 @@ define float @f(<4 x i16>* nocapture %in
ret float %7
}
-; CHECK: g:
+; CHECK-LABEL: g:
define float @g(<4 x i8>* nocapture %in) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
@@ -39,7 +39,7 @@ define float @g(<4 x i8>* nocapture %in)
ret float %7
}
-; CHECK: h:
+; CHECK-LABEL: h:
define <4 x i8> @h(<4 x float> %v) {
; CHECK: vcvt.{{[us]}}32.f32
; CHECK: vmovn.i32
@@ -47,7 +47,7 @@ define <4 x i8> @h(<4 x float> %v) {
ret <4 x i8> %1
}
-; CHECK: i:
+; CHECK-LABEL: i:
define <4 x i8> @i(<4 x i8>* %x) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
@@ -62,7 +62,7 @@ define <4 x i8> @i(<4 x i8>* %x) {
%2 = sdiv <4 x i8> zeroinitializer, %1
ret <4 x i8> %2
}
-; CHECK: j:
+; CHECK-LABEL: j:
define <4 x i32> @j(<4 x i8>* %in) nounwind {
; CHECK: vld1
; CHECK: vmovl.u8
Modified: llvm/trunk/test/CodeGen/ARM/vfcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vfcmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vfcmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vfcmp.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; une is implemented with VCEQ/VMVN
define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunef32:
+;CHECK-LABEL: vcunef32:
;CHECK: vceq.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
@@ -16,7 +16,7 @@ define <2 x i32> @vcunef32(<2 x float>*
; olt is implemented with VCGT
define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcoltf32:
+;CHECK-LABEL: vcoltf32:
;CHECK: vcgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -27,7 +27,7 @@ define <2 x i32> @vcoltf32(<2 x float>*
; ole is implemented with VCGE
define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcolef32:
+;CHECK-LABEL: vcolef32:
;CHECK: vcge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define <2 x i32> @vcolef32(<2 x float>*
; uge is implemented with VCGT/VMVN
define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugef32:
+;CHECK-LABEL: vcugef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
@@ -50,7 +50,7 @@ define <2 x i32> @vcugef32(<2 x float>*
; ule is implemented with VCGT/VMVN
define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vculef32:
+;CHECK-LABEL: vculef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
@@ -62,7 +62,7 @@ define <2 x i32> @vculef32(<2 x float>*
; ugt is implemented with VCGE/VMVN
define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugtf32:
+;CHECK-LABEL: vcugtf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
@@ -74,7 +74,7 @@ define <2 x i32> @vcugtf32(<2 x float>*
; ult is implemented with VCGE/VMVN
define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcultf32:
+;CHECK-LABEL: vcultf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
@@ -86,7 +86,7 @@ define <2 x i32> @vcultf32(<2 x float>*
; ueq is implemented with VCGT/VCGT/VORR/VMVN
define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcueqf32:
+;CHECK-LABEL: vcueqf32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
@@ -100,7 +100,7 @@ define <2 x i32> @vcueqf32(<2 x float>*
; one is implemented with VCGT/VCGT/VORR
define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vconef32:
+;CHECK-LABEL: vconef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
@@ -113,7 +113,7 @@ define <2 x i32> @vconef32(<2 x float>*
; uno is implemented with VCGT/VCGE/VORR/VMVN
define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunof32:
+;CHECK-LABEL: vcunof32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
@@ -127,7 +127,7 @@ define <2 x i32> @vcunof32(<2 x float>*
; ord is implemented with VCGT/VCGE/VORR
define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcordf32:
+;CHECK-LABEL: vcordf32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:3
target triple = "thumbv7-elf"
define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
-;CHECK: vget_lanes8:
+;CHECK-LABEL: vget_lanes8:
;CHECK: vmov.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -12,7 +12,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) no
}
define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
-;CHECK: vget_lanes16:
+;CHECK-LABEL: vget_lanes16:
;CHECK: vmov.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -21,7 +21,7 @@ define i32 @vget_lanes16(<4 x i16>* %A)
}
define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
-;CHECK: vget_laneu8:
+;CHECK-LABEL: vget_laneu8:
;CHECK: vmov.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -30,7 +30,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) no
}
define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
-;CHECK: vget_laneu16:
+;CHECK-LABEL: vget_laneu16:
;CHECK: vmov.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -40,7 +40,7 @@ define i32 @vget_laneu16(<4 x i16>* %A)
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
-;CHECK: vget_lanei32:
+;CHECK-LABEL: vget_lanei32:
;CHECK: vmov.32
%tmp1 = load <2 x i32>* %A
%tmp2 = add <2 x i32> %tmp1, %tmp1
@@ -49,7 +49,7 @@ define i32 @vget_lanei32(<2 x i32>* %A)
}
define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_lanes8:
+;CHECK-LABEL: vgetQ_lanes8:
;CHECK: vmov.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -58,7 +58,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A)
}
define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_lanes16:
+;CHECK-LABEL: vgetQ_lanes16:
;CHECK: vmov.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -67,7 +67,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A)
}
define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_laneu8:
+;CHECK-LABEL: vgetQ_laneu8:
;CHECK: vmov.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -76,7 +76,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A)
}
define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_laneu16:
+;CHECK-LABEL: vgetQ_laneu16:
;CHECK: vmov.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -86,7 +86,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A)
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
-;CHECK: vgetQ_lanei32:
+;CHECK-LABEL: vgetQ_lanei32:
;CHECK: vmov.32
%tmp1 = load <4 x i32>* %A
%tmp2 = add <4 x i32> %tmp1, %tmp1
@@ -159,7 +159,7 @@ return:
}
define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
-;CHECK: vset_lane8:
+;CHECK-LABEL: vset_lane8:
;CHECK: vmov.8
%tmp1 = load <8 x i8>* %A
%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
@@ -167,7 +167,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A
}
define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
-;CHECK: vset_lane16:
+;CHECK-LABEL: vset_lane16:
;CHECK: vmov.16
%tmp1 = load <4 x i16>* %A
%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
@@ -175,7 +175,7 @@ define <4 x i16> @vset_lane16(<4 x i16>*
}
define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
-;CHECK: vset_lane32:
+;CHECK-LABEL: vset_lane32:
;CHECK: vmov.32
%tmp1 = load <2 x i32>* %A
%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
@@ -183,7 +183,7 @@ define <2 x i32> @vset_lane32(<2 x i32>*
}
define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
-;CHECK: vsetQ_lane8:
+;CHECK-LABEL: vsetQ_lane8:
;CHECK: vmov.8
%tmp1 = load <16 x i8>* %A
%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
@@ -191,7 +191,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>*
}
define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
-;CHECK: vsetQ_lane16:
+;CHECK-LABEL: vsetQ_lane16:
;CHECK: vmov.16
%tmp1 = load <8 x i16>* %A
%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
@@ -199,7 +199,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>
}
define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
-;CHECK: vsetQ_lane32:
+;CHECK-LABEL: vsetQ_lane32:
;CHECK: vmov.32 d{{.*}}[1], r1
%tmp1 = load <4 x i32>* %A
%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
Modified: llvm/trunk/test/CodeGen/ARM/vhadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vhadd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vhadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vhadd.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhadds8:
+;CHECK-LABEL: vhadds8:
;CHECK: vhadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <
}
define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhadds16:
+;CHECK-LABEL: vhadds16:
;CHECK: vhadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhadds16(<4 x i16>* %A
}
define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhadds32:
+;CHECK-LABEL: vhadds32:
;CHECK: vhadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhadds32(<2 x i32>* %A
}
define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhaddu8:
+;CHECK-LABEL: vhaddu8:
;CHECK: vhadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <
}
define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhaddu16:
+;CHECK-LABEL: vhaddu16:
;CHECK: vhadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A
}
define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhaddu32:
+;CHECK-LABEL: vhaddu32:
;CHECK: vhadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A
}
define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQs8:
+;CHECK-LABEL: vhaddQs8:
;CHECK: vhadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A
}
define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQs16:
+;CHECK-LABEL: vhaddQs16:
;CHECK: vhadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %
}
define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQs32:
+;CHECK-LABEL: vhaddQs32:
;CHECK: vhadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %
}
define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQu8:
+;CHECK-LABEL: vhaddQu8:
;CHECK: vhadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A
}
define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQu16:
+;CHECK-LABEL: vhaddQu16:
;CHECK: vhadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %
}
define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQu32:
+;CHECK-LABEL: vhaddQu32:
;CHECK: vhadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -125,7 +125,7 @@ declare <8 x i16> @llvm.arm.neon.vhaddu.
declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhadds8:
+;CHECK-LABEL: vrhadds8:
;CHECK: vrhadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -134,7 +134,7 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A,
}
define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhadds16:
+;CHECK-LABEL: vrhadds16:
;CHECK: vrhadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -143,7 +143,7 @@ define <4 x i16> @vrhadds16(<4 x i16>* %
}
define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhadds32:
+;CHECK-LABEL: vrhadds32:
;CHECK: vrhadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -152,7 +152,7 @@ define <2 x i32> @vrhadds32(<2 x i32>* %
}
define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhaddu8:
+;CHECK-LABEL: vrhaddu8:
;CHECK: vrhadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A,
}
define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhaddu16:
+;CHECK-LABEL: vrhaddu16:
;CHECK: vrhadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -170,7 +170,7 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %
}
define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhaddu32:
+;CHECK-LABEL: vrhaddu32:
;CHECK: vrhadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -179,7 +179,7 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %
}
define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQs8:
+;CHECK-LABEL: vrhaddQs8:
;CHECK: vrhadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -188,7 +188,7 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %
}
define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQs16:
+;CHECK-LABEL: vrhaddQs16:
;CHECK: vrhadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vrhaddQs16(<8 x i16>*
}
define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQs32:
+;CHECK-LABEL: vrhaddQs32:
;CHECK: vrhadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -206,7 +206,7 @@ define <4 x i32> @vrhaddQs32(<4 x i32>*
}
define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQu8:
+;CHECK-LABEL: vrhaddQu8:
;CHECK: vrhadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -215,7 +215,7 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %
}
define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQu16:
+;CHECK-LABEL: vrhaddQu16:
;CHECK: vrhadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -224,7 +224,7 @@ define <8 x i16> @vrhaddQu16(<8 x i16>*
}
define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQu32:
+;CHECK-LABEL: vrhaddQu32:
;CHECK: vrhadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vhsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vhsub.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vhsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vhsub.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubs8:
+;CHECK-LABEL: vhsubs8:
;CHECK: vhsub.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <
}
define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubs16:
+;CHECK-LABEL: vhsubs16:
;CHECK: vhsub.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A
}
define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubs32:
+;CHECK-LABEL: vhsubs32:
;CHECK: vhsub.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A
}
define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubu8:
+;CHECK-LABEL: vhsubu8:
;CHECK: vhsub.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <
}
define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubu16:
+;CHECK-LABEL: vhsubu16:
;CHECK: vhsub.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A
}
define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubu32:
+;CHECK-LABEL: vhsubu32:
;CHECK: vhsub.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A
}
define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQs8:
+;CHECK-LABEL: vhsubQs8:
;CHECK: vhsub.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A
}
define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQs16:
+;CHECK-LABEL: vhsubQs16:
;CHECK: vhsub.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %
}
define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQs32:
+;CHECK-LABEL: vhsubQs32:
;CHECK: vhsub.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %
}
define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQu8:
+;CHECK-LABEL: vhsubQu8:
;CHECK: vhsub.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A
}
define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQu16:
+;CHECK-LABEL: vhsubQu16:
;CHECK: vhsub.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %
}
define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQu32:
+;CHECK-LABEL: vhsubQu32:
;CHECK: vhsub.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vicmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vicmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vicmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vicmp.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
; the other operations.
define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcnei8:
+;CHECK-LABEL: vcnei8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
%tmp1 = load <8 x i8>* %A
@@ -18,7 +18,7 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8
}
define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcnei16:
+;CHECK-LABEL: vcnei16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
%tmp1 = load <4 x i16>* %A
@@ -29,7 +29,7 @@ define <4 x i16> @vcnei16(<4 x i16>* %A,
}
define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcnei32:
+;CHECK-LABEL: vcnei32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x i32>* %A
@@ -40,7 +40,7 @@ define <2 x i32> @vcnei32(<2 x i32>* %A,
}
define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcneQi8:
+;CHECK-LABEL: vcneQi8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
%tmp1 = load <16 x i8>* %A
@@ -51,7 +51,7 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A,
}
define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcneQi16:
+;CHECK-LABEL: vcneQi16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
%tmp1 = load <8 x i16>* %A
@@ -62,7 +62,7 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A
}
define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcneQi32:
+;CHECK-LABEL: vcneQi32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
%tmp1 = load <4 x i32>* %A
@@ -73,7 +73,7 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A
}
define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcltQs8:
+;CHECK-LABEL: vcltQs8:
;CHECK: vcgt.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -83,7 +83,7 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A,
}
define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcles16:
+;CHECK-LABEL: vcles16:
;CHECK: vcge.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @vcles16(<4 x i16>* %A,
}
define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcltu16:
+;CHECK-LABEL: vcltu16:
;CHECK: vcgt.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -103,7 +103,7 @@ define <4 x i16> @vcltu16(<4 x i16>* %A,
}
define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcleQu32:
+;CHECK-LABEL: vcleQu32:
;CHECK: vcge.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld1.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.8 {d16}, [r0:64]
%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
@@ -10,7 +10,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind
}
define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
;CHECK: vld1.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
@@ -19,7 +19,7 @@ define <4 x i16> @vld1i16(i16* %A) nounw
;Check for a post-increment updating load.
define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
-;CHECK: vld1i16_update:
+;CHECK-LABEL: vld1i16_update:
;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
@@ -30,7 +30,7 @@ define <4 x i16> @vld1i16_update(i16** %
}
define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
;CHECK: vld1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
@@ -39,7 +39,7 @@ define <2 x i32> @vld1i32(i32* %A) nounw
;Check for a post-increment updating load with register increment.
define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
-;CHECK: vld1i32_update:
+;CHECK-LABEL: vld1i32_update:
;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
@@ -50,7 +50,7 @@ define <2 x i32> @vld1i32_update(i32** %
}
define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
;CHECK: vld1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nou
}
define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
;CHECK: vld1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
@@ -66,7 +66,7 @@ define <1 x i64> @vld1i64(i64* %A) nounw
}
define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.8 {d16, d17}, [r0:64]
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -75,7 +75,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwi
;Check for a post-increment updating load.
define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
-;CHECK: vld1Qi8_update:
+;CHECK-LABEL: vld1Qi8_update:
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
%A = load i8** %ptr
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -85,7 +85,7 @@ define <16 x i8> @vld1Qi8_update(i8** %p
}
define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
+;CHECK-LABEL: vld1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -94,7 +94,7 @@ define <8 x i16> @vld1Qi16(i16* %A) noun
}
define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
;CHECK: vld1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
@@ -102,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) noun
}
define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
;CHECK: vld1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
@@ -110,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) no
}
define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
;CHECK: vld1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
Modified: llvm/trunk/test/CodeGen/ARM/vld2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld2.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
define <8 x i8> @vld2i8(i8* %A) nounwind {
-;CHECK: vld2i8:
+;CHECK-LABEL: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.8 {d16, d17}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
@@ -23,7 +23,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind
}
define <4 x i16> @vld2i16(i16* %A) nounwind {
-;CHECK: vld2i16:
+;CHECK-LABEL: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -35,7 +35,7 @@ define <4 x i16> @vld2i16(i16* %A) nounw
}
define <2 x i32> @vld2i32(i32* %A) nounwind {
-;CHECK: vld2i32:
+;CHECK-LABEL: vld2i32:
;CHECK: vld2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1)
@@ -46,7 +46,7 @@ define <2 x i32> @vld2i32(i32* %A) nounw
}
define <2 x float> @vld2f(float* %A) nounwind {
-;CHECK: vld2f:
+;CHECK-LABEL: vld2f:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld2f(float* %A) nou
;Check for a post-increment updating load.
define <2 x float> @vld2f_update(float** %ptr) nounwind {
-;CHECK: vld2f_update:
+;CHECK-LABEL: vld2f_update:
;CHECK: vld2.32 {d16, d17}, [r1]!
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
@@ -72,7 +72,7 @@ define <2 x float> @vld2f_update(float**
}
define <1 x i64> @vld2i64(i64* %A) nounwind {
-;CHECK: vld2i64:
+;CHECK-LABEL: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.64 {d16, d17}, [r0:128]
%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld2i64(i64* %A) nounw
}
define <16 x i8> @vld2Qi8(i8* %A) nounwind {
-;CHECK: vld2Qi8:
+;CHECK-LABEL: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
@@ -96,7 +96,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwi
;Check for a post-increment updating load with register increment.
define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld2Qi8_update:
+;CHECK-LABEL: vld2Qi8_update:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
@@ -109,7 +109,7 @@ define <16 x i8> @vld2Qi8_update(i8** %p
}
define <8 x i16> @vld2Qi16(i16* %A) nounwind {
-;CHECK: vld2Qi16:
+;CHECK-LABEL: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <8 x i16> @vld2Qi16(i16* %A) noun
}
define <4 x i32> @vld2Qi32(i32* %A) nounwind {
-;CHECK: vld2Qi32:
+;CHECK-LABEL: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
@@ -133,7 +133,7 @@ define <4 x i32> @vld2Qi32(i32* %A) noun
}
define <4 x float> @vld2Qf(float* %A) nounwind {
-;CHECK: vld2Qf:
+;CHECK-LABEL: vld2Qf:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1)
Modified: llvm/trunk/test/CodeGen/ARM/vld3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld3.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld3.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld3i8(i8* %A) nounwind {
-;CHECK: vld3i8:
+;CHECK-LABEL: vld3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
@@ -24,7 +24,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind
}
define <4 x i16> @vld3i16(i16* %A) nounwind {
-;CHECK: vld3i16:
+;CHECK-LABEL: vld3i16:
;CHECK: vld3.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
@@ -36,7 +36,7 @@ define <4 x i16> @vld3i16(i16* %A) nounw
;Check for a post-increment updating load with register increment.
define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
-;CHECK: vld3i16_update:
+;CHECK-LABEL: vld3i16_update:
;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
@@ -50,7 +50,7 @@ define <4 x i16> @vld3i16_update(i16** %
}
define <2 x i32> @vld3i32(i32* %A) nounwind {
-;CHECK: vld3i32:
+;CHECK-LABEL: vld3i32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
@@ -61,7 +61,7 @@ define <2 x i32> @vld3i32(i32* %A) nounw
}
define <2 x float> @vld3f(float* %A) nounwind {
-;CHECK: vld3f:
+;CHECK-LABEL: vld3f:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld3f(float* %A) nou
}
define <1 x i64> @vld3i64(i64* %A) nounwind {
-;CHECK: vld3i64:
+;CHECK-LABEL: vld3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld3i64(i64* %A) nounw
}
define <16 x i8> @vld3Qi8(i8* %A) nounwind {
-;CHECK: vld3Qi8:
+;CHECK-LABEL: vld3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
@@ -96,7 +96,7 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwi
}
define <8 x i16> @vld3Qi16(i16* %A) nounwind {
-;CHECK: vld3Qi16:
+;CHECK-LABEL: vld3Qi16:
;CHECK: vld3.16
;CHECK: vld3.16
%tmp0 = bitcast i16* %A to i8*
@@ -108,7 +108,7 @@ define <8 x i16> @vld3Qi16(i16* %A) noun
}
define <4 x i32> @vld3Qi32(i32* %A) nounwind {
-;CHECK: vld3Qi32:
+;CHECK-LABEL: vld3Qi32:
;CHECK: vld3.32
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i32> @vld3Qi32(i32* %A) noun
;Check for a post-increment updating load.
define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
-;CHECK: vld3Qi32_update:
+;CHECK-LABEL: vld3Qi32_update:
;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
%A = load i32** %ptr
@@ -136,7 +136,7 @@ define <4 x i32> @vld3Qi32_update(i32**
}
define <4 x float> @vld3Qf(float* %A) nounwind {
-;CHECK: vld3Qf:
+;CHECK-LABEL: vld3Qf:
;CHECK: vld3.32
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
Modified: llvm/trunk/test/CodeGen/ARM/vld4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld4.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld4.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld4i8(i8* %A) nounwind {
-;CHECK: vld4i8:
+;CHECK-LABEL: vld4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
@@ -24,7 +24,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind
;Check for a post-increment updating load with register increment.
define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld4i8_update:
+;CHECK-LABEL: vld4i8_update:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
@@ -37,7 +37,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr
}
define <4 x i16> @vld4i16(i16* %A) nounwind {
-;CHECK: vld4i16:
+;CHECK-LABEL: vld4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -49,7 +49,7 @@ define <4 x i16> @vld4i16(i16* %A) nounw
}
define <2 x i32> @vld4i32(i32* %A) nounwind {
-;CHECK: vld4i32:
+;CHECK-LABEL: vld4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
@@ -61,7 +61,7 @@ define <2 x i32> @vld4i32(i32* %A) nounw
}
define <2 x float> @vld4f(float* %A) nounwind {
-;CHECK: vld4f:
+;CHECK-LABEL: vld4f:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld4f(float* %A) nou
}
define <1 x i64> @vld4i64(i64* %A) nounwind {
-;CHECK: vld4i64:
+;CHECK-LABEL: vld4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld4i64(i64* %A) nounw
}
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
-;CHECK: vld4Qi8:
+;CHECK-LABEL: vld4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
@@ -96,7 +96,7 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwi
}
define <8 x i16> @vld4Qi16(i16* %A) nounwind {
-;CHECK: vld4Qi16:
+;CHECK-LABEL: vld4Qi16:
;Check for no alignment specifier.
;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
@@ -110,7 +110,7 @@ define <8 x i16> @vld4Qi16(i16* %A) noun
;Check for a post-increment updating load.
define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
-;CHECK: vld4Qi16_update:
+;CHECK-LABEL: vld4Qi16_update:
;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
%A = load i16** %ptr
@@ -125,7 +125,7 @@ define <8 x i16> @vld4Qi16_update(i16**
}
define <4 x i32> @vld4Qi32(i32* %A) nounwind {
-;CHECK: vld4Qi32:
+;CHECK-LABEL: vld4Qi32:
;CHECK: vld4.32
;CHECK: vld4.32
%tmp0 = bitcast i32* %A to i8*
@@ -137,7 +137,7 @@ define <4 x i32> @vld4Qi32(i32* %A) noun
}
define <4 x float> @vld4Qf(float* %A) nounwind {
-;CHECK: vld4Qf:
+;CHECK-LABEL: vld4Qf:
;CHECK: vld4.32
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
Modified: llvm/trunk/test/CodeGen/ARM/vlddup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vlddup.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vlddup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vlddup.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vld1dupi8(i8* %A) nounwind {
-;CHECK: vld1dupi8:
+;CHECK-LABEL: vld1dupi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[]}, [r0]
%tmp1 = load i8* %A, align 8
@@ -11,7 +11,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounw
}
define <4 x i16> @vld1dupi16(i16* %A) nounwind {
-;CHECK: vld1dupi16:
+;CHECK-LABEL: vld1dupi16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[]}, [r0:16]
%tmp1 = load i16* %A, align 8
@@ -21,7 +21,7 @@ define <4 x i16> @vld1dupi16(i16* %A) no
}
define <2 x i32> @vld1dupi32(i32* %A) nounwind {
-;CHECK: vld1dupi32:
+;CHECK-LABEL: vld1dupi32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp1 = load i32* %A, align 8
@@ -31,7 +31,7 @@ define <2 x i32> @vld1dupi32(i32* %A) no
}
define <2 x float> @vld1dupf(float* %A) nounwind {
-;CHECK: vld1dupf:
+;CHECK-LABEL: vld1dupf:
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
@@ -40,7 +40,7 @@ define <2 x float> @vld1dupf(float* %A)
}
define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
-;CHECK: vld1dupQi8:
+;CHECK-LABEL: vld1dupQi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[], d17[]}, [r0]
%tmp1 = load i8* %A, align 8
@@ -50,7 +50,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nou
}
define <4 x float> @vld1dupQf(float* %A) nounwind {
-;CHECK: vld1dupQf:
+;CHECK-LABEL: vld1dupQf:
;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
@@ -63,7 +63,7 @@ define <4 x float> @vld1dupQf(float* %A)
%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
define <8 x i8> @vld2dupi8(i8* %A) nounwind {
-;CHECK: vld2dupi8:
+;CHECK-LABEL: vld2dupi8:
;Check the (default) alignment value.
;CHECK: vld2.8 {d16[], d17[]}, [r0]
%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
@@ -76,7 +76,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounw
}
define <4 x i16> @vld2dupi16(i8* %A) nounwind {
-;CHECK: vld2dupi16:
+;CHECK-LABEL: vld2dupi16:
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
;CHECK: vld2.16 {d16[], d17[]}, [r0]
@@ -91,7 +91,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nou
;Check for a post-increment updating load.
define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld2dupi16_update:
+;CHECK-LABEL: vld2dupi16_update:
;CHECK: vld2.16 {d16[], d17[]}, [r1]!
%A = load i16** %ptr
%A2 = bitcast i16* %A to i8*
@@ -107,7 +107,7 @@ define <4 x i16> @vld2dupi16_update(i16*
}
define <2 x i32> @vld2dupi32(i8* %A) nounwind {
-;CHECK: vld2dupi32:
+;CHECK-LABEL: vld2dupi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
@@ -128,7 +128,7 @@ declare %struct.__neon_int2x32x2_t @llvm
;Check for a post-increment updating load with register increment.
define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld3dupi8_update:
+;CHECK-LABEL: vld3dupi8_update:
;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
%A = load i8** %ptr
%tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
@@ -146,7 +146,7 @@ define <8 x i8> @vld3dupi8_update(i8** %
}
define <4 x i16> @vld3dupi16(i8* %A) nounwind {
-;CHECK: vld3dupi16:
+;CHECK-LABEL: vld3dupi16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
@@ -169,7 +169,7 @@ declare %struct.__neon_int16x4x3_t @llvm
;Check for a post-increment updating load.
define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld4dupi16_update:
+;CHECK-LABEL: vld4dupi16_update:
;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
%A = load i16** %ptr
%A2 = bitcast i16* %A to i8*
@@ -191,7 +191,7 @@ define <4 x i16> @vld4dupi16_update(i16*
}
define <2 x i32> @vld4dupi32(i8* %A) nounwind {
-;CHECK: vld4dupi32:
+;CHECK-LABEL: vld4dupi32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld1lanei8:
+;CHECK-LABEL: vld1lanei8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[3]}, [r0]
%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x
}
define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld1lanei16:
+;CHECK-LABEL: vld1lanei16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[2]}, [r0:16]
%tmp1 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vld1lanei16(i16* %A, <
}
define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32:
+;CHECK-LABEL: vld1lanei32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <
}
define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32a32:
+;CHECK-LABEL: vld1lanei32a32:
;Check the alignment value. Legal values are none or :32.
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @vld1lanei32a32(i32* %A
}
define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld1lanef:
+;CHECK-LABEL: vld1lanef:
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x float>* %B
%tmp2 = load float* %A, align 4
@@ -51,7 +51,7 @@ define <2 x float> @vld1lanef(float* %A,
}
define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vld1laneQi8:
+;CHECK-LABEL: vld1laneQi8:
;CHECK: vld1.8 {d17[1]}, [r0]
%tmp1 = load <16 x i8>* %B
%tmp2 = load i8* %A, align 8
@@ -60,7 +60,7 @@ define <16 x i8> @vld1laneQi8(i8* %A, <1
}
define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld1laneQi16:
+;CHECK-LABEL: vld1laneQi16:
;CHECK: vld1.16 {d17[1]}, [r0:16]
%tmp1 = load <8 x i16>* %B
%tmp2 = load i16* %A, align 8
@@ -69,7 +69,7 @@ define <8 x i16> @vld1laneQi16(i16* %A,
}
define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld1laneQi32:
+;CHECK-LABEL: vld1laneQi32:
;CHECK: vld1.32 {d17[1]}, [r0:32]
%tmp1 = load <4 x i32>* %B
%tmp2 = load i32* %A, align 8
@@ -78,7 +78,7 @@ define <4 x i32> @vld1laneQi32(i32* %A,
}
define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld1laneQf:
+;CHECK-LABEL: vld1laneQf:
;CHECK: vld1.32 {d16[0]}, [r0:32]
%tmp1 = load <4 x float>* %B
%tmp2 = load float* %A
@@ -96,7 +96,7 @@ define <4 x float> @vld1laneQf(float* %A
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld2lanei8:
+;CHECK-LABEL: vld2lanei8:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
%tmp1 = load <8 x i8>* %B
@@ -108,7 +108,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x
}
define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld2lanei16:
+;CHECK-LABEL: vld2lanei16:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <
}
define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32:
+;CHECK-LABEL: vld2lanei32:
;CHECK: vld2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -134,7 +134,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <
;Check for a post-increment updating load.
define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32_update:
+;CHECK-LABEL: vld2lanei32_update:
;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
@@ -149,7 +149,7 @@ define <2 x i32> @vld2lanei32_update(i32
}
define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld2lanef:
+;CHECK-LABEL: vld2lanef:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -161,7 +161,7 @@ define <2 x float> @vld2lanef(float* %A,
}
define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld2laneQi16:
+;CHECK-LABEL: vld2laneQi16:
;Check the (default) alignment.
;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
@@ -174,7 +174,7 @@ define <8 x i16> @vld2laneQi16(i16* %A,
}
define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld2laneQi32:
+;CHECK-LABEL: vld2laneQi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
%tmp0 = bitcast i32* %A to i8*
@@ -187,7 +187,7 @@ define <4 x i32> @vld2laneQi32(i32* %A,
}
define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld2laneQf:
+;CHECK-LABEL: vld2laneQf:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -217,7 +217,7 @@ declare %struct.__neon_float32x4x2_t @ll
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld3lanei8:
+;CHECK-LABEL: vld3lanei8:
;CHECK: vld3.8
%tmp1 = load <8 x i8>* %B
%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -230,7 +230,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x
}
define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld3lanei16:
+;CHECK-LABEL: vld3lanei16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
@@ -245,7 +245,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <
}
define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld3lanei32:
+;CHECK-LABEL: vld3lanei32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <
}
define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld3lanef:
+;CHECK-LABEL: vld3lanef:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -273,7 +273,7 @@ define <2 x float> @vld3lanef(float* %A,
}
define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld3laneQi16:
+;CHECK-LABEL: vld3laneQi16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
@@ -289,7 +289,7 @@ define <8 x i16> @vld3laneQi16(i16* %A,
;Check for a post-increment updating load with register increment.
define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vld3laneQi16_update:
+;CHECK-LABEL: vld3laneQi16_update:
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
@@ -306,7 +306,7 @@ define <8 x i16> @vld3laneQi16_update(i1
}
define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld3laneQi32:
+;CHECK-LABEL: vld3laneQi32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
@@ -320,7 +320,7 @@ define <4 x i32> @vld3laneQi32(i32* %A,
}
define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld3laneQf:
+;CHECK-LABEL: vld3laneQf:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -352,7 +352,7 @@ declare %struct.__neon_float32x4x3_t @ll
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8:
+;CHECK-LABEL: vld4lanei8:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
%tmp1 = load <8 x i8>* %B
@@ -369,7 +369,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x
;Check for a post-increment updating load.
define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8_update:
+;CHECK-LABEL: vld4lanei8_update:
;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
@@ -387,7 +387,7 @@ define <8 x i8> @vld4lanei8_update(i8**
}
define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld4lanei16:
+;CHECK-LABEL: vld4lanei16:
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}]
@@ -405,7 +405,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <
}
define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld4lanei32:
+;CHECK-LABEL: vld4lanei32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
@@ -423,7 +423,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <
}
define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld4lanef:
+;CHECK-LABEL: vld4lanef:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -439,7 +439,7 @@ define <2 x float> @vld4lanef(float* %A,
}
define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld4laneQi16:
+;CHECK-LABEL: vld4laneQi16:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
%tmp0 = bitcast i16* %A to i8*
@@ -456,7 +456,7 @@ define <8 x i16> @vld4laneQi16(i16* %A,
}
define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld4laneQi32:
+;CHECK-LABEL: vld4laneQi32:
;Check the (default) alignment.
;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}]
%tmp0 = bitcast i32* %A to i8*
@@ -473,7 +473,7 @@ define <4 x i32> @vld4laneQi32(i32* %A,
}
define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld4laneQf:
+;CHECK-LABEL: vld4laneQf:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vminmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vminmax.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vminmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vminmax.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmins8:
+;CHECK-LABEL: vmins8:
;CHECK: vmin.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8
}
define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmins16:
+;CHECK-LABEL: vmins16:
;CHECK: vmin.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmins16(<4 x i16>* %A,
}
define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmins32:
+;CHECK-LABEL: vmins32:
;CHECK: vmin.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmins32(<2 x i32>* %A,
}
define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vminu8:
+;CHECK-LABEL: vminu8:
;CHECK: vmin.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8
}
define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vminu16:
+;CHECK-LABEL: vminu16:
;CHECK: vmin.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vminu16(<4 x i16>* %A,
}
define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vminu32:
+;CHECK-LABEL: vminu32:
;CHECK: vmin.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vminu32(<2 x i32>* %A,
}
define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vminf32:
+;CHECK-LABEL: vminf32:
;CHECK: vmin.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vminf32(<2 x float>*
}
define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQs8:
+;CHECK-LABEL: vminQs8:
;CHECK: vmin.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vminQs8(<16 x i8>* %A,
}
define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQs16:
+;CHECK-LABEL: vminQs16:
;CHECK: vmin.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vminQs16(<8 x i16>* %A
}
define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQs32:
+;CHECK-LABEL: vminQs32:
;CHECK: vmin.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vminQs32(<4 x i32>* %A
}
define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQu8:
+;CHECK-LABEL: vminQu8:
;CHECK: vmin.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vminQu8(<16 x i8>* %A,
}
define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQu16:
+;CHECK-LABEL: vminQu16:
;CHECK: vmin.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vminQu16(<8 x i16>* %A
}
define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQu32:
+;CHECK-LABEL: vminQu32:
;CHECK: vmin.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vminQu32(<4 x i32>* %A
}
define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vminQf32:
+;CHECK-LABEL: vminQf32:
;CHECK: vmin.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vminu.v
declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxs8:
+;CHECK-LABEL: vmaxs8:
;CHECK: vmax.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -156,7 +156,7 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8
}
define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxs16:
+;CHECK-LABEL: vmaxs16:
;CHECK: vmax.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -165,7 +165,7 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A,
}
define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxs32:
+;CHECK-LABEL: vmaxs32:
;CHECK: vmax.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -174,7 +174,7 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A,
}
define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxu8:
+;CHECK-LABEL: vmaxu8:
;CHECK: vmax.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -183,7 +183,7 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8
}
define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxu16:
+;CHECK-LABEL: vmaxu16:
;CHECK: vmax.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -192,7 +192,7 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A,
}
define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxu32:
+;CHECK-LABEL: vmaxu32:
;CHECK: vmax.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -201,7 +201,7 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A,
}
define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmaxf32:
+;CHECK-LABEL: vmaxf32:
;CHECK: vmax.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -210,7 +210,7 @@ define <2 x float> @vmaxf32(<2 x float>*
}
define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQs8:
+;CHECK-LABEL: vmaxQs8:
;CHECK: vmax.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -219,7 +219,7 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A,
}
define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQs16:
+;CHECK-LABEL: vmaxQs16:
;CHECK: vmax.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A
}
define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQs32:
+;CHECK-LABEL: vmaxQs32:
;CHECK: vmax.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -237,7 +237,7 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A
}
define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQu8:
+;CHECK-LABEL: vmaxQu8:
;CHECK: vmax.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -246,7 +246,7 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A,
}
define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQu16:
+;CHECK-LABEL: vmaxQu16:
;CHECK: vmax.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -255,7 +255,7 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A
}
define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQu32:
+;CHECK-LABEL: vmaxQu32:
;CHECK: vmax.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -264,7 +264,7 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A
}
define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmaxQf32:
+;CHECK-LABEL: vmaxQf32:
;CHECK: vmax.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vmla.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmla.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmla.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmla.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlai8:
+;CHECK-LABEL: vmlai8:
;CHECK: vmla.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8
}
define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlai16:
+;CHECK-LABEL: vmlai16:
;CHECK: vmla.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlai16(<4 x i16>* %A,
}
define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlai32:
+;CHECK-LABEL: vmlai32:
;CHECK: vmla.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlai32(<2 x i32>* %A,
}
define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlaf32:
+;CHECK-LABEL: vmlaf32:
;CHECK: vmla.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlaf32(<2 x float>*
}
define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlaQi8:
+;CHECK-LABEL: vmlaQi8:
;CHECK: vmla.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A,
}
define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlaQi16:
+;CHECK-LABEL: vmlaQi16:
;CHECK: vmla.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A
}
define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlaQi32:
+;CHECK-LABEL: vmlaQi32:
;CHECK: vmla.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A
}
define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlaQf32:
+;CHECK-LABEL: vmlaQf32:
;CHECK: vmla.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlaQf32(<4 x float>
}
define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlals8:
+;CHECK-LABEL: vmlals8:
;CHECK: vmlal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlals8(<8 x i16>* %A,
}
define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlals16:
+;CHECK-LABEL: vmlals16:
;CHECK: vmlal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlals16(<4 x i32>* %A
}
define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlals32:
+;CHECK-LABEL: vmlals32:
;CHECK: vmlal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlals32(<2 x i64>* %A
}
define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlalu8:
+;CHECK-LABEL: vmlalu8:
;CHECK: vmlal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A,
}
define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlalu16:
+;CHECK-LABEL: vmlalu16:
;CHECK: vmlal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A
}
define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlalu32:
+;CHECK-LABEL: vmlalu32:
;CHECK: vmlal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vmls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmls.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlsi8:
+;CHECK-LABEL: vmlsi8:
;CHECK: vmls.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8
}
define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsi16:
+;CHECK-LABEL: vmlsi16:
;CHECK: vmls.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A,
}
define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsi32:
+;CHECK-LABEL: vmlsi32:
;CHECK: vmls.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A,
}
define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlsf32:
+;CHECK-LABEL: vmlsf32:
;CHECK: vmls.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlsf32(<2 x float>*
}
define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlsQi8:
+;CHECK-LABEL: vmlsQi8:
;CHECK: vmls.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A,
}
define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlsQi16:
+;CHECK-LABEL: vmlsQi16:
;CHECK: vmls.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A
}
define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlsQi32:
+;CHECK-LABEL: vmlsQi32:
;CHECK: vmls.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A
}
define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlsQf32:
+;CHECK-LABEL: vmlsQf32:
;CHECK: vmls.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlsQf32(<4 x float>
}
define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlsls8:
+;CHECK-LABEL: vmlsls8:
;CHECK: vmlsl.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A,
}
define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsls16:
+;CHECK-LABEL: vmlsls16:
;CHECK: vmlsl.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A
}
define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsls32:
+;CHECK-LABEL: vmlsls32:
;CHECK: vmlsl.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A
}
define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlslu8:
+;CHECK-LABEL: vmlslu8:
;CHECK: vmlsl.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A,
}
define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlslu16:
+;CHECK-LABEL: vmlslu16:
;CHECK: vmlsl.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A
}
define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlslu32:
+;CHECK-LABEL: vmlslu32:
;CHECK: vmlsl.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmov.ll Sun Jul 14 01:24:09 2013
@@ -1,169 +1,169 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_movi8() nounwind {
-;CHECK: v_movi8:
+;CHECK-LABEL: v_movi8:
;CHECK: vmov.i8 d{{.*}}, #0x8
ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @v_movi16a() nounwind {
-;CHECK: v_movi16a:
+;CHECK-LABEL: v_movi16a:
;CHECK: vmov.i16 d{{.*}}, #0x10
ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
define <4 x i16> @v_movi16b() nounwind {
-;CHECK: v_movi16b:
+;CHECK-LABEL: v_movi16b:
;CHECK: vmov.i16 d{{.*}}, #0x1000
ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i16> @v_mvni16a() nounwind {
-;CHECK: v_mvni16a:
+;CHECK-LABEL: v_mvni16a:
;CHECK: vmvn.i16 d{{.*}}, #0x10
ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
}
define <4 x i16> @v_mvni16b() nounwind {
-;CHECK: v_mvni16b:
+;CHECK-LABEL: v_mvni16b:
;CHECK: vmvn.i16 d{{.*}}, #0x1000
ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
}
define <2 x i32> @v_movi32a() nounwind {
-;CHECK: v_movi32a:
+;CHECK-LABEL: v_movi32a:
;CHECK: vmov.i32 d{{.*}}, #0x20
ret <2 x i32> < i32 32, i32 32 >
}
define <2 x i32> @v_movi32b() nounwind {
-;CHECK: v_movi32b:
+;CHECK-LABEL: v_movi32b:
;CHECK: vmov.i32 d{{.*}}, #0x2000
ret <2 x i32> < i32 8192, i32 8192 >
}
define <2 x i32> @v_movi32c() nounwind {
-;CHECK: v_movi32c:
+;CHECK-LABEL: v_movi32c:
;CHECK: vmov.i32 d{{.*}}, #0x200000
ret <2 x i32> < i32 2097152, i32 2097152 >
}
define <2 x i32> @v_movi32d() nounwind {
-;CHECK: v_movi32d:
+;CHECK-LABEL: v_movi32d:
;CHECK: vmov.i32 d{{.*}}, #0x20000000
ret <2 x i32> < i32 536870912, i32 536870912 >
}
define <2 x i32> @v_movi32e() nounwind {
-;CHECK: v_movi32e:
+;CHECK-LABEL: v_movi32e:
;CHECK: vmov.i32 d{{.*}}, #0x20ff
ret <2 x i32> < i32 8447, i32 8447 >
}
define <2 x i32> @v_movi32f() nounwind {
-;CHECK: v_movi32f:
+;CHECK-LABEL: v_movi32f:
;CHECK: vmov.i32 d{{.*}}, #0x20ffff
ret <2 x i32> < i32 2162687, i32 2162687 >
}
define <2 x i32> @v_mvni32a() nounwind {
-;CHECK: v_mvni32a:
+;CHECK-LABEL: v_mvni32a:
;CHECK: vmvn.i32 d{{.*}}, #0x20
ret <2 x i32> < i32 4294967263, i32 4294967263 >
}
define <2 x i32> @v_mvni32b() nounwind {
-;CHECK: v_mvni32b:
+;CHECK-LABEL: v_mvni32b:
;CHECK: vmvn.i32 d{{.*}}, #0x2000
ret <2 x i32> < i32 4294959103, i32 4294959103 >
}
define <2 x i32> @v_mvni32c() nounwind {
-;CHECK: v_mvni32c:
+;CHECK-LABEL: v_mvni32c:
;CHECK: vmvn.i32 d{{.*}}, #0x200000
ret <2 x i32> < i32 4292870143, i32 4292870143 >
}
define <2 x i32> @v_mvni32d() nounwind {
-;CHECK: v_mvni32d:
+;CHECK-LABEL: v_mvni32d:
;CHECK: vmvn.i32 d{{.*}}, #0x20000000
ret <2 x i32> < i32 3758096383, i32 3758096383 >
}
define <2 x i32> @v_mvni32e() nounwind {
-;CHECK: v_mvni32e:
+;CHECK-LABEL: v_mvni32e:
;CHECK: vmvn.i32 d{{.*}}, #0x20ff
ret <2 x i32> < i32 4294958848, i32 4294958848 >
}
define <2 x i32> @v_mvni32f() nounwind {
-;CHECK: v_mvni32f:
+;CHECK-LABEL: v_mvni32f:
;CHECK: vmvn.i32 d{{.*}}, #0x20ffff
ret <2 x i32> < i32 4292804608, i32 4292804608 >
}
define <1 x i64> @v_movi64() nounwind {
-;CHECK: v_movi64:
+;CHECK-LABEL: v_movi64:
;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff
ret <1 x i64> < i64 18374687574888349695 >
}
define <16 x i8> @v_movQi8() nounwind {
-;CHECK: v_movQi8:
+;CHECK-LABEL: v_movQi8:
;CHECK: vmov.i8 q{{.*}}, #0x8
ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @v_movQi16a() nounwind {
-;CHECK: v_movQi16a:
+;CHECK-LABEL: v_movQi16a:
;CHECK: vmov.i16 q{{.*}}, #0x10
ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define <8 x i16> @v_movQi16b() nounwind {
-;CHECK: v_movQi16b:
+;CHECK-LABEL: v_movQi16b:
;CHECK: vmov.i16 q{{.*}}, #0x1000
ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i32> @v_movQi32a() nounwind {
-;CHECK: v_movQi32a:
+;CHECK-LABEL: v_movQi32a:
;CHECK: vmov.i32 q{{.*}}, #0x20
ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
define <4 x i32> @v_movQi32b() nounwind {
-;CHECK: v_movQi32b:
+;CHECK-LABEL: v_movQi32b:
;CHECK: vmov.i32 q{{.*}}, #0x2000
ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
define <4 x i32> @v_movQi32c() nounwind {
-;CHECK: v_movQi32c:
+;CHECK-LABEL: v_movQi32c:
;CHECK: vmov.i32 q{{.*}}, #0x200000
ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
define <4 x i32> @v_movQi32d() nounwind {
-;CHECK: v_movQi32d:
+;CHECK-LABEL: v_movQi32d:
;CHECK: vmov.i32 q{{.*}}, #0x20000000
ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
define <4 x i32> @v_movQi32e() nounwind {
-;CHECK: v_movQi32e:
+;CHECK-LABEL: v_movQi32e:
;CHECK: vmov.i32 q{{.*}}, #0x20ff
ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
define <4 x i32> @v_movQi32f() nounwind {
-;CHECK: v_movQi32f:
+;CHECK-LABEL: v_movQi32f:
;CHECK: vmov.i32 q{{.*}}, #0x20ffff
ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
define <2 x i64> @v_movQi64() nounwind {
-;CHECK: v_movQi64:
+;CHECK-LABEL: v_movQi64:
;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
@@ -172,7 +172,7 @@ define <2 x i64> @v_movQi64() nounwind {
%struct.int8x8_t = type { <8 x i8> }
define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
entry:
-;CHECK: vdupn128:
+;CHECK-LABEL: vdupn128:
;CHECK: vmov.i8 d{{.*}}, #0x80
%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
@@ -181,7 +181,7 @@ entry:
define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
entry:
-;CHECK: vdupnneg75:
+;CHECK-LABEL: vdupnneg75:
;CHECK: vmov.i8 d{{.*}}, #0xb5
%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
@@ -189,7 +189,7 @@ entry:
}
define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
-;CHECK: vmovls8:
+;CHECK-LABEL: vmovls8:
;CHECK: vmovl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
@@ -197,7 +197,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A)
}
define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
-;CHECK: vmovls16:
+;CHECK-LABEL: vmovls16:
;CHECK: vmovl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
@@ -205,7 +205,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A
}
define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
-;CHECK: vmovls32:
+;CHECK-LABEL: vmovls32:
;CHECK: vmovl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
@@ -213,7 +213,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A
}
define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
-;CHECK: vmovlu8:
+;CHECK-LABEL: vmovlu8:
;CHECK: vmovl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
@@ -221,7 +221,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A)
}
define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
-;CHECK: vmovlu16:
+;CHECK-LABEL: vmovlu16:
;CHECK: vmovl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
@@ -229,7 +229,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A
}
define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
-;CHECK: vmovlu32:
+;CHECK-LABEL: vmovlu32:
;CHECK: vmovl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
@@ -237,7 +237,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A
}
define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
-;CHECK: vmovni16:
+;CHECK-LABEL: vmovni16:
;CHECK: vmovn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
@@ -245,7 +245,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A)
}
define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
-;CHECK: vmovni32:
+;CHECK-LABEL: vmovni32:
;CHECK: vmovn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
@@ -253,7 +253,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A
}
define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
-;CHECK: vmovni64:
+;CHECK-LABEL: vmovni64:
;CHECK: vmovn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
@@ -261,7 +261,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A
}
define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovns16:
+;CHECK-LABEL: vqmovns16:
;CHECK: vqmovn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
@@ -269,7 +269,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A
}
define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovns32:
+;CHECK-LABEL: vqmovns32:
;CHECK: vqmovn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
@@ -277,7 +277,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %
}
define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovns64:
+;CHECK-LABEL: vqmovns64:
;CHECK: vqmovn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
@@ -285,7 +285,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %
}
define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovnu16:
+;CHECK-LABEL: vqmovnu16:
;CHECK: vqmovn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
@@ -293,7 +293,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A
}
define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovnu32:
+;CHECK-LABEL: vqmovnu32:
;CHECK: vqmovn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
@@ -301,7 +301,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %
}
define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovnu64:
+;CHECK-LABEL: vqmovnu64:
;CHECK: vqmovn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
@@ -309,7 +309,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %
}
define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovuns16:
+;CHECK-LABEL: vqmovuns16:
;CHECK: vqmovun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
@@ -317,7 +317,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %
}
define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovuns32:
+;CHECK-LABEL: vqmovuns32:
;CHECK: vqmovun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
@@ -325,7 +325,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>*
}
define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovuns64:
+;CHECK-LABEL: vqmovuns64:
;CHECK: vqmovun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
@@ -358,7 +358,7 @@ define void @noTruncStore(<4 x i32>* %a,
; rdar://10437054
define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v2f32:
+;CHECK-LABEL: v_mov_v2f32:
;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
ret void
@@ -366,7 +366,7 @@ entry:
define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v4f32:
+;CHECK-LABEL: v_mov_v4f32:
;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
ret void
@@ -374,7 +374,7 @@ entry:
define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v4f32_undef:
+;CHECK-LABEL: v_mov_v4f32_undef:
;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
%a = load <4 x float> *%p
%b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmul.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmuli8:
+;CHECK-LABEL: vmuli8:
;CHECK: vmul.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8
}
define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmuli16:
+;CHECK-LABEL: vmuli16:
;CHECK: vmul.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmuli16(<4 x i16>* %A,
}
define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmuli32:
+;CHECK-LABEL: vmuli32:
;CHECK: vmul.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmuli32(<2 x i32>* %A,
}
define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmulf32:
+;CHECK-LABEL: vmulf32:
;CHECK: vmul.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -37,7 +37,7 @@ define <2 x float> @vmulf32(<2 x float>*
}
define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulp8:
+;CHECK-LABEL: vmulp8:
;CHECK: vmul.p8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8
}
define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQi8:
+;CHECK-LABEL: vmulQi8:
;CHECK: vmul.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A,
}
define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmulQi16:
+;CHECK-LABEL: vmulQi16:
;CHECK: vmul.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A
}
define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmulQi32:
+;CHECK-LABEL: vmulQi32:
;CHECK: vmul.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A
}
define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmulQf32:
+;CHECK-LABEL: vmulQf32:
;CHECK: vmul.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -82,7 +82,7 @@ define <4 x float> @vmulQf32(<4 x float>
}
define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQp8:
+;CHECK-LABEL: vmulQp8:
;CHECK: vmul.p8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -148,7 +148,7 @@ entry:
}
define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8:
+;CHECK-LABEL: vmulls8:
;CHECK: vmull.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -159,7 +159,7 @@ define <8 x i16> @vmulls8(<8 x i8>* %A,
}
define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8_int:
+;CHECK-LABEL: vmulls8_int:
;CHECK: vmull.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -168,7 +168,7 @@ define <8 x i16> @vmulls8_int(<8 x i8>*
}
define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16:
+;CHECK-LABEL: vmulls16:
;CHECK: vmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -179,7 +179,7 @@ define <4 x i32> @vmulls16(<4 x i16>* %A
}
define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16_int:
+;CHECK-LABEL: vmulls16_int:
;CHECK: vmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -188,7 +188,7 @@ define <4 x i32> @vmulls16_int(<4 x i16>
}
define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32:
+;CHECK-LABEL: vmulls32:
;CHECK: vmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -199,7 +199,7 @@ define <2 x i64> @vmulls32(<2 x i32>* %A
}
define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32_int:
+;CHECK-LABEL: vmulls32_int:
;CHECK: vmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -208,7 +208,7 @@ define <2 x i64> @vmulls32_int(<2 x i32>
}
define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8:
+;CHECK-LABEL: vmullu8:
;CHECK: vmull.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -219,7 +219,7 @@ define <8 x i16> @vmullu8(<8 x i8>* %A,
}
define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8_int:
+;CHECK-LABEL: vmullu8_int:
;CHECK: vmull.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmullu8_int(<8 x i8>*
}
define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16:
+;CHECK-LABEL: vmullu16:
;CHECK: vmull.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vmullu16(<4 x i16>* %A
}
define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16_int:
+;CHECK-LABEL: vmullu16_int:
;CHECK: vmull.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -248,7 +248,7 @@ define <4 x i32> @vmullu16_int(<4 x i16>
}
define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32:
+;CHECK-LABEL: vmullu32:
;CHECK: vmull.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i64> @vmullu32(<2 x i32>* %A
}
define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32_int:
+;CHECK-LABEL: vmullu32_int:
;CHECK: vmull.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -268,7 +268,7 @@ define <2 x i64> @vmullu32_int(<2 x i32>
}
define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullp8:
+;CHECK-LABEL: vmullp8:
;CHECK: vmull.p8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @vmull_extvec_u32(<2 x
; rdar://9197392
define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
entry:
-; CHECK: distribute:
+; CHECK-LABEL: distribute:
; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
%0 = trunc i32 %mul to i8
Modified: llvm/trunk/test/CodeGen/ARM/vneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vneg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vneg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vneg.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vnegs8:
+;CHECK-LABEL: vnegs8:
;CHECK: vneg.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
@@ -9,7 +9,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) no
}
define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vnegs16:
+;CHECK-LABEL: vnegs16:
;CHECK: vneg.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
@@ -17,7 +17,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A)
}
define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vnegs32:
+;CHECK-LABEL: vnegs32:
;CHECK: vneg.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
@@ -25,7 +25,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A)
}
define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
-;CHECK: vnegf32:
+;CHECK-LABEL: vnegf32:
;CHECK: vneg.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -33,7 +33,7 @@ define <2 x float> @vnegf32(<2 x float>*
}
define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vnegQs8:
+;CHECK-LABEL: vnegQs8:
;CHECK: vneg.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
@@ -41,7 +41,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A)
}
define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vnegQs16:
+;CHECK-LABEL: vnegQs16:
;CHECK: vneg.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
@@ -49,7 +49,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A
}
define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vnegQs32:
+;CHECK-LABEL: vnegQs32:
;CHECK: vneg.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
@@ -57,7 +57,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A
}
define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
-;CHECK: vnegQf32:
+;CHECK-LABEL: vnegQf32:
;CHECK: vneg.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -65,7 +65,7 @@ define <4 x float> @vnegQf32(<4 x float>
}
define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vqnegs8:
+;CHECK-LABEL: vqnegs8:
;CHECK: vqneg.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
@@ -73,7 +73,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) n
}
define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vqnegs16:
+;CHECK-LABEL: vqnegs16:
;CHECK: vqneg.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
@@ -81,7 +81,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A
}
define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vqnegs32:
+;CHECK-LABEL: vqnegs32:
;CHECK: vqneg.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
@@ -89,7 +89,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A
}
define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqnegQs8:
+;CHECK-LABEL: vqnegQs8:
;CHECK: vqneg.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
@@ -97,7 +97,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A
}
define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqnegQs16:
+;CHECK-LABEL: vqnegQs16:
;CHECK: vqneg.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
@@ -105,7 +105,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %
}
define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqnegQs32:
+;CHECK-LABEL: vqnegQs32:
;CHECK: vqneg.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
Modified: llvm/trunk/test/CodeGen/ARM/vpadal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpadal.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vpadal.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vpadal.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadals8:
+;CHECK-LABEL: vpadals8:
;CHECK: vpadal.s8
%tmp1 = load <4 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <4 x i16> @vpadals8(<4 x i16>* %A
}
define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadals16:
+;CHECK-LABEL: vpadals16:
;CHECK: vpadal.s16
%tmp1 = load <2 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <2 x i32> @vpadals16(<2 x i32>* %
}
define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadals32:
+;CHECK-LABEL: vpadals32:
;CHECK: vpadal.s32
%tmp1 = load <1 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <1 x i64> @vpadals32(<1 x i64>* %
}
define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadalu8:
+;CHECK-LABEL: vpadalu8:
;CHECK: vpadal.u8
%tmp1 = load <4 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A
}
define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadalu16:
+;CHECK-LABEL: vpadalu16:
;CHECK: vpadal.u16
%tmp1 = load <2 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <2 x i32> @vpadalu16(<2 x i32>* %
}
define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadalu32:
+;CHECK-LABEL: vpadalu32:
;CHECK: vpadal.u32
%tmp1 = load <1 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @vpadalu32(<1 x i64>* %
}
define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQs8:
+;CHECK-LABEL: vpadalQs8:
;CHECK: vpadal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %
}
define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQs16:
+;CHECK-LABEL: vpadalQs16:
;CHECK: vpadal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vpadalQs16(<4 x i32>*
}
define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQs32:
+;CHECK-LABEL: vpadalQs32:
;CHECK: vpadal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vpadalQs32(<2 x i64>*
}
define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQu8:
+;CHECK-LABEL: vpadalQu8:
;CHECK: vpadal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %
}
define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQu16:
+;CHECK-LABEL: vpadalQu16:
;CHECK: vpadal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vpadalQu16(<4 x i32>*
}
define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQu32:
+;CHECK-LABEL: vpadalQu32:
;CHECK: vpadal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <4 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vpadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpadd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vpadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vpadd.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpaddi8:
+;CHECK-LABEL: vpaddi8:
;CHECK: vpadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <
}
define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpaddi16:
+;CHECK-LABEL: vpaddi16:
;CHECK: vpadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A
}
define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpaddi32:
+;CHECK-LABEL: vpaddi32:
;CHECK: vpadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A
}
define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpaddf32:
+;CHECK-LABEL: vpaddf32:
;CHECK: vpadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -43,7 +43,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddls8:
+;CHECK-LABEL: vpaddls8:
;CHECK: vpaddl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
@@ -51,7 +51,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A)
}
define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddls16:
+;CHECK-LABEL: vpaddls16:
;CHECK: vpaddl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
@@ -59,7 +59,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %
}
define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddls32:
+;CHECK-LABEL: vpaddls32:
;CHECK: vpaddl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
@@ -67,7 +67,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %
}
define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddlu8:
+;CHECK-LABEL: vpaddlu8:
;CHECK: vpaddl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
@@ -75,7 +75,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A)
}
define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddlu16:
+;CHECK-LABEL: vpaddlu16:
;CHECK: vpaddl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
@@ -83,7 +83,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %
}
define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddlu32:
+;CHECK-LABEL: vpaddlu32:
;CHECK: vpaddl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
@@ -91,7 +91,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %
}
define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQs8:
+;CHECK-LABEL: vpaddlQs8:
;CHECK: vpaddl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
@@ -99,7 +99,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %
}
define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQs16:
+;CHECK-LABEL: vpaddlQs16:
;CHECK: vpaddl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
@@ -107,7 +107,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>*
}
define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQs32:
+;CHECK-LABEL: vpaddlQs32:
;CHECK: vpaddl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
@@ -115,7 +115,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>*
}
define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQu8:
+;CHECK-LABEL: vpaddlQu8:
;CHECK: vpaddl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
@@ -123,7 +123,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %
}
define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQu16:
+;CHECK-LABEL: vpaddlQu16:
;CHECK: vpaddl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
@@ -131,7 +131,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>*
}
define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQu32:
+;CHECK-LABEL: vpaddlQu32:
;CHECK: vpaddl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
Modified: llvm/trunk/test/CodeGen/ARM/vpminmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpminmax.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vpminmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vpminmax.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmins8:
+;CHECK-LABEL: vpmins8:
;CHECK: vpmin.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <
}
define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmins16:
+;CHECK-LABEL: vpmins16:
;CHECK: vpmin.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpmins16(<4 x i16>* %A
}
define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmins32:
+;CHECK-LABEL: vpmins32:
;CHECK: vpmin.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpmins32(<2 x i32>* %A
}
define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpminu8:
+;CHECK-LABEL: vpminu8:
;CHECK: vpmin.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <
}
define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpminu16:
+;CHECK-LABEL: vpminu16:
;CHECK: vpmin.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vpminu16(<4 x i16>* %A
}
define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpminu32:
+;CHECK-LABEL: vpminu32:
;CHECK: vpmin.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vpminu32(<2 x i32>* %A
}
define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpminf32:
+;CHECK-LABEL: vpminf32:
;CHECK: vpmin.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -74,7 +74,7 @@ declare <2 x i32> @llvm.arm.neon.vpminu.
declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxs8:
+;CHECK-LABEL: vpmaxs8:
;CHECK: vpmax.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <
}
define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxs16:
+;CHECK-LABEL: vpmaxs16:
;CHECK: vpmax.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -92,7 +92,7 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A
}
define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxs32:
+;CHECK-LABEL: vpmaxs32:
;CHECK: vpmax.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -101,7 +101,7 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A
}
define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxu8:
+;CHECK-LABEL: vpmaxu8:
;CHECK: vpmax.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -110,7 +110,7 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <
}
define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxu16:
+;CHECK-LABEL: vpmaxu16:
;CHECK: vpmax.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -119,7 +119,7 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A
}
define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxu32:
+;CHECK-LABEL: vpmaxu32:
;CHECK: vpmax.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A
}
define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpmaxf32:
+;CHECK-LABEL: vpmaxf32:
;CHECK: vpmax.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vqadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqadd.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vqadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vqadd.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqadds8:
+;CHECK-LABEL: vqadds8:
;CHECK: vqadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <
}
define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqadds16:
+;CHECK-LABEL: vqadds16:
;CHECK: vqadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqadds16(<4 x i16>* %A
}
define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqadds32:
+;CHECK-LABEL: vqadds32:
;CHECK: vqadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqadds32(<2 x i32>* %A
}
define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqadds64:
+;CHECK-LABEL: vqadds64:
;CHECK: vqadd.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqadds64(<1 x i64>* %A
}
define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqaddu8:
+;CHECK-LABEL: vqaddu8:
;CHECK: vqadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <
}
define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqaddu16:
+;CHECK-LABEL: vqaddu16:
;CHECK: vqadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A
}
define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqaddu32:
+;CHECK-LABEL: vqaddu32:
;CHECK: vqadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A
}
define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqaddu64:
+;CHECK-LABEL: vqaddu64:
;CHECK: vqadd.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A
}
define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQs8:
+;CHECK-LABEL: vqaddQs8:
;CHECK: vqadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A
}
define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQs16:
+;CHECK-LABEL: vqaddQs16:
;CHECK: vqadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %
}
define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQs32:
+;CHECK-LABEL: vqaddQs32:
;CHECK: vqadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %
}
define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQs64:
+;CHECK-LABEL: vqaddQs64:
;CHECK: vqadd.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %
}
define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQu8:
+;CHECK-LABEL: vqaddQu8:
;CHECK: vqadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A
}
define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQu16:
+;CHECK-LABEL: vqaddQu16:
;CHECK: vqadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %
}
define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQu32:
+;CHECK-LABEL: vqaddQu32:
;CHECK: vqadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %
}
define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQu64:
+;CHECK-LABEL: vqaddQu64:
;CHECK: vqadd.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vqdmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqdmul.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vqdmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vqdmul.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:3
target triple = "thumbv7-elf"
define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulhs16:
+;CHECK-LABEL: vqdmulhs16:
;CHECK: vqdmulh.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -12,7 +12,7 @@ define <4 x i16> @vqdmulhs16(<4 x i16>*
}
define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulhs32:
+;CHECK-LABEL: vqdmulhs32:
;CHECK: vqdmulh.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -21,7 +21,7 @@ define <2 x i32> @vqdmulhs32(<2 x i32>*
}
define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqdmulhQs16:
+;CHECK-LABEL: vqdmulhQs16:
;CHECK: vqdmulh.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -30,7 +30,7 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>*
}
define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqdmulhQs32:
+;CHECK-LABEL: vqdmulhQs32:
;CHECK: vqdmulh.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -81,7 +81,7 @@ declare <8 x i16> @llvm.arm.neon.vqdmulh
declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrdmulhs16:
+;CHECK-LABEL: vqrdmulhs16:
;CHECK: vqrdmulh.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -90,7 +90,7 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>*
}
define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrdmulhs32:
+;CHECK-LABEL: vqrdmulhs32:
;CHECK: vqrdmulh.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -99,7 +99,7 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>*
}
define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrdmulhQs16:
+;CHECK-LABEL: vqrdmulhQs16:
;CHECK: vqrdmulh.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -108,7 +108,7 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>
}
define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrdmulhQs32:
+;CHECK-LABEL: vqrdmulhQs32:
;CHECK: vqrdmulh.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -159,7 +159,7 @@ declare <8 x i16> @llvm.arm.neon.vqrdmul
declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulls16:
+;CHECK-LABEL: vqdmulls16:
;CHECK: vqdmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -168,7 +168,7 @@ define <4 x i32> @vqdmulls16(<4 x i16>*
}
define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulls32:
+;CHECK-LABEL: vqdmulls32:
;CHECK: vqdmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -198,7 +198,7 @@ declare <4 x i32> @llvm.arm.neon.vqdmul
declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlals16:
+;CHECK-LABEL: vqdmlals16:
;CHECK: vqdmlal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vqdmlals16(<4 x i32>*
}
define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlals32:
+;CHECK-LABEL: vqdmlals32:
;CHECK: vqdmlal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -239,7 +239,7 @@ declare <4 x i32> @llvm.arm.neon.vqdmla
declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlsls16:
+;CHECK-LABEL: vqdmlsls16:
;CHECK: vqdmlsl.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -249,7 +249,7 @@ define <4 x i32> @vqdmlsls16(<4 x i32>*
}
define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlsls32:
+;CHECK-LABEL: vqdmlsls32:
;CHECK: vqdmlsl.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vqshl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqshl.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vqshl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vqshl.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshls8:
+;CHECK-LABEL: vqshls8:
;CHECK: vqshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <
}
define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshls16:
+;CHECK-LABEL: vqshls16:
;CHECK: vqshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqshls16(<4 x i16>* %A
}
define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshls32:
+;CHECK-LABEL: vqshls32:
;CHECK: vqshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqshls32(<2 x i32>* %A
}
define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshls64:
+;CHECK-LABEL: vqshls64:
;CHECK: vqshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqshls64(<1 x i64>* %A
}
define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshlu8:
+;CHECK-LABEL: vqshlu8:
;CHECK: vqshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <
}
define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshlu16:
+;CHECK-LABEL: vqshlu16:
;CHECK: vqshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A
}
define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshlu32:
+;CHECK-LABEL: vqshlu32:
;CHECK: vqshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A
}
define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshlu64:
+;CHECK-LABEL: vqshlu64:
;CHECK: vqshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A
}
define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQs8:
+;CHECK-LABEL: vqshlQs8:
;CHECK: vqshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A
}
define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQs16:
+;CHECK-LABEL: vqshlQs16:
;CHECK: vqshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %
}
define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQs32:
+;CHECK-LABEL: vqshlQs32:
;CHECK: vqshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %
}
define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQs64:
+;CHECK-LABEL: vqshlQs64:
;CHECK: vqshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %
}
define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQu8:
+;CHECK-LABEL: vqshlQu8:
;CHECK: vqshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A
}
define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQu16:
+;CHECK-LABEL: vqshlQu16:
;CHECK: vqshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %
}
define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQu32:
+;CHECK-LABEL: vqshlQu32:
;CHECK: vqshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %
}
define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQu64:
+;CHECK-LABEL: vqshlQu64:
;CHECK: vqshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -145,7 +145,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %
}
define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshls_n8:
+;CHECK-LABEL: vqshls_n8:
;CHECK: vqshl.s8{{.*#7}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -153,7 +153,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A)
}
define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshls_n16:
+;CHECK-LABEL: vqshls_n16:
;CHECK: vqshl.s16{{.*#15}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -161,7 +161,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>*
}
define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshls_n32:
+;CHECK-LABEL: vqshls_n32:
;CHECK: vqshl.s32{{.*#31}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -169,7 +169,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>*
}
define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshls_n64:
+;CHECK-LABEL: vqshls_n64:
;CHECK: vqshl.s64{{.*#63}}
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -177,7 +177,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>*
}
define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlu_n8:
+;CHECK-LABEL: vqshlu_n8:
;CHECK: vqshl.u8{{.*#7}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -185,7 +185,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A)
}
define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlu_n16:
+;CHECK-LABEL: vqshlu_n16:
;CHECK: vqshl.u16{{.*#15}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -193,7 +193,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>*
}
define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlu_n32:
+;CHECK-LABEL: vqshlu_n32:
;CHECK: vqshl.u32{{.*#31}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -201,7 +201,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>*
}
define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlu_n64:
+;CHECK-LABEL: vqshlu_n64:
;CHECK: vqshl.u64{{.*#63}}
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -209,7 +209,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>*
}
define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlsu_n8:
+;CHECK-LABEL: vqshlsu_n8:
;CHECK: vqshlu.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -217,7 +217,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A
}
define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlsu_n16:
+;CHECK-LABEL: vqshlsu_n16:
;CHECK: vqshlu.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -225,7 +225,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>*
}
define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlsu_n32:
+;CHECK-LABEL: vqshlsu_n32:
;CHECK: vqshlu.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -233,7 +233,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>*
}
define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlsu_n64:
+;CHECK-LABEL: vqshlsu_n64:
;CHECK: vqshlu.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -241,7 +241,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>*
}
define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQs_n8:
+;CHECK-LABEL: vqshlQs_n8:
;CHECK: vqshl.s8{{.*#7}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -249,7 +249,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>*
}
define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQs_n16:
+;CHECK-LABEL: vqshlQs_n16:
;CHECK: vqshl.s16{{.*#15}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -257,7 +257,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>*
}
define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQs_n32:
+;CHECK-LABEL: vqshlQs_n32:
;CHECK: vqshl.s32{{.*#31}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -265,7 +265,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>*
}
define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQs_n64:
+;CHECK-LABEL: vqshlQs_n64:
;CHECK: vqshl.s64{{.*#63}}
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -273,7 +273,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>*
}
define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQu_n8:
+;CHECK-LABEL: vqshlQu_n8:
;CHECK: vqshl.u8{{.*#7}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -281,7 +281,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>*
}
define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQu_n16:
+;CHECK-LABEL: vqshlQu_n16:
;CHECK: vqshl.u16{{.*#15}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -289,7 +289,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>*
}
define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQu_n32:
+;CHECK-LABEL: vqshlQu_n32:
;CHECK: vqshl.u32{{.*#31}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -297,7 +297,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>*
}
define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQu_n64:
+;CHECK-LABEL: vqshlQu_n64:
;CHECK: vqshl.u64{{.*#63}}
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -305,7 +305,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>*
}
define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQsu_n8:
+;CHECK-LABEL: vqshlQsu_n8:
;CHECK: vqshlu.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -313,7 +313,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>*
}
define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQsu_n16:
+;CHECK-LABEL: vqshlQsu_n16:
;CHECK: vqshlu.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -321,7 +321,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>
}
define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQsu_n32:
+;CHECK-LABEL: vqshlQsu_n32:
;CHECK: vqshlu.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -329,7 +329,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>
}
define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQsu_n64:
+;CHECK-LABEL: vqshlQsu_n64:
;CHECK: vqshlu.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -367,7 +367,7 @@ declare <4 x i32> @llvm.arm.neon.vqshift
declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshls8:
+;CHECK-LABEL: vqrshls8:
;CHECK: vqrshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -376,7 +376,7 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A,
}
define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshls16:
+;CHECK-LABEL: vqrshls16:
;CHECK: vqrshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -385,7 +385,7 @@ define <4 x i16> @vqrshls16(<4 x i16>* %
}
define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshls32:
+;CHECK-LABEL: vqrshls32:
;CHECK: vqrshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -394,7 +394,7 @@ define <2 x i32> @vqrshls32(<2 x i32>* %
}
define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshls64:
+;CHECK-LABEL: vqrshls64:
;CHECK: vqrshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -403,7 +403,7 @@ define <1 x i64> @vqrshls64(<1 x i64>* %
}
define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshlu8:
+;CHECK-LABEL: vqrshlu8:
;CHECK: vqrshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -412,7 +412,7 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A,
}
define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshlu16:
+;CHECK-LABEL: vqrshlu16:
;CHECK: vqrshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -421,7 +421,7 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %
}
define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshlu32:
+;CHECK-LABEL: vqrshlu32:
;CHECK: vqrshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -430,7 +430,7 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %
}
define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshlu64:
+;CHECK-LABEL: vqrshlu64:
;CHECK: vqrshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -439,7 +439,7 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %
}
define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQs8:
+;CHECK-LABEL: vqrshlQs8:
;CHECK: vqrshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -448,7 +448,7 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %
}
define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQs16:
+;CHECK-LABEL: vqrshlQs16:
;CHECK: vqrshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -457,7 +457,7 @@ define <8 x i16> @vqrshlQs16(<8 x i16>*
}
define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQs32:
+;CHECK-LABEL: vqrshlQs32:
;CHECK: vqrshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -466,7 +466,7 @@ define <4 x i32> @vqrshlQs32(<4 x i32>*
}
define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQs64:
+;CHECK-LABEL: vqrshlQs64:
;CHECK: vqrshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -475,7 +475,7 @@ define <2 x i64> @vqrshlQs64(<2 x i64>*
}
define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQu8:
+;CHECK-LABEL: vqrshlQu8:
;CHECK: vqrshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -484,7 +484,7 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %
}
define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQu16:
+;CHECK-LABEL: vqrshlQu16:
;CHECK: vqrshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -493,7 +493,7 @@ define <8 x i16> @vqrshlQu16(<8 x i16>*
}
define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQu32:
+;CHECK-LABEL: vqrshlQu32:
;CHECK: vqrshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -502,7 +502,7 @@ define <4 x i32> @vqrshlQu32(<4 x i32>*
}
define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQu64:
+;CHECK-LABEL: vqrshlQu64:
;CHECK: vqrshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vqshrn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqshrn.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vqshrn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vqshrn.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrns8:
+;CHECK-LABEL: vqshrns8:
;CHECK: vqshrn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A)
}
define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrns16:
+;CHECK-LABEL: vqshrns16:
;CHECK: vqshrn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %
}
define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrns32:
+;CHECK-LABEL: vqshrns32:
;CHECK: vqshrn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -25,7 +25,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %
}
define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrnu8:
+;CHECK-LABEL: vqshrnu8:
;CHECK: vqshrn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -33,7 +33,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A)
}
define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrnu16:
+;CHECK-LABEL: vqshrnu16:
;CHECK: vqshrn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -41,7 +41,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %
}
define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrnu32:
+;CHECK-LABEL: vqshrnu32:
;CHECK: vqshrn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -49,7 +49,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %
}
define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshruns8:
+;CHECK-LABEL: vqshruns8:
;CHECK: vqshrun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -57,7 +57,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A
}
define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshruns16:
+;CHECK-LABEL: vqshruns16:
;CHECK: vqshrun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -65,7 +65,7 @@ define <4 x i16> @vqshruns16(<4 x i32>*
}
define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshruns32:
+;CHECK-LABEL: vqshruns32:
;CHECK: vqshrun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -85,7 +85,7 @@ declare <4 x i16> @llvm.arm.neon.vqshift
declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrns8:
+;CHECK-LABEL: vqrshrns8:
;CHECK: vqrshrn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -93,7 +93,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A
}
define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrns16:
+;CHECK-LABEL: vqrshrns16:
;CHECK: vqrshrn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -101,7 +101,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>*
}
define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrns32:
+;CHECK-LABEL: vqrshrns32:
;CHECK: vqrshrn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -109,7 +109,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>*
}
define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrnu8:
+;CHECK-LABEL: vqrshrnu8:
;CHECK: vqrshrn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -117,7 +117,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A
}
define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrnu16:
+;CHECK-LABEL: vqrshrnu16:
;CHECK: vqrshrn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -125,7 +125,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>*
}
define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrnu32:
+;CHECK-LABEL: vqrshrnu32:
;CHECK: vqrshrn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -133,7 +133,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>*
}
define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshruns8:
+;CHECK-LABEL: vqrshruns8:
;CHECK: vqrshrun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -141,7 +141,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %
}
define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshruns16:
+;CHECK-LABEL: vqrshruns16:
;CHECK: vqrshrun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -149,7 +149,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>*
}
define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshruns32:
+;CHECK-LABEL: vqrshruns32:
;CHECK: vqrshrun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
Modified: llvm/trunk/test/CodeGen/ARM/vqsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqsub.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vqsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vqsub.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubs8:
+;CHECK-LABEL: vqsubs8:
;CHECK: vqsub.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <
}
define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubs16:
+;CHECK-LABEL: vqsubs16:
;CHECK: vqsub.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A
}
define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubs32:
+;CHECK-LABEL: vqsubs32:
;CHECK: vqsub.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A
}
define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubs64:
+;CHECK-LABEL: vqsubs64:
;CHECK: vqsub.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A
}
define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubu8:
+;CHECK-LABEL: vqsubu8:
;CHECK: vqsub.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <
}
define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubu16:
+;CHECK-LABEL: vqsubu16:
;CHECK: vqsub.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A
}
define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubu32:
+;CHECK-LABEL: vqsubu32:
;CHECK: vqsub.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A
}
define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubu64:
+;CHECK-LABEL: vqsubu64:
;CHECK: vqsub.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A
}
define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQs8:
+;CHECK-LABEL: vqsubQs8:
;CHECK: vqsub.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A
}
define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQs16:
+;CHECK-LABEL: vqsubQs16:
;CHECK: vqsub.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %
}
define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQs32:
+;CHECK-LABEL: vqsubQs32:
;CHECK: vqsub.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %
}
define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQs64:
+;CHECK-LABEL: vqsubQs64:
;CHECK: vqsub.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %
}
define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQu8:
+;CHECK-LABEL: vqsubQu8:
;CHECK: vqsub.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A
}
define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQu16:
+;CHECK-LABEL: vqsubQu16:
;CHECK: vqsub.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %
}
define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQu32:
+;CHECK-LABEL: vqsubQu32:
;CHECK: vqsub.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %
}
define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQu64:
+;CHECK-LABEL: vqsubQu64:
;CHECK: vqsub.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vrec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrec.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vrec.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vrec.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
-;CHECK: vrecpei32:
+;CHECK-LABEL: vrecpei32:
;CHECK: vrecpe.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
@@ -9,7 +9,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %
}
define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrecpeQi32:
+;CHECK-LABEL: vrecpeQi32:
;CHECK: vrecpe.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>*
}
define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
-;CHECK: vrecpef32:
+;CHECK-LABEL: vrecpef32:
;CHECK: vrecpe.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
@@ -25,7 +25,7 @@ define <2 x float> @vrecpef32(<2 x float
}
define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
-;CHECK: vrecpeQf32:
+;CHECK-LABEL: vrecpeQf32:
;CHECK: vrecpe.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
@@ -39,7 +39,7 @@ declare <2 x float> @llvm.arm.neon.vrecp
declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrecpsf32:
+;CHECK-LABEL: vrecpsf32:
;CHECK: vrecps.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -48,7 +48,7 @@ define <2 x float> @vrecpsf32(<2 x float
}
define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrecpsQf32:
+;CHECK-LABEL: vrecpsQf32:
;CHECK: vrecps.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -60,7 +60,7 @@ declare <2 x float> @llvm.arm.neon.vrecp
declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
-;CHECK: vrsqrtei32:
+;CHECK-LABEL: vrsqrtei32:
;CHECK: vrsqrte.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
@@ -68,7 +68,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>*
}
define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrsqrteQi32:
+;CHECK-LABEL: vrsqrteQi32:
;CHECK: vrsqrte.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
@@ -76,7 +76,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>*
}
define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
-;CHECK: vrsqrtef32:
+;CHECK-LABEL: vrsqrtef32:
;CHECK: vrsqrte.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
@@ -84,7 +84,7 @@ define <2 x float> @vrsqrtef32(<2 x floa
}
define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
-;CHECK: vrsqrteQf32:
+;CHECK-LABEL: vrsqrteQf32:
;CHECK: vrsqrte.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
@@ -98,7 +98,7 @@ declare <2 x float> @llvm.arm.neon.vrsqr
declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrsqrtsf32:
+;CHECK-LABEL: vrsqrtsf32:
;CHECK: vrsqrts.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -107,7 +107,7 @@ define <2 x float> @vrsqrtsf32(<2 x floa
}
define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrsqrtsQf32:
+;CHECK-LABEL: vrsqrtsQf32:
;CHECK: vrsqrts.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vselect_imax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vselect_imax.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vselect_imax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vselect_imax.ll Sun Jul 14 01:24:09 2013
@@ -15,7 +15,7 @@ define void @vmax_v4i32(<4 x i32>* %m, <
; lowering we also need to adjust the cost.
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
-; CHECK: func_blend10:
+; CHECK-LABEL: func_blend10:
define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
%T1_10* %blend, %T0_10* %storeaddr) {
%v0 = load %T0_10* %loadaddr
@@ -31,7 +31,7 @@ define void @func_blend10(%T0_10* %loada
}
%T0_14 = type <8 x i32>
%T1_14 = type <8 x i1>
-; CHECK: func_blend14:
+; CHECK-LABEL: func_blend14:
define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
%T1_14* %blend, %T0_14* %storeaddr) {
%v0 = load %T0_14* %loadaddr
@@ -47,7 +47,7 @@ define void @func_blend14(%T0_14* %loada
}
%T0_15 = type <16 x i32>
%T1_15 = type <16 x i1>
-; CHECK: func_blend15:
+; CHECK-LABEL: func_blend15:
define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
%T1_15* %blend, %T0_15* %storeaddr) {
; CHECK: vbsl
@@ -63,7 +63,7 @@ define void @func_blend15(%T0_15* %loada
}
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
-; CHECK: func_blend18:
+; CHECK-LABEL: func_blend18:
define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
%T1_18* %blend, %T0_18* %storeaddr) {
; CHECK: vbsl
@@ -79,7 +79,7 @@ define void @func_blend18(%T0_18* %loada
}
%T0_19 = type <8 x i64>
%T1_19 = type <8 x i1>
-; CHECK: func_blend19:
+; CHECK-LABEL: func_blend19:
define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
%T1_19* %blend, %T0_19* %storeaddr) {
; CHECK: vbsl
@@ -97,7 +97,7 @@ define void @func_blend19(%T0_19* %loada
}
%T0_20 = type <16 x i64>
%T1_20 = type <16 x i1>
-; CHECK: func_blend20:
+; CHECK-LABEL: func_blend20:
define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
%T1_20* %blend, %T0_20* %storeaddr) {
; CHECK: vbsl
Modified: llvm/trunk/test/CodeGen/ARM/vshift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshift.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vshift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vshift.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8
}
define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A,
}
define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A,
}
define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A,
}
define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -45,7 +45,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) no
}
define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
@@ -53,7 +53,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A)
}
define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
@@ -61,7 +61,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A)
}
define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
@@ -69,7 +69,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A)
}
define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A,
}
define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -87,7 +87,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A
}
define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -96,7 +96,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A
}
define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -105,7 +105,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A
}
define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -113,7 +113,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A)
}
define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
@@ -121,7 +121,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A
}
define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
@@ -129,7 +129,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A
}
define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
@@ -137,7 +137,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A
}
define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vlshru8:
+;CHECK-LABEL: vlshru8:
;CHECK: vneg.s8
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
@@ -147,7 +147,7 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <
}
define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vlshru16:
+;CHECK-LABEL: vlshru16:
;CHECK: vneg.s16
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
@@ -157,7 +157,7 @@ define <4 x i16> @vlshru16(<4 x i16>* %A
}
define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vlshru32:
+;CHECK-LABEL: vlshru32:
;CHECK: vneg.s32
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
@@ -167,7 +167,7 @@ define <2 x i32> @vlshru32(<2 x i32>* %A
}
define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vlshru64:
+;CHECK-LABEL: vlshru64:
;CHECK: vsub.i64
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
@@ -177,7 +177,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A
}
define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
-;CHECK: vlshri8:
+;CHECK-LABEL: vlshri8:
;CHECK: vshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -185,7 +185,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) n
}
define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
-;CHECK: vlshri16:
+;CHECK-LABEL: vlshri16:
;CHECK: vshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -193,7 +193,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A
}
define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
-;CHECK: vlshri32:
+;CHECK-LABEL: vlshri32:
;CHECK: vshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -201,7 +201,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A
}
define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
-;CHECK: vlshri64:
+;CHECK-LABEL: vlshri64:
;CHECK: vshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
@@ -209,7 +209,7 @@ define <1 x i64> @vlshri64(<1 x i64>* %A
}
define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vlshrQu8:
+;CHECK-LABEL: vlshrQu8:
;CHECK: vneg.s8
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
@@ -219,7 +219,7 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A
}
define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vlshrQu16:
+;CHECK-LABEL: vlshrQu16:
;CHECK: vneg.s16
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
@@ -229,7 +229,7 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %
}
define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vlshrQu32:
+;CHECK-LABEL: vlshrQu32:
;CHECK: vneg.s32
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
@@ -239,7 +239,7 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %
}
define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vlshrQu64:
+;CHECK-LABEL: vlshrQu64:
;CHECK: vsub.i64
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
@@ -249,7 +249,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %
}
define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vlshrQi8:
+;CHECK-LABEL: vlshrQi8:
;CHECK: vshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -257,7 +257,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A
}
define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vlshrQi16:
+;CHECK-LABEL: vlshrQi16:
;CHECK: vshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -265,7 +265,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %
}
define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vlshrQi32:
+;CHECK-LABEL: vlshrQi32:
;CHECK: vshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -273,7 +273,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %
}
define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vlshrQi64:
+;CHECK-LABEL: vlshrQi64:
;CHECK: vshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
@@ -288,7 +288,7 @@ entry:
}
define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vashrs8:
+;CHECK-LABEL: vashrs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
%tmp1 = load <8 x i8>* %A
@@ -298,7 +298,7 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <
}
define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vashrs16:
+;CHECK-LABEL: vashrs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
%tmp1 = load <4 x i16>* %A
@@ -308,7 +308,7 @@ define <4 x i16> @vashrs16(<4 x i16>* %A
}
define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vashrs32:
+;CHECK-LABEL: vashrs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
%tmp1 = load <2 x i32>* %A
@@ -318,7 +318,7 @@ define <2 x i32> @vashrs32(<2 x i32>* %A
}
define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vashrs64:
+;CHECK-LABEL: vashrs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
%tmp1 = load <1 x i64>* %A
@@ -328,7 +328,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A
}
define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
-;CHECK: vashri8:
+;CHECK-LABEL: vashri8:
;CHECK: vshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -336,7 +336,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) n
}
define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
-;CHECK: vashri16:
+;CHECK-LABEL: vashri16:
;CHECK: vshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -344,7 +344,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A
}
define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
-;CHECK: vashri32:
+;CHECK-LABEL: vashri32:
;CHECK: vshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -352,7 +352,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A
}
define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
-;CHECK: vashri64:
+;CHECK-LABEL: vashri64:
;CHECK: vshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
@@ -360,7 +360,7 @@ define <1 x i64> @vashri64(<1 x i64>* %A
}
define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vashrQs8:
+;CHECK-LABEL: vashrQs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
%tmp1 = load <16 x i8>* %A
@@ -370,7 +370,7 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A
}
define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vashrQs16:
+;CHECK-LABEL: vashrQs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
%tmp1 = load <8 x i16>* %A
@@ -380,7 +380,7 @@ define <8 x i16> @vashrQs16(<8 x i16>* %
}
define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vashrQs32:
+;CHECK-LABEL: vashrQs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
%tmp1 = load <4 x i32>* %A
@@ -390,7 +390,7 @@ define <4 x i32> @vashrQs32(<4 x i32>* %
}
define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vashrQs64:
+;CHECK-LABEL: vashrQs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
%tmp1 = load <2 x i64>* %A
@@ -400,7 +400,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %
}
define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vashrQi8:
+;CHECK-LABEL: vashrQi8:
;CHECK: vshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -408,7 +408,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A
}
define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vashrQi16:
+;CHECK-LABEL: vashrQi16:
;CHECK: vshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -416,7 +416,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %
}
define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vashrQi32:
+;CHECK-LABEL: vashrQi32:
;CHECK: vshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -424,7 +424,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %
}
define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vashrQi64:
+;CHECK-LABEL: vashrQi64:
;CHECK: vshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
Modified: llvm/trunk/test/CodeGen/ARM/vshiftins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshiftins.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vshiftins.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vshiftins.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsli8:
+;CHECK-LABEL: vsli8:
;CHECK: vsli.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8
}
define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsli16:
+;CHECK-LABEL: vsli16:
;CHECK: vsli.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsli16(<4 x i16>* %A,
}
define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsli32:
+;CHECK-LABEL: vsli32:
;CHECK: vsli.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsli32(<2 x i32>* %A,
}
define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsli64:
+;CHECK-LABEL: vsli64:
;CHECK: vsli.64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsli64(<1 x i64>* %A,
}
define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsliQ8:
+;CHECK-LABEL: vsliQ8:
;CHECK: vsli.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A,
}
define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsliQ16:
+;CHECK-LABEL: vsliQ16:
;CHECK: vsli.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A,
}
define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsliQ32:
+;CHECK-LABEL: vsliQ32:
;CHECK: vsli.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A,
}
define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsliQ64:
+;CHECK-LABEL: vsliQ64:
;CHECK: vsli.64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A,
}
define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsri8:
+;CHECK-LABEL: vsri8:
;CHECK: vsri.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -82,7 +82,7 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8
}
define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsri16:
+;CHECK-LABEL: vsri16:
;CHECK: vsri.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -91,7 +91,7 @@ define <4 x i16> @vsri16(<4 x i16>* %A,
}
define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsri32:
+;CHECK-LABEL: vsri32:
;CHECK: vsri.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -100,7 +100,7 @@ define <2 x i32> @vsri32(<2 x i32>* %A,
}
define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsri64:
+;CHECK-LABEL: vsri64:
;CHECK: vsri.64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -109,7 +109,7 @@ define <1 x i64> @vsri64(<1 x i64>* %A,
}
define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsriQ8:
+;CHECK-LABEL: vsriQ8:
;CHECK: vsri.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A,
}
define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsriQ16:
+;CHECK-LABEL: vsriQ16:
;CHECK: vsri.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A,
}
define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsriQ32:
+;CHECK-LABEL: vsriQ32:
;CHECK: vsri.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A,
}
define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsriQ64:
+;CHECK-LABEL: vsriQ64:
;CHECK: vsri.64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vshl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshl.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vshl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vshl.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
;CHECK: vshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8
}
define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
;CHECK: vshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A,
}
define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
;CHECK: vshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A,
}
define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
;CHECK: vshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A,
}
define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshlu8:
+;CHECK-LABEL: vshlu8:
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8
}
define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshlu16:
+;CHECK-LABEL: vshlu16:
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vshlu16(<4 x i16>* %A,
}
define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshlu32:
+;CHECK-LABEL: vshlu32:
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vshlu32(<2 x i32>* %A,
}
define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshlu64:
+;CHECK-LABEL: vshlu64:
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vshlu64(<1 x i64>* %A,
}
define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
;CHECK: vshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A,
}
define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
;CHECK: vshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A
}
define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
;CHECK: vshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A
}
define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
;CHECK: vshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A
}
define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQu8:
+;CHECK-LABEL: vshlQu8:
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A,
}
define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQu16:
+;CHECK-LABEL: vshlQu16:
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A
}
define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQu32:
+;CHECK-LABEL: vshlQu32:
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A
}
define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQu64:
+;CHECK-LABEL: vshlQu64:
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -148,7 +148,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A
; Test a mix of both signed and unsigned intrinsics.
define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -156,7 +156,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) no
}
define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -164,7 +164,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A)
}
define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -172,7 +172,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A)
}
define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -180,7 +180,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A)
}
define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -188,7 +188,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A)
}
define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -196,7 +196,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A
}
define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -204,7 +204,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A
}
define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -214,7 +214,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A
; Right shift by immediate:
define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vshrs8:
+;CHECK-LABEL: vshrs8:
;CHECK: vshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -222,7 +222,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) no
}
define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vshrs16:
+;CHECK-LABEL: vshrs16:
;CHECK: vshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -230,7 +230,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A)
}
define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vshrs32:
+;CHECK-LABEL: vshrs32:
;CHECK: vshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -238,7 +238,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A)
}
define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vshrs64:
+;CHECK-LABEL: vshrs64:
;CHECK: vshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -246,7 +246,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A)
}
define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
-;CHECK: vshru8:
+;CHECK-LABEL: vshru8:
;CHECK: vshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -254,7 +254,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) no
}
define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
-;CHECK: vshru16:
+;CHECK-LABEL: vshru16:
;CHECK: vshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -262,7 +262,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A)
}
define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
-;CHECK: vshru32:
+;CHECK-LABEL: vshru32:
;CHECK: vshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -270,7 +270,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A)
}
define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
-;CHECK: vshru64:
+;CHECK-LABEL: vshru64:
;CHECK: vshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -278,7 +278,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A)
}
define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQs8:
+;CHECK-LABEL: vshrQs8:
;CHECK: vshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -286,7 +286,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A)
}
define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQs16:
+;CHECK-LABEL: vshrQs16:
;CHECK: vshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -294,7 +294,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A
}
define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQs32:
+;CHECK-LABEL: vshrQs32:
;CHECK: vshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -302,7 +302,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A
}
define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQs64:
+;CHECK-LABEL: vshrQs64:
;CHECK: vshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -310,7 +310,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A
}
define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQu8:
+;CHECK-LABEL: vshrQu8:
;CHECK: vshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -318,7 +318,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A)
}
define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQu16:
+;CHECK-LABEL: vshrQu16:
;CHECK: vshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -326,7 +326,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A
}
define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQu32:
+;CHECK-LABEL: vshrQu32:
;CHECK: vshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -334,7 +334,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A
}
define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQu64:
+;CHECK-LABEL: vshrQu64:
;CHECK: vshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -362,7 +362,7 @@ declare <4 x i32> @llvm.arm.neon.vshiftu
declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshls8:
+;CHECK-LABEL: vrshls8:
;CHECK: vrshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <
}
define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshls16:
+;CHECK-LABEL: vrshls16:
;CHECK: vrshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -380,7 +380,7 @@ define <4 x i16> @vrshls16(<4 x i16>* %A
}
define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshls32:
+;CHECK-LABEL: vrshls32:
;CHECK: vrshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -389,7 +389,7 @@ define <2 x i32> @vrshls32(<2 x i32>* %A
}
define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshls64:
+;CHECK-LABEL: vrshls64:
;CHECK: vrshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -398,7 +398,7 @@ define <1 x i64> @vrshls64(<1 x i64>* %A
}
define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshlu8:
+;CHECK-LABEL: vrshlu8:
;CHECK: vrshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -407,7 +407,7 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <
}
define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshlu16:
+;CHECK-LABEL: vrshlu16:
;CHECK: vrshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -416,7 +416,7 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A
}
define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshlu32:
+;CHECK-LABEL: vrshlu32:
;CHECK: vrshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -425,7 +425,7 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A
}
define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshlu64:
+;CHECK-LABEL: vrshlu64:
;CHECK: vrshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -434,7 +434,7 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A
}
define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQs8:
+;CHECK-LABEL: vrshlQs8:
;CHECK: vrshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -443,7 +443,7 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A
}
define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQs16:
+;CHECK-LABEL: vrshlQs16:
;CHECK: vrshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -452,7 +452,7 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %
}
define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQs32:
+;CHECK-LABEL: vrshlQs32:
;CHECK: vrshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -461,7 +461,7 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %
}
define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQs64:
+;CHECK-LABEL: vrshlQs64:
;CHECK: vrshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -470,7 +470,7 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %
}
define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQu8:
+;CHECK-LABEL: vrshlQu8:
;CHECK: vrshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -479,7 +479,7 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A
}
define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQu16:
+;CHECK-LABEL: vrshlQu16:
;CHECK: vrshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -488,7 +488,7 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %
}
define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQu32:
+;CHECK-LABEL: vrshlQu32:
;CHECK: vrshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -497,7 +497,7 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %
}
define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQu64:
+;CHECK-LABEL: vrshlQu64:
;CHECK: vrshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -506,7 +506,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %
}
define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vrshrs8:
+;CHECK-LABEL: vrshrs8:
;CHECK: vrshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -514,7 +514,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) n
}
define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vrshrs16:
+;CHECK-LABEL: vrshrs16:
;CHECK: vrshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -522,7 +522,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A
}
define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vrshrs32:
+;CHECK-LABEL: vrshrs32:
;CHECK: vrshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -530,7 +530,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A
}
define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vrshrs64:
+;CHECK-LABEL: vrshrs64:
;CHECK: vrshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -538,7 +538,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A
}
define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
-;CHECK: vrshru8:
+;CHECK-LABEL: vrshru8:
;CHECK: vrshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -546,7 +546,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) n
}
define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
-;CHECK: vrshru16:
+;CHECK-LABEL: vrshru16:
;CHECK: vrshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -554,7 +554,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A
}
define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
-;CHECK: vrshru32:
+;CHECK-LABEL: vrshru32:
;CHECK: vrshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -562,7 +562,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A
}
define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
-;CHECK: vrshru64:
+;CHECK-LABEL: vrshru64:
;CHECK: vrshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -570,7 +570,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A
}
define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQs8:
+;CHECK-LABEL: vrshrQs8:
;CHECK: vrshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -578,7 +578,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A
}
define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQs16:
+;CHECK-LABEL: vrshrQs16:
;CHECK: vrshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -586,7 +586,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %
}
define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQs32:
+;CHECK-LABEL: vrshrQs32:
;CHECK: vrshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -594,7 +594,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %
}
define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQs64:
+;CHECK-LABEL: vrshrQs64:
;CHECK: vrshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -602,7 +602,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %
}
define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQu8:
+;CHECK-LABEL: vrshrQu8:
;CHECK: vrshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -610,7 +610,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A
}
define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQu16:
+;CHECK-LABEL: vrshrQu16:
;CHECK: vrshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -618,7 +618,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %
}
define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQu32:
+;CHECK-LABEL: vrshrQu32:
;CHECK: vrshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -626,7 +626,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %
}
define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQu64:
+;CHECK-LABEL: vrshrQu64:
;CHECK: vrshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
Modified: llvm/trunk/test/CodeGen/ARM/vshll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshll.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vshll.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vshll.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
-;CHECK: vshlls8:
+;CHECK-LABEL: vshlls8:
;CHECK: vshll.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -9,7 +9,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A)
}
define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
-;CHECK: vshlls16:
+;CHECK-LABEL: vshlls16:
;CHECK: vshll.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -17,7 +17,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A
}
define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
-;CHECK: vshlls32:
+;CHECK-LABEL: vshlls32:
;CHECK: vshll.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -25,7 +25,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A
}
define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
-;CHECK: vshllu8:
+;CHECK-LABEL: vshllu8:
;CHECK: vshll.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -33,7 +33,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A)
}
define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
-;CHECK: vshllu16:
+;CHECK-LABEL: vshllu16:
;CHECK: vshll.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -41,7 +41,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A
}
define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
-;CHECK: vshllu32:
+;CHECK-LABEL: vshllu32:
;CHECK: vshll.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -51,7 +51,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A
; The following tests use the maximum shift count, so the signedness is
; irrelevant. Test both signed and unsigned versions.
define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
-;CHECK: vshlli8:
+;CHECK-LABEL: vshlli8:
;CHECK: vshll.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
@@ -59,7 +59,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A)
}
define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
-;CHECK: vshlli16:
+;CHECK-LABEL: vshlli16:
;CHECK: vshll.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
@@ -67,7 +67,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A
}
define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
-;CHECK: vshlli32:
+;CHECK-LABEL: vshlli32:
;CHECK: vshll.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
Modified: llvm/trunk/test/CodeGen/ARM/vshrn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshrn.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vshrn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vshrn.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vshrns8:
+;CHECK-LABEL: vshrns8:
;CHECK: vshrn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A)
}
define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vshrns16:
+;CHECK-LABEL: vshrns16:
;CHECK: vshrn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A
}
define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vshrns32:
+;CHECK-LABEL: vshrns32:
;CHECK: vshrn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -29,7 +29,7 @@ declare <4 x i16> @llvm.arm.neon.vshiftn
declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vrshrns8:
+;CHECK-LABEL: vrshrns8:
;CHECK: vrshrn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -37,7 +37,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A)
}
define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vrshrns16:
+;CHECK-LABEL: vrshrns16:
;CHECK: vrshrn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -45,7 +45,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %
}
define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vrshrns32:
+;CHECK-LABEL: vrshrns32:
;CHECK: vrshrn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
Modified: llvm/trunk/test/CodeGen/ARM/vsra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsra.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vsra.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vsra.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsras8:
+;CHECK-LABEL: vsras8:
;CHECK: vsra.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8
}
define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsras16:
+;CHECK-LABEL: vsras16:
;CHECK: vsra.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vsras16(<4 x i16>* %A,
}
define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsras32:
+;CHECK-LABEL: vsras32:
;CHECK: vsra.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vsras32(<2 x i32>* %A,
}
define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsras64:
+;CHECK-LABEL: vsras64:
;CHECK: vsra.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -41,7 +41,7 @@ define <1 x i64> @vsras64(<1 x i64>* %A,
}
define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQs8:
+;CHECK-LABEL: vsraQs8:
;CHECK: vsra.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A,
}
define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQs16:
+;CHECK-LABEL: vsraQs16:
;CHECK: vsra.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A
}
define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQs32:
+;CHECK-LABEL: vsraQs32:
;CHECK: vsra.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A
}
define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQs64:
+;CHECK-LABEL: vsraQs64:
;CHECK: vsra.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -81,7 +81,7 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A
}
define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsrau8:
+;CHECK-LABEL: vsrau8:
;CHECK: vsra.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8
}
define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsrau16:
+;CHECK-LABEL: vsrau16:
;CHECK: vsra.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -101,7 +101,7 @@ define <4 x i16> @vsrau16(<4 x i16>* %A,
}
define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsrau32:
+;CHECK-LABEL: vsrau32:
;CHECK: vsra.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -111,7 +111,7 @@ define <2 x i32> @vsrau32(<2 x i32>* %A,
}
define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsrau64:
+;CHECK-LABEL: vsrau64:
;CHECK: vsra.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -121,7 +121,7 @@ define <1 x i64> @vsrau64(<1 x i64>* %A,
}
define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQu8:
+;CHECK-LABEL: vsraQu8:
;CHECK: vsra.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -131,7 +131,7 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A,
}
define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQu16:
+;CHECK-LABEL: vsraQu16:
;CHECK: vsra.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A
}
define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQu32:
+;CHECK-LABEL: vsraQu32:
;CHECK: vsra.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -151,7 +151,7 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A
}
define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQu64:
+;CHECK-LABEL: vsraQu64:
;CHECK: vsra.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -161,7 +161,7 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A
}
define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsras8:
+;CHECK-LABEL: vrsras8:
;CHECK: vrsra.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -171,7 +171,7 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <
}
define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsras16:
+;CHECK-LABEL: vrsras16:
;CHECK: vrsra.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -181,7 +181,7 @@ define <4 x i16> @vrsras16(<4 x i16>* %A
}
define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsras32:
+;CHECK-LABEL: vrsras32:
;CHECK: vrsra.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -191,7 +191,7 @@ define <2 x i32> @vrsras32(<2 x i32>* %A
}
define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsras64:
+;CHECK-LABEL: vrsras64:
;CHECK: vrsra.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -201,7 +201,7 @@ define <1 x i64> @vrsras64(<1 x i64>* %A
}
define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsrau8:
+;CHECK-LABEL: vrsrau8:
;CHECK: vrsra.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -211,7 +211,7 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <
}
define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsrau16:
+;CHECK-LABEL: vrsrau16:
;CHECK: vrsra.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -221,7 +221,7 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A
}
define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsrau32:
+;CHECK-LABEL: vrsrau32:
;CHECK: vrsra.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -231,7 +231,7 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A
}
define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsrau64:
+;CHECK-LABEL: vrsrau64:
;CHECK: vrsra.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -241,7 +241,7 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A
}
define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQs8:
+;CHECK-LABEL: vrsraQs8:
;CHECK: vrsra.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -251,7 +251,7 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A
}
define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQs16:
+;CHECK-LABEL: vrsraQs16:
;CHECK: vrsra.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -261,7 +261,7 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %
}
define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQs32:
+;CHECK-LABEL: vrsraQs32:
;CHECK: vrsra.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -271,7 +271,7 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %
}
define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQs64:
+;CHECK-LABEL: vrsraQs64:
;CHECK: vrsra.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -281,7 +281,7 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %
}
define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQu8:
+;CHECK-LABEL: vrsraQu8:
;CHECK: vrsra.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -291,7 +291,7 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A
}
define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQu16:
+;CHECK-LABEL: vrsraQu16:
;CHECK: vrsra.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -301,7 +301,7 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %
}
define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQu32:
+;CHECK-LABEL: vrsraQu32:
;CHECK: vrsra.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -311,7 +311,7 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %
}
define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQu64:
+;CHECK-LABEL: vrsraQu64:
;CHECK: vrsra.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vst1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst1.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1i8:
+;CHECK-LABEL: vst1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst1.8 {d16}, [r0:64]
%tmp1 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B
}
define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1i16:
+;CHECK-LABEL: vst1i16:
;CHECK: vst1.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define void @vst1i16(i16* %A, <4 x i16>*
}
define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1i32:
+;CHECK-LABEL: vst1i32:
;CHECK: vst1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define void @vst1i32(i32* %A, <2 x i32>*
}
define void @vst1f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1f:
+;CHECK-LABEL: vst1f:
;CHECK: vst1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define void @vst1f(float* %A, <2 x float
;Check for a post-increment updating store.
define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
-;CHECK: vst1f_update:
+;CHECK-LABEL: vst1f_update:
;CHECK: vst1.32 {d16}, [r1]!
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
@@ -50,7 +50,7 @@ define void @vst1f_update(float** %ptr,
}
define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst1i64:
+;CHECK-LABEL: vst1i64:
;CHECK: vst1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = load <1 x i64>* %B
@@ -59,7 +59,7 @@ define void @vst1i64(i64* %A, <1 x i64>*
}
define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1Qi8:
+;CHECK-LABEL: vst1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.8 {d16, d17}, [r0:64]
%tmp1 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>*
}
define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1Qi16:
+;CHECK-LABEL: vst1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -79,7 +79,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>
;Check for a post-increment updating store with register increment.
define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst1Qi16_update:
+;CHECK-LABEL: vst1Qi16_update:
;CHECK: vst1.16 {d16, d17}, [r1:64], r2
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
@@ -91,7 +91,7 @@ define void @vst1Qi16_update(i16** %ptr,
}
define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1Qi32:
+;CHECK-LABEL: vst1Qi32:
;CHECK: vst1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>
}
define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1Qf:
+;CHECK-LABEL: vst1Qf:
;CHECK: vst1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -109,7 +109,7 @@ define void @vst1Qf(float* %A, <4 x floa
}
define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
-;CHECK: vst1Qi64:
+;CHECK-LABEL: vst1Qi64:
;CHECK: vst1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = load <2 x i64>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vst2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst2.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2i8:
+;CHECK-LABEL: vst2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.8 {d16, d17}, [r0:64]
%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B
;Check for a post-increment updating store with register increment.
define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst2i8_update:
+;CHECK-LABEL: vst2i8_update:
;CHECK: vst2.8 {d16, d17}, [r1], r2
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst2i8_update(i8** %ptr, <8
}
define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2i16:
+;CHECK-LABEL: vst2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst2i16(i16* %A, <4 x i16>*
}
define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2i32:
+;CHECK-LABEL: vst2i32:
;CHECK: vst2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -41,7 +41,7 @@ define void @vst2i32(i32* %A, <2 x i32>*
}
define void @vst2f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2f:
+;CHECK-LABEL: vst2f:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -50,7 +50,7 @@ define void @vst2f(float* %A, <2 x float
}
define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64:
+;CHECK-LABEL: vst2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.64 {d16, d17}, [r0:128]
%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst2i64(i64* %A, <1 x i64>*
;Check for a post-increment updating store.
define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64_update:
+;CHECK-LABEL: vst2i64_update:
;CHECK: vst1.64 {d16, d17}, [r1:64]!
%A = load i64** %ptr
%tmp0 = bitcast i64* %A to i8*
@@ -73,7 +73,7 @@ define void @vst2i64_update(i64** %ptr,
}
define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst2Qi8:
+;CHECK-LABEL: vst2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>*
}
define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2Qi16:
+;CHECK-LABEL: vst2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -92,7 +92,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>
}
define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2Qi32:
+;CHECK-LABEL: vst2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
@@ -102,7 +102,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>
}
define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2Qf:
+;CHECK-LABEL: vst2Qf:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vst3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst3.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst3.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3i8:
+;CHECK-LABEL: vst3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -11,7 +11,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B
}
define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3i16:
+;CHECK-LABEL: vst3i16:
;CHECK: vst3.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
@@ -20,7 +20,7 @@ define void @vst3i16(i16* %A, <4 x i16>*
}
define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32:
+;CHECK-LABEL: vst3i32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -30,7 +30,7 @@ define void @vst3i32(i32* %A, <2 x i32>*
;Check for a post-increment updating store.
define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32_update:
+;CHECK-LABEL: vst3i32_update:
;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst3i32_update(i32** %ptr,
}
define void @vst3f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3f:
+;CHECK-LABEL: vst3f:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst3f(float* %A, <2 x float
}
define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst3i64:
+;CHECK-LABEL: vst3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -62,7 +62,7 @@ define void @vst3i64(i64* %A, <1 x i64>*
}
define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst3Qi8:
+;CHECK-LABEL: vst3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
@@ -73,7 +73,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>*
}
define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16:
+;CHECK-LABEL: vst3Qi16:
;CHECK: vst3.16
;CHECK: vst3.16
%tmp0 = bitcast i16* %A to i8*
@@ -84,7 +84,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>
;Check for a post-increment updating store.
define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16_update:
+;CHECK-LABEL: vst3Qi16_update:
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
%A = load i16** %ptr
@@ -97,7 +97,7 @@ define void @vst3Qi16_update(i16** %ptr,
}
define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3Qi32:
+;CHECK-LABEL: vst3Qi32:
;CHECK: vst3.32
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
@@ -107,7 +107,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>
}
define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3Qf:
+;CHECK-LABEL: vst3Qf:
;CHECK: vst3.32
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
Modified: llvm/trunk/test/CodeGen/ARM/vst4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst4.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst4.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4i8:
+;CHECK-LABEL: vst4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B
;Check for a post-increment updating store with register increment.
define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst4i8_update:
+;CHECK-LABEL: vst4i8_update:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst4i8_update(i8** %ptr, <8
}
define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4i16:
+;CHECK-LABEL: vst4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst4i16(i16* %A, <4 x i16>*
}
define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4i32:
+;CHECK-LABEL: vst4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst4i32(i32* %A, <2 x i32>*
}
define void @vst4f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4f:
+;CHECK-LABEL: vst4f:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst4f(float* %A, <2 x float
}
define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst4i64:
+;CHECK-LABEL: vst4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst4i64(i64* %A, <1 x i64>*
}
define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst4Qi8:
+;CHECK-LABEL: vst4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
@@ -71,7 +71,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>*
}
define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4Qi16:
+;CHECK-LABEL: vst4Qi16:
;Check for no alignment specifier.
;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
@@ -82,7 +82,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>
}
define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4Qi32:
+;CHECK-LABEL: vst4Qi32:
;CHECK: vst4.32
;CHECK: vst4.32
%tmp0 = bitcast i32* %A to i8*
@@ -92,7 +92,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>
}
define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf:
+;CHECK-LABEL: vst4Qf:
;CHECK: vst4.32
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
@@ -103,7 +103,7 @@ define void @vst4Qf(float* %A, <4 x floa
;Check for a post-increment updating store.
define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf_update:
+;CHECK-LABEL: vst4Qf_update:
;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]!
;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]!
%A = load float** %ptr
Modified: llvm/trunk/test/CodeGen/ARM/vstlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vstlane.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vstlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vstlane.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8:
+;CHECK-LABEL: vst1lanei8:
;Check the (default) alignment.
;CHECK: vst1.8 {d16[3]}, [r0]
%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>
;Check for a post-increment updating store.
define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8_update:
+;CHECK-LABEL: vst1lanei8_update:
;CHECK: vst1.8 {d16[3]}, [r2]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
@@ -24,7 +24,7 @@ define void @vst1lanei8_update(i8** %ptr
}
define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1lanei16:
+;CHECK-LABEL: vst1lanei16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vst1.16 {d16[2]}, [r0:16]
%tmp1 = load <4 x i16>* %B
@@ -34,7 +34,7 @@ define void @vst1lanei16(i16* %A, <4 x i
}
define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1lanei32:
+;CHECK-LABEL: vst1lanei32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
@@ -44,7 +44,7 @@ define void @vst1lanei32(i32* %A, <2 x i
}
define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1lanef:
+;CHECK-LABEL: vst1lanef:
;CHECK: vst1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x float>* %B
%tmp2 = extractelement <2 x float> %tmp1, i32 1
@@ -53,7 +53,7 @@ define void @vst1lanef(float* %A, <2 x f
}
define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1laneQi8:
+;CHECK-LABEL: vst1laneQi8:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.8 {d17[1]}, [r0]
%tmp1 = load <16 x i8>* %B
@@ -63,7 +63,7 @@ define void @vst1laneQi8(i8* %A, <16 x i
}
define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1laneQi16:
+;CHECK-LABEL: vst1laneQi16:
;CHECK: vst1.16 {d17[1]}, [r0:16]
%tmp1 = load <8 x i16>* %B
%tmp2 = extractelement <8 x i16> %tmp1, i32 5
@@ -72,7 +72,7 @@ define void @vst1laneQi16(i16* %A, <8 x
}
define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32:
+;CHECK-LABEL: vst1laneQi32:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
%tmp1 = load <4 x i32>* %B
@@ -83,7 +83,7 @@ define void @vst1laneQi32(i32* %A, <4 x
;Check for a post-increment updating store.
define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32_update:
+;CHECK-LABEL: vst1laneQi32_update:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
%A = load i32** %ptr
@@ -96,7 +96,7 @@ define void @vst1laneQi32_update(i32** %
}
define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1laneQf:
+;CHECK-LABEL: vst1laneQf:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0]
%tmp1 = load <4 x float>* %B
@@ -106,7 +106,7 @@ define void @vst1laneQf(float* %A, <4 x
}
define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2lanei8:
+;CHECK-LABEL: vst2lanei8:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
%tmp1 = load <8 x i8>* %B
@@ -115,7 +115,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>
}
define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2lanei16:
+;CHECK-LABEL: vst2lanei16:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
%tmp0 = bitcast i16* %A to i8*
@@ -126,7 +126,7 @@ define void @vst2lanei16(i16* %A, <4 x i
;Check for a post-increment updating store with register increment.
define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst2lanei16_update:
+;CHECK-LABEL: vst2lanei16_update:
;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
@@ -138,7 +138,7 @@ define void @vst2lanei16_update(i16** %p
}
define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2lanei32:
+;CHECK-LABEL: vst2lanei32:
;CHECK: vst2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -147,7 +147,7 @@ define void @vst2lanei32(i32* %A, <2 x i
}
define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2lanef:
+;CHECK-LABEL: vst2lanef:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -156,7 +156,7 @@ define void @vst2lanef(float* %A, <2 x f
}
define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2laneQi16:
+;CHECK-LABEL: vst2laneQi16:
;Check the (default) alignment.
;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
%tmp0 = bitcast i16* %A to i8*
@@ -166,7 +166,7 @@ define void @vst2laneQi16(i16* %A, <8 x
}
define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2laneQi32:
+;CHECK-LABEL: vst2laneQi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
%tmp0 = bitcast i32* %A to i8*
@@ -176,7 +176,7 @@ define void @vst2laneQi32(i32* %A, <4 x
}
define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2laneQf:
+;CHECK-LABEL: vst2laneQf:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -194,7 +194,7 @@ declare void @llvm.arm.neon.vst2lane.v4i
declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3lanei8:
+;CHECK-LABEL: vst3lanei8:
;CHECK: vst3.8
%tmp1 = load <8 x i8>* %B
call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -202,7 +202,7 @@ define void @vst3lanei8(i8* %A, <8 x i8>
}
define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3lanei16:
+;CHECK-LABEL: vst3lanei16:
;Check the (default) alignment value. VST3 does not support alignment.
;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
%tmp0 = bitcast i16* %A to i8*
@@ -212,7 +212,7 @@ define void @vst3lanei16(i16* %A, <4 x i
}
define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3lanei32:
+;CHECK-LABEL: vst3lanei32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
@@ -221,7 +221,7 @@ define void @vst3lanei32(i32* %A, <2 x i
}
define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3lanef:
+;CHECK-LABEL: vst3lanef:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -230,7 +230,7 @@ define void @vst3lanef(float* %A, <2 x f
}
define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3laneQi16:
+;CHECK-LABEL: vst3laneQi16:
;Check the (default) alignment value. VST3 does not support alignment.
;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
%tmp0 = bitcast i16* %A to i8*
@@ -240,7 +240,7 @@ define void @vst3laneQi16(i16* %A, <8 x
}
define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32:
+;CHECK-LABEL: vst3laneQi32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
@@ -250,7 +250,7 @@ define void @vst3laneQi32(i32* %A, <4 x
;Check for a post-increment updating store.
define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32_update:
+;CHECK-LABEL: vst3laneQi32_update:
;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
@@ -262,7 +262,7 @@ define void @vst3laneQi32_update(i32** %
}
define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3laneQf:
+;CHECK-LABEL: vst3laneQf:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -281,7 +281,7 @@ declare void @llvm.arm.neon.vst3lane.v4f
define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8:
+;CHECK-LABEL: vst4lanei8:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
%tmp1 = load <8 x i8>* %B
@@ -291,7 +291,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>
;Check for a post-increment updating store.
define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8_update:
+;CHECK-LABEL: vst4lanei8_update:
;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
@@ -302,7 +302,7 @@ define void @vst4lanei8_update(i8** %ptr
}
define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4lanei16:
+;CHECK-LABEL: vst4lanei16:
;CHECK: vst4.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
@@ -311,7 +311,7 @@ define void @vst4lanei16(i16* %A, <4 x i
}
define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4lanei32:
+;CHECK-LABEL: vst4lanei32:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
%tmp0 = bitcast i32* %A to i8*
@@ -321,7 +321,7 @@ define void @vst4lanei32(i32* %A, <2 x i
}
define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4lanef:
+;CHECK-LABEL: vst4lanef:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
@@ -330,7 +330,7 @@ define void @vst4lanef(float* %A, <2 x f
}
define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4laneQi16:
+;CHECK-LABEL: vst4laneQi16:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
%tmp0 = bitcast i16* %A to i8*
@@ -340,7 +340,7 @@ define void @vst4laneQi16(i16* %A, <8 x
}
define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4laneQi32:
+;CHECK-LABEL: vst4laneQi32:
;Check the (default) alignment.
;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
%tmp0 = bitcast i32* %A to i8*
@@ -350,7 +350,7 @@ define void @vst4laneQi32(i32* %A, <4 x
}
define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4laneQf:
+;CHECK-LABEL: vst4laneQf:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
@@ -360,7 +360,7 @@ define void @vst4laneQf(float* %A, <4 x
; Make sure this doesn't crash; PR10258
define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
-;CHECK: variable_insertelement:
+;CHECK-LABEL: variable_insertelement:
%r = insertelement <8 x i16> %a, i16 %b, i32 %c
ret <8 x i16> %r
}
Modified: llvm/trunk/test/CodeGen/ARM/vsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsub.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vsub.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubi8:
+;CHECK-LABEL: vsubi8:
;CHECK: vsub.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8
}
define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubi16:
+;CHECK-LABEL: vsubi16:
;CHECK: vsub.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsubi16(<4 x i16>* %A,
}
define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubi32:
+;CHECK-LABEL: vsubi32:
;CHECK: vsub.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsubi32(<2 x i32>* %A,
}
define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsubi64:
+;CHECK-LABEL: vsubi64:
;CHECK: vsub.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsubi64(<1 x i64>* %A,
}
define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vsubf32:
+;CHECK-LABEL: vsubf32:
;CHECK: vsub.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vsubf32(<2 x float>*
}
define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsubQi8:
+;CHECK-LABEL: vsubQi8:
;CHECK: vsub.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A,
}
define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubQi16:
+;CHECK-LABEL: vsubQi16:
;CHECK: vsub.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A
}
define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubQi32:
+;CHECK-LABEL: vsubQi32:
;CHECK: vsub.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A
}
define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubQi64:
+;CHECK-LABEL: vsubQi64:
;CHECK: vsub.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A
}
define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vsubQf32:
+;CHECK-LABEL: vsubQf32:
;CHECK: vsub.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vsubQf32(<4 x float>
}
define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubhni16:
+;CHECK-LABEL: vsubhni16:
;CHECK: vsubhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vsubhni16(<8 x i16>* %A
}
define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubhni32:
+;CHECK-LABEL: vsubhni32:
;CHECK: vsubhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vsubhni32(<4 x i32>* %
}
define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubhni64:
+;CHECK-LABEL: vsubhni64:
;CHECK: vsubhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vsubhn.
declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsubhni16:
+;CHECK-LABEL: vrsubhni16:
;CHECK: vrsubhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %
}
define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsubhni32:
+;CHECK-LABEL: vrsubhni32:
;CHECK: vrsubhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vrsubhni32(<4 x i32>*
}
define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsubhni64:
+;CHECK-LABEL: vrsubhni64:
;CHECK: vrsubhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vrsubhn
declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubls8:
+;CHECK-LABEL: vsubls8:
;CHECK: vsubl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vsubls8(<8 x i8>* %A,
}
define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubls16:
+;CHECK-LABEL: vsubls16:
;CHECK: vsubl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vsubls16(<4 x i16>* %A
}
define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubls32:
+;CHECK-LABEL: vsubls32:
;CHECK: vsubl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vsubls32(<2 x i32>* %A
}
define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsublu8:
+;CHECK-LABEL: vsublu8:
;CHECK: vsubl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vsublu8(<8 x i8>* %A,
}
define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsublu16:
+;CHECK-LABEL: vsublu16:
;CHECK: vsubl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vsublu16(<4 x i16>* %A
}
define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsublu32:
+;CHECK-LABEL: vsublu32:
;CHECK: vsubl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vsublu32(<2 x i32>* %A
}
define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubws8:
+;CHECK-LABEL: vsubws8:
;CHECK: vsubw.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vsubws8(<8 x i16>* %A,
}
define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubws16:
+;CHECK-LABEL: vsubws16:
;CHECK: vsubw.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vsubws16(<4 x i32>* %A
}
define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubws32:
+;CHECK-LABEL: vsubws32:
;CHECK: vsubw.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vsubws32(<2 x i64>* %A
}
define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubwu8:
+;CHECK-LABEL: vsubwu8:
;CHECK: vsubw.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A,
}
define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubwu16:
+;CHECK-LABEL: vsubwu16:
;CHECK: vsubw.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A
}
define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubwu32:
+;CHECK-LABEL: vsubwu32:
;CHECK: vsubw.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
Modified: llvm/trunk/test/CodeGen/ARM/vtbl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vtbl.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vtbl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vtbl.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtbl1:
+;CHECK-LABEL: vtbl1:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -14,7 +14,7 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8
}
define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
-;CHECK: vtbl2:
+;CHECK-LABEL: vtbl2:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -25,7 +25,7 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %st
}
define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
-;CHECK: vtbl3:
+;CHECK-LABEL: vtbl3:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %st
}
define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
-;CHECK: vtbl4:
+;CHECK-LABEL: vtbl4:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t* %B
@@ -50,7 +50,7 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %st
}
define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx1:
+;CHECK-LABEL: vtbx1:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -60,7 +60,7 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8
}
define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx2:
+;CHECK-LABEL: vtbx2:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -72,7 +72,7 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %st
}
define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx3:
+;CHECK-LABEL: vtbx3:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -85,7 +85,7 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %st
}
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx4:
+;CHECK-LABEL: vtbx4:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t* %B
Modified: llvm/trunk/test/CodeGen/ARM/vtrn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vtrn.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vtrn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vtrn.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8:
+;CHECK-LABEL: vtrni8:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8
}
define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtrni16:
+;CHECK-LABEL: vtrni16:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
@@ -25,7 +25,7 @@ define <4 x i16> @vtrni16(<4 x i16>* %A,
}
define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtrni32:
+;CHECK-LABEL: vtrni32:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <2 x i32>* %A
@@ -37,7 +37,7 @@ define <2 x i32> @vtrni32(<2 x i32>* %A,
}
define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vtrnf:
+;CHECK-LABEL: vtrnf:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <2 x float>* %A
@@ -49,7 +49,7 @@ define <2 x float> @vtrnf(<2 x float>* %
}
define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtrnQi8:
+;CHECK-LABEL: vtrnQi8:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
@@ -61,7 +61,7 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A,
}
define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16:
+;CHECK-LABEL: vtrnQi16:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
@@ -73,7 +73,7 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A
}
define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtrnQi32:
+;CHECK-LABEL: vtrnQi32:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
@@ -85,7 +85,7 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A
}
define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vtrnQf:
+;CHECK-LABEL: vtrnQf:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
@@ -99,7 +99,7 @@ define <4 x float> @vtrnQf(<4 x float>*
; Undef shuffle indices should not prevent matching to VTRN:
define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8_undef:
+;CHECK-LABEL: vtrni8_undef:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -111,7 +111,7 @@ define <8 x i8> @vtrni8_undef(<8 x i8>*
}
define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16_undef:
+;CHECK-LABEL: vtrnQi16_undef:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
Modified: llvm/trunk/test/CodeGen/ARM/vuzp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vuzp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vuzp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vuzp.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8:
+;CHECK-LABEL: vuzpi8:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8
}
define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vuzpi16:
+;CHECK-LABEL: vuzpi16:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A,
; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vuzpQi8:
+;CHECK-LABEL: vuzpQi8:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A,
}
define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16:
+;CHECK-LABEL: vuzpQi16:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A
}
define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vuzpQi32:
+;CHECK-LABEL: vuzpQi32:
;CHECK: vuzp.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A
}
define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vuzpQf:
+;CHECK-LABEL: vuzpQf:
;CHECK: vuzp.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vuzpQf(<4 x float>*
; Undef shuffle indices should not prevent matching to VUZP:
define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8_undef:
+;CHECK-LABEL: vuzpi8_undef:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>*
}
define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16_undef:
+;CHECK-LABEL: vuzpQi16_undef:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
Modified: llvm/trunk/test/CodeGen/ARM/vzip.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vzip.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vzip.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vzip.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8:
+;CHECK-LABEL: vzipi8:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8
}
define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vzipi16:
+;CHECK-LABEL: vzipi16:
;CHECK: vzip.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vzipi16(<4 x i16>* %A,
; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8:
+;CHECK-LABEL: vzipQi8:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A,
}
define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vzipQi16:
+;CHECK-LABEL: vzipQi16:
;CHECK: vzip.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A
}
define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vzipQi32:
+;CHECK-LABEL: vzipQi32:
;CHECK: vzip.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A
}
define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vzipQf:
+;CHECK-LABEL: vzipQf:
;CHECK: vzip.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vzipQf(<4 x float>*
; Undef shuffle indices should not prevent matching to VZIP:
define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8_undef:
+;CHECK-LABEL: vzipi8_undef:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vzipi8_undef(<8 x i8>*
}
define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8_undef:
+;CHECK-LABEL: vzipQi8_undef:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
Modified: llvm/trunk/test/CodeGen/MBlaze/brind.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/brind.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/brind.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/brind.ll Sun Jul 14 01:24:09 2013
@@ -15,7 +15,7 @@ declare i32 @printf(i8*, ...)
define i32 @brind(i32 %a, i32 %b)
{
- ; CHECK: brind:
+ ; CHECK-LABEL: brind:
entry:
br label %loop
Modified: llvm/trunk/test/CodeGen/MBlaze/callind.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/callind.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/callind.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/callind.ll Sun Jul 14 01:24:09 2013
@@ -15,7 +15,7 @@ declare i32 @printf(i8*, ...)
define i32 @doadd(i32 %a, i32 %b)
{
- ; CHECK: doadd:
+ ; CHECK-LABEL: doadd:
%tmp.0 = add i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
@@ -23,7 +23,7 @@ define i32 @doadd(i32 %a, i32 %b)
define i32 @dosub(i32 %a, i32 %b)
{
- ; CHECK: dosub:
+ ; CHECK-LABEL: dosub:
%tmp.0 = sub i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
@@ -31,7 +31,7 @@ define i32 @dosub(i32 %a, i32 %b)
define i32 @domul(i32 %a, i32 %b)
{
- ; CHECK: domul:
+ ; CHECK-LABEL: domul:
%tmp.0 = mul i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
@@ -39,7 +39,7 @@ define i32 @domul(i32 %a, i32 %b)
define i32 @dodiv(i32 %a, i32 %b)
{
- ; CHECK: dodiv:
+ ; CHECK-LABEL: dodiv:
%tmp.0 = sdiv i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
@@ -47,7 +47,7 @@ define i32 @dodiv(i32 %a, i32 %b)
define i32 @dorem(i32 %a, i32 %b)
{
- ; CHECK: dorem:
+ ; CHECK-LABEL: dorem:
%tmp.0 = srem i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
@@ -55,7 +55,7 @@ define i32 @dorem(i32 %a, i32 %b)
define i32 @callind(i32 %a, i32 %b)
{
- ; CHECK: callind:
+ ; CHECK-LABEL: callind:
entry:
br label %loop
Modified: llvm/trunk/test/CodeGen/MBlaze/cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/cc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/cc.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/cc.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@ declare i32 @printf(i8*, ...)
@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
define void @params0_noret() {
- ; CHECK: params0_noret:
+ ; CHECK-LABEL: params0_noret:
ret void
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -18,7 +18,7 @@ define void @params0_noret() {
}
define i8 @params0_8bitret() {
- ; CHECK: params0_8bitret:
+ ; CHECK-LABEL: params0_8bitret:
ret i8 1
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -27,7 +27,7 @@ define i8 @params0_8bitret() {
}
define i16 @params0_16bitret() {
- ; CHECK: params0_16bitret:
+ ; CHECK-LABEL: params0_16bitret:
ret i16 1
; CHECK: rtsd
; CHECK: {{.* r3, r0, 1}}
@@ -35,7 +35,7 @@ define i16 @params0_16bitret() {
}
define i32 @params0_32bitret() {
- ; CHECK: params0_32bitret:
+ ; CHECK-LABEL: params0_32bitret:
ret i32 1
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
@@ -43,7 +43,7 @@ define i32 @params0_32bitret() {
}
define i64 @params0_64bitret() {
- ; CHECK: params0_64bitret:
+ ; CHECK-LABEL: params0_64bitret:
ret i64 1
; CHECK: {{.* r3, r0, .*}}
; CHECK: rtsd
@@ -51,7 +51,7 @@ define i64 @params0_64bitret() {
}
define i32 @params1_32bitret(i32 %a) {
- ; CHECK: params1_32bitret:
+ ; CHECK-LABEL: params1_32bitret:
ret i32 %a
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -60,7 +60,7 @@ define i32 @params1_32bitret(i32 %a) {
}
define i32 @params2_32bitret(i32 %a, i32 %b) {
- ; CHECK: params2_32bitret:
+ ; CHECK-LABEL: params2_32bitret:
ret i32 %b
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -69,7 +69,7 @@ define i32 @params2_32bitret(i32 %a, i32
}
define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
- ; CHECK: params3_32bitret:
+ ; CHECK-LABEL: params3_32bitret:
ret i32 %c
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -78,7 +78,7 @@ define i32 @params3_32bitret(i32 %a, i32
}
define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
- ; CHECK: params4_32bitret:
+ ; CHECK-LABEL: params4_32bitret:
ret i32 %d
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -87,7 +87,7 @@ define i32 @params4_32bitret(i32 %a, i32
}
define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
- ; CHECK: params5_32bitret:
+ ; CHECK-LABEL: params5_32bitret:
ret i32 %e
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -96,7 +96,7 @@ define i32 @params5_32bitret(i32 %a, i32
}
define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
- ; CHECK: params6_32bitret:
+ ; CHECK-LABEL: params6_32bitret:
ret i32 %f
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -106,7 +106,7 @@ define i32 @params6_32bitret(i32 %a, i32
define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g) {
- ; CHECK: params7_32bitret:
+ ; CHECK-LABEL: params7_32bitret:
ret i32 %g
; CHECK: {{lwi? r3, r1, 32}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -115,7 +115,7 @@ define i32 @params7_32bitret(i32 %a, i32
define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h) {
- ; CHECK: params8_32bitret:
+ ; CHECK-LABEL: params8_32bitret:
ret i32 %h
; CHECK: {{lwi? r3, r1, 36}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -124,7 +124,7 @@ define i32 @params8_32bitret(i32 %a, i32
define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i) {
- ; CHECK: params9_32bitret:
+ ; CHECK-LABEL: params9_32bitret:
ret i32 %i
; CHECK: {{lwi? r3, r1, 40}}
; CHECK-NOT: {{.* r4, .*, .*}}
@@ -133,7 +133,7 @@ define i32 @params9_32bitret(i32 %a, i32
define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i, i32 %j) {
- ; CHECK: params10_32bitret:
+ ; CHECK-LABEL: params10_32bitret:
ret i32 %j
; CHECK: {{lwi? r3, r1, 44}}
; CHECK-NOT: {{.* r4, .*, .*}}
Modified: llvm/trunk/test/CodeGen/MBlaze/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/div.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/div.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/div.ll Sun Jul 14 01:24:09 2013
@@ -6,8 +6,8 @@
; RUN: llc < %s -march=mblaze -mattr=+div | FileCheck -check-prefix=DIV %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; DIV: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; DIV-LABEL: test_i8:
%tmp.1 = udiv i8 %a, %b
; FUN-NOT: idiv
@@ -29,8 +29,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; DIV: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; DIV-LABEL: test_i16:
%tmp.1 = udiv i16 %a, %b
; FUN-NOT: idiv
@@ -52,8 +52,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; DIV: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; DIV-LABEL: test_i32:
%tmp.1 = udiv i32 %a, %b
; FUN-NOT: idiv
Modified: llvm/trunk/test/CodeGen/MBlaze/fpu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/fpu.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/fpu.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/fpu.ll Sun Jul 14 01:24:09 2013
@@ -6,8 +6,8 @@
; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
define float @test_add(float %a, float %b) {
- ; FUN: test_add:
- ; FPU: test_add:
+ ; FUN-LABEL: test_add:
+ ; FPU-LABEL: test_add:
%tmp.1 = fadd float %a, %b
; FUN: brlid
@@ -21,8 +21,8 @@ define float @test_add(float %a, float %
}
define float @test_sub(float %a, float %b) {
- ; FUN: test_sub:
- ; FPU: test_sub:
+ ; FUN-LABEL: test_sub:
+ ; FPU-LABEL: test_sub:
%tmp.1 = fsub float %a, %b
; FUN: brlid
@@ -36,8 +36,8 @@ define float @test_sub(float %a, float %
}
define float @test_mul(float %a, float %b) {
- ; FUN: test_mul:
- ; FPU: test_mul:
+ ; FUN-LABEL: test_mul:
+ ; FPU-LABEL: test_mul:
%tmp.1 = fmul float %a, %b
; FUN: brlid
@@ -51,8 +51,8 @@ define float @test_mul(float %a, float %
}
define float @test_div(float %a, float %b) {
- ; FUN: test_div:
- ; FPU: test_div:
+ ; FUN-LABEL: test_div:
+ ; FPU-LABEL: test_div:
%tmp.1 = fdiv float %a, %b
; FUN: brlid
Modified: llvm/trunk/test/CodeGen/MBlaze/fsl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/fsl.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/fsl.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/fsl.ll Sun Jul 14 01:24:09 2013
@@ -56,7 +56,7 @@ declare void @llvm.mblaze.fsl.tncput(i32
declare void @llvm.mblaze.fsl.tncaput(i32 %port)
define void @fsl_get(i32 %port) {
- ; CHECK: fsl_get:
+ ; CHECK-LABEL: fsl_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 %port)
; CHECK: getd
%v1 = call i32 @llvm.mblaze.fsl.aget(i32 %port)
@@ -126,7 +126,7 @@ define void @fsl_get(i32 %port) {
}
define void @fslc_get() {
- ; CHECK: fslc_get:
+ ; CHECK-LABEL: fslc_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 1)
; CHECK: get
%v1 = call i32 @llvm.mblaze.fsl.aget(i32 1)
@@ -227,7 +227,7 @@ define void @fslc_get() {
}
define void @putfsl(i32 %value, i32 %port) {
- ; CHECK: putfsl:
+ ; CHECK-LABEL: putfsl:
call void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
; CHECK: putd
call void @llvm.mblaze.fsl.aput(i32 %value, i32 %port)
@@ -265,7 +265,7 @@ define void @putfsl(i32 %value, i32 %por
}
define void @putfsl_const(i32 %value) {
- ; CHECK: putfsl_const:
+ ; CHECK-LABEL: putfsl_const:
call void @llvm.mblaze.fsl.put(i32 %value, i32 1)
; CHECK-NOT: putd
; CHECK: put
Modified: llvm/trunk/test/CodeGen/MBlaze/imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/imm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/imm.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/imm.ll Sun Jul 14 01:24:09 2013
@@ -6,41 +6,41 @@
; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
define i8 @retimm_i8() {
- ; CHECK: retimm_i8:
+ ; CHECK-LABEL: retimm_i8:
; CHECK: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i8:
+ ; FPU-LABEL: retimm_i8:
; FPU: rtsd
; FPU-NEXT: add
ret i8 123
}
define i16 @retimm_i16() {
- ; CHECK: retimm_i16:
+ ; CHECK-LABEL: retimm_i16:
; CHECK: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i16:
+ ; FPU-LABEL: retimm_i16:
; FPU: rtsd
; FPU-NEXT: add
ret i16 31212
}
define i32 @retimm_i32() {
- ; CHECK: retimm_i32:
+ ; CHECK-LABEL: retimm_i32:
; CHECK: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_i32:
+ ; FPU-LABEL: retimm_i32:
; FPU: add
; FPU-NEXT: rtsd
ret i32 2938128
}
define i64 @retimm_i64() {
- ; CHECK: retimm_i64:
+ ; CHECK-LABEL: retimm_i64:
; CHECK: add
; CHECK-NEXT: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i64:
+ ; FPU-LABEL: retimm_i64:
; FPU: add
; FPU-NEXT: rtsd
; FPU-NEXT: add
@@ -48,21 +48,21 @@ define i64 @retimm_i64() {
}
define float @retimm_float() {
- ; CHECK: retimm_float:
+ ; CHECK-LABEL: retimm_float:
; CHECK: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_float:
+ ; FPU-LABEL: retimm_float:
; FPU: or
; FPU-NEXT: rtsd
ret float 12.0
}
define double @retimm_double() {
- ; CHECK: retimm_double:
+ ; CHECK-LABEL: retimm_double:
; CHECK: add
; CHECK-NEXT: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_double:
+ ; FPU-LABEL: retimm_double:
; FPU: add
; FPU-NEXT: add
; FPU-NEXT: rtsd
Modified: llvm/trunk/test/CodeGen/MBlaze/intr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/intr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/intr.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/intr.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
@_interrupt_handler = alias void ()* @myintr
define cc73 void @myintr() nounwind noinline {
- ; CHECK: myintr:
+ ; CHECK-LABEL: myintr:
; CHECK: swi r3, r1
; CHECK: swi r4, r1
; CHECK: swi r5, r1
Modified: llvm/trunk/test/CodeGen/MBlaze/jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/jumptable.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/jumptable.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/jumptable.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
define i32 @jmptable(i32 %arg)
{
- ; CHECK: jmptable:
+ ; CHECK-LABEL: jmptable:
switch i32 %arg, label %DEFAULT [ i32 0, label %L0
i32 1, label %L1
i32 2, label %L2
Modified: llvm/trunk/test/CodeGen/MBlaze/loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/loop.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/loop.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/loop.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@ declare i32 @printf(i8*, ...)
define i32 @loop(i32 %a, i32 %b)
{
- ; CHECK: loop:
+ ; CHECK-LABEL: loop:
entry:
br label %loop_outer
Modified: llvm/trunk/test/CodeGen/MBlaze/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/mul.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/mul.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/mul.ll Sun Jul 14 01:24:09 2013
@@ -6,8 +6,8 @@
; RUN: llc < %s -march=mblaze -mattr=+mul | FileCheck -check-prefix=MUL %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; MUL: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; MUL-LABEL: test_i8:
%tmp.1 = mul i8 %a, %b
; FUN-NOT: mul
@@ -21,8 +21,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; MUL: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; MUL-LABEL: test_i16:
%tmp.1 = mul i16 %a, %b
; FUN-NOT: mul
@@ -36,8 +36,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; MUL: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; MUL-LABEL: test_i32:
%tmp.1 = mul i32 %a, %b
; FUN-NOT: mul
Modified: llvm/trunk/test/CodeGen/MBlaze/mul64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/mul64.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/mul64.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/mul64.ll Sun Jul 14 01:24:09 2013
@@ -7,8 +7,8 @@
; RUN: FileCheck -check-prefix=MUL %s
define i64 @test_i64(i64 %a, i64 %b) {
- ; FUN: test_i64:
- ; MUL: test_i64:
+ ; FUN-LABEL: test_i64:
+ ; MUL-LABEL: test_i64:
%tmp.1 = mul i64 %a, %b
; FUN-NOT: mul
Modified: llvm/trunk/test/CodeGen/MBlaze/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/select.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/select.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/select.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
define i32 @testsel(i32 %a, i32 %b)
{
- ; CHECK: testsel:
+ ; CHECK-LABEL: testsel:
%tmp.1 = icmp eq i32 %a, %b
; CHECK: cmp
%tmp.2 = select i1 %tmp.1, i32 %a, i32 %b
Modified: llvm/trunk/test/CodeGen/MBlaze/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/shift.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/shift.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/shift.ll Sun Jul 14 01:24:09 2013
@@ -6,8 +6,8 @@
; RUN: llc < %s -march=mblaze -mattr=+barrel | FileCheck -check-prefix=SHT %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; SHT: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; SHT-LABEL: test_i8:
%tmp.1 = shl i8 %a, %b
; FUN: andi
@@ -23,8 +23,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
}
define i8 @testc_i8(i8 %a, i8 %b) {
- ; FUN: testc_i8:
- ; SHT: testc_i8:
+ ; FUN-LABEL: testc_i8:
+ ; SHT-LABEL: testc_i8:
%tmp.1 = shl i8 %a, 5
; FUN: andi
@@ -42,8 +42,8 @@ define i8 @testc_i8(i8 %a, i8 %b) {
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; SHT: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; SHT-LABEL: test_i16:
%tmp.1 = shl i16 %a, %b
; FUN: andi
@@ -59,8 +59,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
}
define i16 @testc_i16(i16 %a, i16 %b) {
- ; FUN: testc_i16:
- ; SHT: testc_i16:
+ ; FUN-LABEL: testc_i16:
+ ; SHT-LABEL: testc_i16:
%tmp.1 = shl i16 %a, 5
; FUN: andi
@@ -78,8 +78,8 @@ define i16 @testc_i16(i16 %a, i16 %b) {
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; SHT: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; SHT-LABEL: test_i32:
%tmp.1 = shl i32 %a, %b
; FUN: andi
@@ -96,8 +96,8 @@ define i32 @test_i32(i32 %a, i32 %b) {
}
define i32 @testc_i32(i32 %a, i32 %b) {
- ; FUN: testc_i32:
- ; SHT: testc_i32:
+ ; FUN-LABEL: testc_i32:
+ ; SHT-LABEL: testc_i32:
%tmp.1 = shl i32 %a, 5
; FUN: andi
Modified: llvm/trunk/test/CodeGen/MBlaze/svol.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/svol.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/svol.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/svol.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
define cc74 void @mysvol() nounwind noinline {
- ; CHECK: mysvol:
+ ; CHECK-LABEL: mysvol:
; CHECK: swi r3, r1
; CHECK: swi r4, r1
; CHECK: swi r5, r1
@@ -41,7 +41,7 @@ define cc74 void @mysvol() nounwind noin
}
define cc74 void @mysvol2() nounwind noinline {
- ; CHECK: mysvol2:
+ ; CHECK-LABEL: mysvol2:
; CHECK-NOT: swi r3, r1
; CHECK-NOT: swi r4, r1
; CHECK-NOT: swi r5, r1
Modified: llvm/trunk/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@ target triple = "msp430-elf"
define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: call #__mulqi3
%mul = mul i8 %_si2, %_si1 ; <i8> [#uses=1]
ret i8 %mul
Modified: llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-rx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-rx.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-rx.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-rx.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@ define i16 @am1(i16 %x, i16* %a) nounwin
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: bis.w 0(r14), r15
@foo = external global i16
@@ -17,7 +17,7 @@ define i16 @am2(i16 %x) nounwind {
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: bis.w &foo, r15
@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -28,7 +28,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
%3 = or i8 %2,%x
ret i8 %3
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: bis.b bar(r14), r15
define i16 @am4(i16 %x) nounwind {
@@ -36,7 +36,7 @@ define i16 @am4(i16 %x) nounwind {
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: bis.w &32, r15
define i16 @am5(i16 %x, i16* %a) nounwind {
@@ -45,7 +45,7 @@ define i16 @am5(i16 %x, i16* %a) nounwin
%3 = or i16 %2,%x
ret i16 %3
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: bis.w 4(r14), r15
%S = type { i16, i16 }
@@ -56,7 +56,7 @@ define i16 @am6(i16 %x) nounwind {
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: bis.w &baz+2, r15
%T = type { i16, [2 x i8] }
@@ -69,6 +69,6 @@ define i8 @am7(i8 %x, i16 %n) nounwind {
%4 = or i8 %3,%x
ret i8 %4
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: bis.b duh+2(r14), r15
Modified: llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-xr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-xr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-xr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/AddrMode-bis-xr.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@ define void @am1(i16* %a, i16 %x) nounwi
store i16 %2, i16* %a
ret void
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: bis.w r14, 0(r15)
@foo = external global i16
@@ -19,7 +19,7 @@ define void @am2(i16 %x) nounwind {
store i16 %2, i16* @foo
ret void
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: bis.w r15, &foo
@bar = external global [2 x i8]
@@ -31,7 +31,7 @@ define void @am3(i16 %i, i8 %x) nounwind
store i8 %3, i8* %1
ret void
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: bis.b r14, bar(r15)
define void @am4(i16 %x) nounwind {
@@ -40,7 +40,7 @@ define void @am4(i16 %x) nounwind {
store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
ret void
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: bis.w r15, &32
define void @am5(i16* %a, i16 %x) readonly {
@@ -50,7 +50,7 @@ define void @am5(i16* %a, i16 %x) readon
store i16 %3, i16* %1
ret void
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: bis.w r14, 4(r15)
%S = type { i16, i16 }
@@ -62,7 +62,7 @@ define void @am6(i16 %x) nounwind {
store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
ret void
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: bis.w r15, &baz+2
%T = type { i16, [2 x i8] }
@@ -76,6 +76,6 @@ define void @am7(i16 %n, i8 %x) nounwind
store i8 %4, i8* %2
ret void
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: bis.b r14, duh+2(r15)
Modified: llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-rx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-rx.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-rx.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-rx.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ define i16 @am1(i16* %a) nounwind {
%1 = load i16* %a
ret i16 %1
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: mov.w 0(r15), r15
@foo = external global i16
@@ -15,7 +15,7 @@ define i16 @am2() nounwind {
%1 = load i16* @foo
ret i16 %1
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: mov.w &foo, r15
@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -25,14 +25,14 @@ define i8 @am3(i16 %n) nounwind {
%2 = load i8* %1
ret i8 %2
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: mov.b bar(r15), r15
define i16 @am4() nounwind {
%1 = load volatile i16* inttoptr(i16 32 to i16*)
ret i16 %1
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: mov.w &32, r15
define i16 @am5(i16* %a) nounwind {
@@ -40,7 +40,7 @@ define i16 @am5(i16* %a) nounwind {
%2 = load i16* %1
ret i16 %2
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: mov.w 4(r15), r15
%S = type { i16, i16 }
@@ -50,7 +50,7 @@ define i16 @am6() nounwind {
%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
ret i16 %1
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: mov.w &baz+2, r15
%T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define i8 @am7(i16 %n) nounwind {
%3= load i8* %2
ret i8 %3
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: mov.b duh+2(r15), r15
Modified: llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-xr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-xr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-xr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/AddrMode-mov-xr.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ define void @am1(i16* %a, i16 %b) nounwi
store i16 %b, i16* %a
ret void
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: mov.w r14, 0(r15)
@foo = external global i16
@@ -15,7 +15,7 @@ define void @am2(i16 %a) nounwind {
store i16 %a, i16* @foo
ret void
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: mov.w r15, &foo
@bar = external global [2 x i8]
@@ -25,14 +25,14 @@ define void @am3(i16 %i, i8 %a) nounwind
store i8 %a, i8* %1
ret void
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: mov.b r14, bar(r15)
define void @am4(i16 %a) nounwind {
store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
ret void
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: mov.w r15, &32
define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
@@ -40,7 +40,7 @@ define void @am5(i16* nocapture %p, i16
store i16 %a, i16* %1
ret void
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: mov.w r14, 4(r15)
%S = type { i16, i16 }
@@ -50,7 +50,7 @@ define void @am6(i16 %a) nounwind {
store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
ret void
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: mov.w r15, &baz+2
%T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define void @am7(i16 %n, i8 %a) nounwind
store i8 %a, i8* %2
ret void
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: mov.b r14, duh+2(r15)
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mi.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mi.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mi.ll Sun Jul 14 01:24:09 2013
@@ -5,14 +5,14 @@ target triple = "msp430-generic-generic"
@foo = common global i16 0, align 2
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w #2, &foo
store i16 2, i16 * @foo
ret void
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w #2, &foo
%1 = load i16* @foo
%2 = add i16 %1, 2
@@ -21,7 +21,7 @@ define void @add() nounwind {
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w #2, &foo
%1 = load i16* @foo
%2 = and i16 %1, 2
@@ -30,7 +30,7 @@ define void @and() nounwind {
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w #2, &foo
%1 = load i16* @foo
%2 = or i16 %1, 2
@@ -39,7 +39,7 @@ define void @bis() nounwind {
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w #2, &foo
%1 = load i16* @foo
%2 = xor i16 %1, 2
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ target triple = "msp430-generic-generic"
@bar = common global i16 0, align 2
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w &bar, &foo
%1 = load i16* @bar
store i16 %1, i16* @foo
@@ -13,7 +13,7 @@ define void @mov() nounwind {
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
@@ -23,7 +23,7 @@ define void @add() nounwind {
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
@@ -33,7 +33,7 @@ define void @and() nounwind {
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
@@ -43,7 +43,7 @@ define void @bis() nounwind {
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
@@ -63,7 +63,7 @@ entry:
store i16 0, i16* %retval
%0 = load i16* %retval ; <i16> [#uses=1]
ret i16 %0
-; CHECK: mov2:
+; CHECK-LABEL: mov2:
; CHECK: mov.w 2(r1), 6(r1)
; CHECK: mov.w 0(r1), 4(r1)
}
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mr.ll Sun Jul 14 01:24:09 2013
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
@foo = common global i16 0, align 2
define void @mov(i16 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w r15, &foo
store i16 %a, i16* @foo
ret void
}
define void @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w r15, &foo
%1 = load i16* @foo
%2 = add i16 %a, %1
@@ -20,7 +20,7 @@ define void @add(i16 %a) nounwind {
}
define void @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r15, &foo
%1 = load i16* @foo
%2 = and i16 %a, %1
@@ -29,7 +29,7 @@ define void @and(i16 %a) nounwind {
}
define void @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r15, &foo
%1 = load i16* @foo
%2 = or i16 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i16 %a) nounwind {
}
define void @bic(i16 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w r15, &foo
%1 = xor i16 %m, -1
%2 = load i16* @foo
@@ -48,7 +48,7 @@ define void @bic(i16 zeroext %m) nounwin
}
define void @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r15, &foo
%1 = load i16* @foo
%2 = xor i16 %a, %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16ri.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16ri.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16ri.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16ri.ll Sun Jul 14 01:24:09 2013
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i
target triple = "msp430-generic-generic"
define i16 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w #1, r15
ret i16 1
}
define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w #1, r15
%1 = add i16 %a, 1
ret i16 %1
}
define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w #1, r15
%1 = and i16 %a, 1
ret i16 %1
}
define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w #1, r15
%1 = or i16 %a, 1
ret i16 %1
}
define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w #1, r15
%1 = xor i16 %a, 1
ret i16 %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16rm.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
@foo = common global i16 0, align 2
define i16 @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w &foo, r15
%1 = load i16* @foo
%2 = add i16 %a, %1
@@ -12,7 +12,7 @@ define i16 @add(i16 %a) nounwind {
}
define i16 @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w &foo, r15
%1 = load i16* @foo
%2 = and i16 %a, %1
@@ -20,7 +20,7 @@ define i16 @and(i16 %a) nounwind {
}
define i16 @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w &foo, r15
%1 = load i16* @foo
%2 = or i16 %a, %1
@@ -28,7 +28,7 @@ define i16 @bis(i16 %a) nounwind {
}
define i16 @bic(i16 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w &foo, r15
%1 = load i16* @foo
%2 = xor i16 %1, -1
@@ -37,7 +37,7 @@ define i16 @bic(i16 %a) nounwind {
}
define i16 @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w &foo, r15
%1 = load i16* @foo
%2 = xor i16 %a, %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16rr.ll Sun Jul 14 01:24:09 2013
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i
target triple = "msp430-generic-generic"
define i16 @mov(i16 %a, i16 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w r14, r15
ret i16 %b
}
define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w r14, r15
%1 = add i16 %a, %b
ret i16 %1
}
define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r14, r15
%1 = and i16 %a, %b
ret i16 %1
}
define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r14, r15
%1 = or i16 %a, %b
ret i16 %1
}
define i16 @bic(i16 %a, i16 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w r14, r15
%1 = xor i16 %b, -1
%2 = and i16 %a, %1
@@ -38,7 +38,7 @@ define i16 @bic(i16 %a, i16 %b) nounwind
}
define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r14, r15
%1 = xor i16 %a, %b
ret i16 %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8mi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8mi.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8mi.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8mi.ll Sun Jul 14 01:24:09 2013
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
@foo = common global i8 0, align 1
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b #2, &foo
store i8 2, i8 * @foo
ret void
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b #2, &foo
%1 = load i8* @foo
%2 = add i8 %1, 2
@@ -20,7 +20,7 @@ define void @add() nounwind {
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b #2, &foo
%1 = load i8* @foo
%2 = and i8 %1, 2
@@ -29,7 +29,7 @@ define void @and() nounwind {
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b #2, &foo
%1 = load i8* @foo
%2 = or i8 %1, 2
@@ -38,7 +38,7 @@ define void @bis() nounwind {
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b #2, &foo
%1 = load i8* @foo
%2 = xor i8 %1, 2
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8mm.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
@bar = common global i8 0, align 1
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b &bar, &foo
%1 = load i8* @bar
store i8 %1, i8* @foo
@@ -14,7 +14,7 @@ define void @mov() nounwind {
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
@@ -24,7 +24,7 @@ define void @add() nounwind {
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
@@ -34,7 +34,7 @@ define void @and() nounwind {
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
@@ -44,7 +44,7 @@ define void @bis() nounwind {
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8mr.ll Sun Jul 14 01:24:09 2013
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
@foo = common global i8 0, align 1
define void @mov(i8 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b r15, &foo
store i8 %a, i8* @foo
ret void
}
define void @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b r15, &foo
%1 = load i8* @foo
%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define void @and(i8 %a) nounwind {
}
define void @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b r15, &foo
%1 = load i8* @foo
%2 = add i8 %a, %1
@@ -29,7 +29,7 @@ define void @add(i8 %a) nounwind {
}
define void @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b r15, &foo
%1 = load i8* @foo
%2 = or i8 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i8 %a) nounwind {
}
define void @bic(i8 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b r15, &foo
%1 = xor i8 %m, -1
%2 = load i8* @foo
@@ -48,7 +48,7 @@ define void @bic(i8 zeroext %m) nounwind
}
define void @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b r15, &foo
%1 = load i8* @foo
%2 = xor i8 %a, %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8ri.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8ri.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8ri.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8ri.ll Sun Jul 14 01:24:09 2013
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i
target triple = "msp430-generic-generic"
define i8 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b #1, r15
ret i8 1
}
define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b #1, r15
%1 = add i8 %a, 1
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b #1, r15
%1 = and i8 %a, 1
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b #1, r15
%1 = or i8 %a, 1
ret i8 %1
}
define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b #1, r15
%1 = xor i8 %a, 1
ret i8 %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8rm.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
@foo = common global i8 0, align 1
define i8 @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b &foo, r15
%1 = load i8* @foo
%2 = add i8 %a, %1
@@ -12,7 +12,7 @@ define i8 @add(i8 %a) nounwind {
}
define i8 @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b &foo, r15
%1 = load i8* @foo
%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define i8 @and(i8 %a) nounwind {
}
define i8 @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b &foo, r15
%1 = load i8* @foo
%2 = or i8 %a, %1
@@ -28,7 +28,7 @@ define i8 @bis(i8 %a) nounwind {
}
define i8 @bic(i8 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b &foo, r15
%1 = load i8* @foo
%2 = xor i8 %1, -1
@@ -37,7 +37,7 @@ define i8 @bic(i8 %a) nounwind {
}
define i8 @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b &foo, r15
%1 = load i8* @foo
%2 = xor i8 %a, %1
Modified: llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst8rr.ll Sun Jul 14 01:24:09 2013
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i
target triple = "msp430-generic-generic"
define i8 @mov(i8 %a, i8 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.{{[bw]}} r14, r15
ret i8 %b
}
define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r14, r15
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r14, r15
%1 = or i8 %a, %b
ret i8 %1
}
define i8 @bic(i8 %a, i8 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b r14, r15
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
@@ -38,7 +38,7 @@ define i8 @bic(i8 %a, i8 %b) nounwind {
}
define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r14, r15
%1 = xor i8 %a, %b
ret i8 %1
Modified: llvm/trunk/test/CodeGen/MSP430/bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/bit.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/bit.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/bit.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@ define i8 @bitbrr(i8 %a, i8 %b) nounwind
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbrr:
+; CHECK-LABEL: bitbrr:
; CHECK: bit.b r14, r15
define i8 @bitbri(i8 %a) nounwind {
@@ -20,7 +20,7 @@ define i8 @bitbri(i8 %a) nounwind {
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbri:
+; CHECK-LABEL: bitbri:
; CHECK: bit.b #15, r15
define i8 @bitbir(i8 %a) nounwind {
@@ -29,7 +29,7 @@ define i8 @bitbir(i8 %a) nounwind {
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbir:
+; CHECK-LABEL: bitbir:
; CHECK: bit.b #15, r15
define i8 @bitbmi() nounwind {
@@ -39,7 +39,7 @@ define i8 @bitbmi() nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbmi:
+; CHECK-LABEL: bitbmi:
; CHECK: bit.b #15, &foo8
define i8 @bitbim() nounwind {
@@ -49,7 +49,7 @@ define i8 @bitbim() nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbim:
+; CHECK-LABEL: bitbim:
; CHECK: bit.b #15, &foo8
define i8 @bitbrm(i8 %a) nounwind {
@@ -59,7 +59,7 @@ define i8 @bitbrm(i8 %a) nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbrm:
+; CHECK-LABEL: bitbrm:
; CHECK: bit.b &foo8, r15
define i8 @bitbmr(i8 %a) nounwind {
@@ -69,7 +69,7 @@ define i8 @bitbmr(i8 %a) nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbmr:
+; CHECK-LABEL: bitbmr:
; CHECK: bit.b r15, &foo8
define i8 @bitbmm() nounwind {
@@ -80,7 +80,7 @@ define i8 @bitbmm() nounwind {
%t5 = zext i1 %t4 to i8
ret i8 %t5
}
-; CHECK: bitbmm:
+; CHECK-LABEL: bitbmm:
; CHECK: bit.b &bar8, &foo8
@foo16 = external global i16
@@ -92,7 +92,7 @@ define i16 @bitwrr(i16 %a, i16 %b) nounw
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwrr:
+; CHECK-LABEL: bitwrr:
; CHECK: bit.w r14, r15
define i16 @bitwri(i16 %a) nounwind {
@@ -101,7 +101,7 @@ define i16 @bitwri(i16 %a) nounwind {
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwri:
+; CHECK-LABEL: bitwri:
; CHECK: bit.w #4080, r15
define i16 @bitwir(i16 %a) nounwind {
@@ -110,7 +110,7 @@ define i16 @bitwir(i16 %a) nounwind {
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwir:
+; CHECK-LABEL: bitwir:
; CHECK: bit.w #4080, r15
define i16 @bitwmi() nounwind {
@@ -120,7 +120,7 @@ define i16 @bitwmi() nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwmi:
+; CHECK-LABEL: bitwmi:
; CHECK: bit.w #4080, &foo16
define i16 @bitwim() nounwind {
@@ -130,7 +130,7 @@ define i16 @bitwim() nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwim:
+; CHECK-LABEL: bitwim:
; CHECK: bit.w #4080, &foo16
define i16 @bitwrm(i16 %a) nounwind {
@@ -140,7 +140,7 @@ define i16 @bitwrm(i16 %a) nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwrm:
+; CHECK-LABEL: bitwrm:
; CHECK: bit.w &foo16, r15
define i16 @bitwmr(i16 %a) nounwind {
@@ -150,7 +150,7 @@ define i16 @bitwmr(i16 %a) nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwmr:
+; CHECK-LABEL: bitwmr:
; CHECK: bit.w r15, &foo16
define i16 @bitwmm() nounwind {
@@ -161,6 +161,6 @@ define i16 @bitwmm() nounwind {
%t5 = zext i1 %t4 to i16
ret i16 %t5
}
-; CHECK: bitwmm:
+; CHECK-LABEL: bitwmm:
; CHECK: bit.w &bar16, &foo16
Modified: llvm/trunk/test/CodeGen/MSP430/byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/byval.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/byval.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/byval.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@ target triple = "msp430---elf"
define i16 @callee(%struct.Foo* byval %f) nounwind {
entry:
-; CHECK: callee:
+; CHECK-LABEL: callee:
; CHECK: mov.w 2(r1), r15
%0 = getelementptr inbounds %struct.Foo* %f, i32 0, i32 0
%1 = load i16* %0, align 2
@@ -17,7 +17,7 @@ entry:
define void @caller() nounwind {
entry:
-; CHECK: caller:
+; CHECK-LABEL: caller:
; CHECK: mov.w &foo+4, 4(r1)
; CHECK-NEXT: mov.w &foo+2, 2(r1)
; CHECK-NEXT: mov.w &foo, 0(r1)
Modified: llvm/trunk/test/CodeGen/MSP430/fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/fp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/fp.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/fp.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ target triple = "msp430---elf"
define void @fp() nounwind {
entry:
-; CHECK: fp:
+; CHECK-LABEL: fp:
; CHECK: push.w r4
; CHECK: mov.w r1, r4
; CHECK: sub.w #2, r1
Modified: llvm/trunk/test/CodeGen/MSP430/postinc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/postinc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/postinc.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/postinc.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@ for.body:
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
@@ -33,7 +33,7 @@ for.body:
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: sub:
+; CHECK-LABEL: sub:
; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2]
@@ -55,7 +55,7 @@ for.body:
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: or:
+; CHECK-LABEL: or:
; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2]
@@ -77,7 +77,7 @@ for.body:
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2]
@@ -99,7 +99,7 @@ for.body:
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2]
Modified: llvm/trunk/test/CodeGen/MSP430/setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/setcc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/setcc.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/setcc.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@ define i16 @sccweqand(i16 %a, i16 %b) no
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
@@ -20,7 +20,7 @@ define i16 @sccwneand(i16 %a, i16 %b) no
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
@@ -30,7 +30,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounw
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r12
; CHECK: rra.w r12
@@ -42,7 +42,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounw
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
@@ -53,7 +53,7 @@ define i16 @sccwugt(i16 %a, i16 %b) noun
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
; CHECK: cmp.w r15, r14
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
@@ -63,7 +63,7 @@ define i16 @sccwuge(i16 %a, i16 %b) noun
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
@@ -73,7 +73,7 @@ define i16 @sccwult(i16 %a, i16 %b) noun
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
; CHECK: cmp.w r14, r15
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
@@ -83,7 +83,7 @@ define i16 @sccwule(i16 %a, i16 %b) noun
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
; CHECK: cmp.w r15, r14
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
Modified: llvm/trunk/test/CodeGen/MSP430/shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/shifts.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/shifts.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/shifts.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@ target triple = "msp430-elf"
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: lshr8:
+; CHECK-LABEL: lshr8:
; CHECK: rrc.b
%shr = lshr i8 %a, %cnt
ret i8 %shr
@@ -12,7 +12,7 @@ entry:
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: ashr8:
+; CHECK-LABEL: ashr8:
; CHECK: rra.b
%shr = ashr i8 %a, %cnt
ret i8 %shr
@@ -28,7 +28,7 @@ entry:
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: lshr16:
+; CHECK-LABEL: lshr16:
; CHECK: rrc.w
%shr = lshr i16 %a, %cnt
ret i16 %shr
@@ -36,7 +36,7 @@ entry:
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: ashr16:
+; CHECK-LABEL: ashr16:
; CHECK: rra.w
%shr = ashr i16 %a, %cnt
ret i16 %shr
@@ -44,7 +44,7 @@ entry:
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: shl16:
+; CHECK-LABEL: shl16:
; CHECK: rla.w
%shl = shl i16 %a, %cnt
ret i16 %shl
Modified: llvm/trunk/test/CodeGen/MSP430/vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/vararg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/vararg.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/vararg.ll Sun Jul 14 01:24:09 2013
@@ -9,7 +9,7 @@ declare void @llvm.va_copy(i8*, i8*) nou
define void @va_start(i16 %a, ...) nounwind {
entry:
-; CHECK: va_start:
+; CHECK-LABEL: va_start:
; CHECK: sub.w #2, r1
%vl = alloca i8*, align 2
%vl1 = bitcast i8** %vl to i8*
@@ -23,7 +23,7 @@ entry:
define i16 @va_arg(i8* %vl) nounwind {
entry:
-; CHECK: va_arg:
+; CHECK-LABEL: va_arg:
%vl.addr = alloca i8*, align 2
; CHECK: mov.w r15, 0(r1)
store i8* %vl, i8** %vl.addr, align 2
@@ -37,7 +37,7 @@ entry:
define void @va_copy(i8* %vl) nounwind {
entry:
-; CHECK: va_copy:
+; CHECK-LABEL: va_copy:
%vl.addr = alloca i8*, align 2
%vl2 = alloca i8*, align 2
; CHECK: mov.w r15, 2(r1)
Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/atomic.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@ entry:
%0 = atomicrmw add i32* @x, i32 %incr monotonic
ret i32 %0
-; CHECK-EL: AtomicLoadAdd32:
+; CHECK-EL-LABEL: AtomicLoadAdd32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
@@ -16,7 +16,7 @@ entry:
; CHECK-EL: sc $[[R2]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicLoadAdd32:
+; CHECK-EB-LABEL: AtomicLoadAdd32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
@@ -30,7 +30,7 @@ entry:
%0 = atomicrmw nand i32* @x, i32 %incr monotonic
ret i32 %0
-; CHECK-EL: AtomicLoadNand32:
+; CHECK-EL-LABEL: AtomicLoadNand32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
@@ -39,7 +39,7 @@ entry:
; CHECK-EL: sc $[[R2]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicLoadNand32:
+; CHECK-EB-LABEL: AtomicLoadNand32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
@@ -57,14 +57,14 @@ entry:
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
ret i32 %0
-; CHECK-EL: AtomicSwap32:
+; CHECK-EL-LABEL: AtomicSwap32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicSwap32:
+; CHECK-EB-LABEL: AtomicSwap32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])
@@ -80,7 +80,7 @@ entry:
%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
ret i32 %0
-; CHECK-EL: AtomicCmpSwap32:
+; CHECK-EL-LABEL: AtomicCmpSwap32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $2, 0($[[R0]])
@@ -89,7 +89,7 @@ entry:
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
; CHECK-EL: $[[BB1]]:
-; CHECK-EB: AtomicCmpSwap32:
+; CHECK-EB-LABEL: AtomicCmpSwap32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $2, 0($[[R0]])
@@ -108,7 +108,7 @@ entry:
%0 = atomicrmw add i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadAdd8:
+; CHECK-EL-LABEL: AtomicLoadAdd8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -133,7 +133,7 @@ entry:
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadAdd8:
+; CHECK-EB-LABEL: AtomicLoadAdd8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -165,7 +165,7 @@ entry:
%0 = atomicrmw sub i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadSub8:
+; CHECK-EL-LABEL: AtomicLoadSub8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -190,7 +190,7 @@ entry:
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadSub8:
+; CHECK-EB-LABEL: AtomicLoadSub8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -222,7 +222,7 @@ entry:
%0 = atomicrmw nand i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadNand8:
+; CHECK-EL-LABEL: AtomicLoadNand8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -248,7 +248,7 @@ entry:
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadNand8:
+; CHECK-EB-LABEL: AtomicLoadNand8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -281,7 +281,7 @@ entry:
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
ret i8 %0
-; CHECK-EL: AtomicSwap8:
+; CHECK-EL-LABEL: AtomicSwap8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -305,7 +305,7 @@ entry:
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicSwap8:
+; CHECK-EB-LABEL: AtomicSwap8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -336,7 +336,7 @@ entry:
%0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
ret i8 %0
-; CHECK-EL: AtomicCmpSwap8:
+; CHECK-EL-LABEL: AtomicCmpSwap8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -365,7 +365,7 @@ entry:
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicCmpSwap8:
+; CHECK-EB-LABEL: AtomicCmpSwap8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -403,14 +403,14 @@ entry:
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
ret i32 %0
-; CHECK-EL: CheckSync:
+; CHECK-EL-LABEL: CheckSync:
; CHECK-EL: sync 0
; CHECK-EL: ll
; CHECK-EL: sc
; CHECK-EL: beq
; CHECK-EL: sync 0
-; CHECK-EB: CheckSync:
+; CHECK-EB-LABEL: CheckSync:
; CHECK-EB: sync 0
; CHECK-EB: ll
; CHECK-EB: sc
Modified: llvm/trunk/test/CodeGen/Mips/atomicops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomicops.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/atomicops.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/atomicops.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@ entry:
%0 = atomicrmw add i32* %mem, i32 %val seq_cst
%add = add nsw i32 %0, %c
ret i32 %add
-; 16: foo:
+; 16-LABEL: foo:
; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
}
@@ -26,7 +26,7 @@ entry:
%4 = atomicrmw xchg i32* %x, i32 1 seq_cst
%5 = load volatile i32* %x, align 4
%call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
-; 16: main:
+; 16-LABEL: main:
; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
Modified: llvm/trunk/test/CodeGen/Mips/biggot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/biggot.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/biggot.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/biggot.ll Sun Jul 14 01:24:09 2013
@@ -31,12 +31,12 @@ declare void @foo0(i32)
define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
entry:
-; O32: foo2:
+; O32-LABEL: foo2:
; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
; O32: lw ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
-; N64: foo2:
+; N64-LABEL: foo2:
; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
; N64: ld ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
Modified: llvm/trunk/test/CodeGen/Mips/brdelayslot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/brdelayslot.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/brdelayslot.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/brdelayslot.ll Sun Jul 14 01:24:09 2013
@@ -31,7 +31,7 @@ declare void @foo2(i32)
;
define void @foo3(i32 %a) nounwind {
entry:
-; Default: foo3:
+; Default-LABEL: foo3:
; Default: jalr
; Default: cvt.d.w
@@ -49,7 +49,7 @@ declare void @foo4(double)
; Check that branch delay slot can be filled with an instruction with operand
; $1.
;
-; Default: foo5:
+; Default-LABEL: foo5:
; Default-NOT: nop
define void @foo5(i32 %a) nounwind {
@@ -76,7 +76,7 @@ if.end:
; Check that delay slot filler can place mov.s or mov.d in delay slot.
;
-; Default: foo6:
+; Default-LABEL: foo6:
; Default-NOT: nop
; Default: .end foo6
@@ -90,7 +90,7 @@ declare void @foo7(double, float)
; Check that a store can move past other memory instructions.
;
-; STATICO1: foo8:
+; STATICO1-LABEL: foo8:
; STATICO1: jalr ${{[0-9]+}}
; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
@@ -109,7 +109,7 @@ entry:
; Test searchForward. Check that the second jal's slot is filled with another
; instruction in the same block.
;
-; FORWARD: foo10:
+; FORWARD-LABEL: foo10:
; FORWARD: jal foo11
; FORWARD: jal foo11
; FORWARD-NOT: nop
@@ -130,7 +130,7 @@ declare void @foo11()
; Check that delay slots of branches in both the entry block and loop body are
; filled.
;
-; SUCCBB: succbbs_loop1:
+; SUCCBB-LABEL: succbbs_loop1:
; SUCCBB: blez $5, $BB
; SUCCBB-NEXT: addiu
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
@@ -158,7 +158,7 @@ for.end:
; Check that the first branch has its slot filled.
;
-; SUCCBB: succbbs_br1:
+; SUCCBB-LABEL: succbbs_br1:
; SUCCBB: beq ${{[0-9]+}}, $zero, $BB
; SUCCBB-NEXT: lw $25, %call16(foo100)
Modified: llvm/trunk/test/CodeGen/Mips/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/bswap.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/bswap.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
define i32 @bswap32(i32 %x) nounwind readnone {
entry:
-; MIPS32: bswap32:
+; MIPS32-LABEL: bswap32:
; MIPS32: wsbh $[[R0:[0-9]+]]
; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
%or.3 = call i32 @llvm.bswap.i32(i32 %x)
@@ -12,7 +12,7 @@ entry:
define i64 @bswap64(i64 %x) nounwind readnone {
entry:
-; MIPS64: bswap64:
+; MIPS64-LABEL: bswap64:
; MIPS64: dsbh $[[R0:[0-9]+]]
; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
%or.7 = call i64 @llvm.bswap.i64(i64 %x)
Modified: llvm/trunk/test/CodeGen/Mips/check-noat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/check-noat.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/check-noat.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/check-noat.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
define void @f() nounwind readnone {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: .set noat
; CHECK: .set at
Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Sun Jul 14 01:24:09 2013
@@ -22,11 +22,11 @@ entry:
@c = global i32 1, align 4
@d = global i32 0, align 4
-; O32: cmov2:
+; O32-LABEL: cmov2:
; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
-; N64: cmov2:
+; N64-LABEL: cmov2:
; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
@@ -39,7 +39,7 @@ entry:
ret i32 %cond
}
-; O32: cmov3:
+; O32-LABEL: cmov3:
; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
@@ -49,7 +49,7 @@ entry:
ret i32 %cond
}
-; N64: cmov4:
+; N64-LABEL: cmov4:
; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
@@ -67,7 +67,7 @@ entry:
; (movz t, (setlt a, N + 1), f)
; if N + 1 fits in 16-bit.
-; O32: slti0:
+; O32-LABEL: slti0:
; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -78,7 +78,7 @@ entry:
ret i32 %cond
}
-; O32: slti1:
+; O32-LABEL: slti1:
; O32: slt ${{[0-9]+}}
define i32 @slti1(i32 %a) {
@@ -88,7 +88,7 @@ entry:
ret i32 %cond
}
-; O32: slti2:
+; O32-LABEL: slti2:
; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -99,7 +99,7 @@ entry:
ret i32 %cond
}
-; O32: slti3:
+; O32-LABEL: slti3:
; O32: slt ${{[0-9]+}}
define i32 @slti3(i32 %a) {
@@ -111,7 +111,7 @@ entry:
; 64-bit patterns.
-; N64: slti64_0:
+; N64-LABEL: slti64_0:
; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -122,7 +122,7 @@ entry:
ret i64 %conv
}
-; N64: slti64_1:
+; N64-LABEL: slti64_1:
; N64: slt ${{[0-9]+}}
define i64 @slti64_1(i64 %a) {
@@ -132,7 +132,7 @@ entry:
ret i64 %conv
}
-; N64: slti64_2:
+; N64-LABEL: slti64_2:
; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -143,7 +143,7 @@ entry:
ret i64 %conv
}
-; N64: slti64_3:
+; N64-LABEL: slti64_3:
; N64: slt ${{[0-9]+}}
define i64 @slti64_3(i64 %a) {
@@ -155,7 +155,7 @@ entry:
; sltiu instructions.
-; O32: sltiu0:
+; O32-LABEL: sltiu0:
; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -166,7 +166,7 @@ entry:
ret i32 %cond
}
-; O32: sltiu1:
+; O32-LABEL: sltiu1:
; O32: sltu ${{[0-9]+}}
define i32 @sltiu1(i32 %a) {
@@ -176,7 +176,7 @@ entry:
ret i32 %cond
}
-; O32: sltiu2:
+; O32-LABEL: sltiu2:
; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
@@ -187,7 +187,7 @@ entry:
ret i32 %cond
}
-; O32: sltiu3:
+; O32-LABEL: sltiu3:
; O32: sltu ${{[0-9]+}}
define i32 @sltiu3(i32 %a) {
Modified: llvm/trunk/test/CodeGen/Mips/const-mult.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/const-mult.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/const-mult.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/const-mult.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
-; CHECK: mul5_32:
+; CHECK-LABEL: mul5_32:
; CHECK: sll $[[R0:[0-9]+]], $4, 2
; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
@@ -12,7 +12,7 @@ entry:
ret i32 %mul
}
-; CHECK: mul27_32:
+; CHECK-LABEL: mul27_32:
; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
@@ -24,7 +24,7 @@ entry:
ret i32 %mul
}
-; CHECK: muln2147483643_32:
+; CHECK-LABEL: muln2147483643_32:
; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
@@ -36,7 +36,7 @@ entry:
ret i32 %mul
}
-; CHECK64: muln9223372036854775805_64:
+; CHECK64-LABEL: muln9223372036854775805_64:
; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
Modified: llvm/trunk/test/CodeGen/Mips/divrem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/divrem.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/divrem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/divrem.ll Sun Jul 14 01:24:09 2013
@@ -2,12 +2,12 @@
; RUN: llc -march=mips -mno-check-zero-division < %s |\
; RUN: FileCheck %s -check-prefix=NOCHECK
-; TRAP: sdiv1:
+; TRAP-LABEL: sdiv1:
; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mflo
-; NOCHECK: sdiv1:
+; NOCHECK-LABEL: sdiv1:
; NOCHECK-NOT: teq
; NOCHECK: .end sdiv1
@@ -17,7 +17,7 @@ entry:
ret i32 %div
}
-; TRAP: srem1:
+; TRAP-LABEL: srem1:
; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mfhi
@@ -28,7 +28,7 @@ entry:
ret i32 %rem
}
-; TRAP: udiv1:
+; TRAP-LABEL: udiv1:
; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mflo
@@ -39,7 +39,7 @@ entry:
ret i32 %div
}
-; TRAP: urem1:
+; TRAP-LABEL: urem1:
; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mfhi
Modified: llvm/trunk/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -17,7 +17,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -34,7 +34,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -51,7 +51,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -68,7 +68,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -85,7 +85,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -102,7 +102,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -119,7 +119,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -136,7 +136,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -153,7 +153,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -170,7 +170,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -187,7 +187,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -204,7 +204,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -221,7 +221,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -238,7 +238,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -255,7 +255,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -272,7 +272,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -289,7 +289,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -306,7 +306,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -323,7 +323,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -340,7 +340,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -355,7 +355,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -370,7 +370,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -385,7 +385,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -400,7 +400,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -415,7 +415,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -430,7 +430,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -445,7 +445,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -460,7 +460,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -475,7 +475,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -490,7 +490,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -505,7 +505,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -520,7 +520,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -535,7 +535,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -550,7 +550,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -565,7 +565,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -580,7 +580,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -595,7 +595,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -610,7 +610,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -625,7 +625,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
Modified: llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll Sun Jul 14 01:24:09 2013
@@ -128,7 +128,7 @@ entry:
ret i64 %add
}
-; R1: shift1_v2i16_shl_:
+; R1-LABEL: shift1_v2i16_shl_:
; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
@@ -140,7 +140,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v2i16_sra_:
+; R1-LABEL: shift1_v2i16_sra_:
; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
@@ -152,9 +152,9 @@ entry:
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v2ui16_srl_:
+; R1-LABEL: shift1_v2ui16_srl_:
; R1-NOT: shrl.ph
-; R2: shift1_v2ui16_srl_:
+; R2-LABEL: shift1_v2ui16_srl_:
; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
@@ -166,7 +166,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4i8_shl_:
+; R1-LABEL: shift1_v4i8_shl_:
; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
@@ -178,9 +178,9 @@ entry:
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4i8_sra_:
+; R1-LABEL: shift1_v4i8_sra_:
; R1-NOT: shra.qb
-; R2: shift1_v4i8_sra_:
+; R2-LABEL: shift1_v4i8_sra_:
; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
@@ -192,7 +192,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4ui8_srl_:
+; R1-LABEL: shift1_v4ui8_srl_:
; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
Modified: llvm/trunk/test/CodeGen/Mips/ex2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/ex2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/ex2.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/ex2.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@_ZTIPKc = external constant i8*
define i32 @main() {
-; 16: main:
+; 16-LABEL: main:
; 16: .cfi_startproc
; 16: save $ra, $s0, $s1, 32
; 16: .cfi_def_cfa_offset 32
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@
; X with -3
define i32 @constraint_X() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_X:
+;CHECK_LITTLE_32-LABEL: constraint_X:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
;CHECK_LITTLE_32: #NO_APP
@@ -21,7 +21,7 @@ entry:
; x with -3
define i32 @constraint_x() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_x:
+;CHECK_LITTLE_32-LABEL: constraint_x:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
;CHECK_LITTLE_32: #NO_APP
@@ -32,7 +32,7 @@ entry:
; d with -3
define i32 @constraint_d() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_d:
+;CHECK_LITTLE_32-LABEL: constraint_d:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
@@ -43,7 +43,7 @@ entry:
; m with -3
define i32 @constraint_m() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_m:
+;CHECK_LITTLE_32-LABEL: constraint_m:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-4
;CHECK_LITTLE_32: #NO_APP
@@ -54,7 +54,7 @@ entry:
; z with -3
define i32 @constraint_z() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_z:
+;CHECK_LITTLE_32-LABEL: constraint_z:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
@@ -71,7 +71,7 @@ entry:
; a long long in 32 bit mode (use to assert)
define i32 @constraint_longlong() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_longlong:
+;CHECK_LITTLE_32-LABEL: constraint_longlong:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},3
;CHECK_LITTLE_32: #NO_APP
@@ -82,7 +82,7 @@ entry:
; D, in little endian the source reg will be 4 bytes into the long long
define i32 @constraint_D() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_D:
+;CHECK_LITTLE_32-LABEL: constraint_D:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -91,7 +91,7 @@ entry:
;CHECK_LITTLE_32: #NO_APP
; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32: constraint_D:
+;CHECK_BIG_32-LABEL: constraint_D:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -107,7 +107,7 @@ entry:
; L, in little endian the source reg will be 0 bytes into the long long
define i32 @constraint_L() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_L:
+;CHECK_LITTLE_32-LABEL: constraint_L:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -115,7 +115,7 @@ entry:
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32: constraint_L:
+;CHECK_BIG_32-LABEL: constraint_L:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -131,7 +131,7 @@ entry:
; M, in little endian the source reg will be 4 bytes into the long long
define i32 @constraint_M() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_M:
+;CHECK_LITTLE_32-LABEL: constraint_M:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -139,7 +139,7 @@ entry:
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32: constraint_M:
+;CHECK_BIG_32-LABEL: constraint_M:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
Modified: llvm/trunk/test/CodeGen/Mips/largefr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largefr1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largefr1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largefr1.ll Sun Jul 14 01:24:09 2013
@@ -22,7 +22,7 @@ entry:
define i32 @main() nounwind {
entry:
-; 1: main:
+; 1-LABEL: main:
; 1: 1: .word -797992
; 1: li ${{[0-9]+}}, 12
; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
Modified: llvm/trunk/test/CodeGen/Mips/mips16fpe.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips16fpe.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips16fpe.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips16fpe.ll Sun Jul 14 01:24:09 2013
@@ -41,7 +41,7 @@
define void @test_addsf3() nounwind {
entry:
-;16hf: test_addsf3:
+;16hf-LABEL: test_addsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%add = fadd float %0, %1
@@ -52,7 +52,7 @@ entry:
define void @test_adddf3() nounwind {
entry:
-;16hf: test_adddf3:
+;16hf-LABEL: test_adddf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%add = fadd double %0, %1
@@ -63,7 +63,7 @@ entry:
define void @test_subsf3() nounwind {
entry:
-;16hf: test_subsf3:
+;16hf-LABEL: test_subsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%sub = fsub float %0, %1
@@ -74,7 +74,7 @@ entry:
define void @test_subdf3() nounwind {
entry:
-;16hf: test_subdf3:
+;16hf-LABEL: test_subdf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%sub = fsub double %0, %1
@@ -85,7 +85,7 @@ entry:
define void @test_mulsf3() nounwind {
entry:
-;16hf: test_mulsf3:
+;16hf-LABEL: test_mulsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%mul = fmul float %0, %1
@@ -96,7 +96,7 @@ entry:
define void @test_muldf3() nounwind {
entry:
-;16hf: test_muldf3:
+;16hf-LABEL: test_muldf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%mul = fmul double %0, %1
@@ -107,7 +107,7 @@ entry:
define void @test_divsf3() nounwind {
entry:
-;16hf: test_divsf3:
+;16hf-LABEL: test_divsf3:
%0 = load float* @y, align 4
%1 = load float* @x, align 4
%div = fdiv float %0, %1
@@ -118,7 +118,7 @@ entry:
define void @test_divdf3() nounwind {
entry:
-;16hf: test_divdf3:
+;16hf-LABEL: test_divdf3:
%0 = load double* @yd, align 8
%mul = fmul double %0, 2.000000e+00
%1 = load double* @xd, align 8
@@ -130,7 +130,7 @@ entry:
define void @test_extendsfdf2() nounwind {
entry:
-;16hf: test_extendsfdf2:
+;16hf-LABEL: test_extendsfdf2:
%0 = load float* @x, align 4
%conv = fpext float %0 to double
store double %conv, double* @extendsfdf2_result, align 8
@@ -140,7 +140,7 @@ entry:
define void @test_truncdfsf2() nounwind {
entry:
-;16hf: test_truncdfsf2:
+;16hf-LABEL: test_truncdfsf2:
%0 = load double* @xd2, align 8
%conv = fptrunc double %0 to float
store float %conv, float* @truncdfsf2_result, align 4
@@ -150,7 +150,7 @@ entry:
define void @test_fix_truncsfsi() nounwind {
entry:
-;16hf: test_fix_truncsfsi:
+;16hf-LABEL: test_fix_truncsfsi:
%0 = load float* @x, align 4
%conv = fptosi float %0 to i32
store i32 %conv, i32* @fix_truncsfsi_result, align 4
@@ -160,7 +160,7 @@ entry:
define void @test_fix_truncdfsi() nounwind {
entry:
-;16hf: test_fix_truncdfsi:
+;16hf-LABEL: test_fix_truncdfsi:
%0 = load double* @xd, align 8
%conv = fptosi double %0 to i32
store i32 %conv, i32* @fix_truncdfsi_result, align 4
@@ -170,7 +170,7 @@ entry:
define void @test_floatsisf() nounwind {
entry:
-;16hf: test_floatsisf:
+;16hf-LABEL: test_floatsisf:
%0 = load i32* @si, align 4
%conv = sitofp i32 %0 to float
store float %conv, float* @floatsisf_result, align 4
@@ -180,7 +180,7 @@ entry:
define void @test_floatsidf() nounwind {
entry:
-;16hf: test_floatsidf:
+;16hf-LABEL: test_floatsidf:
%0 = load i32* @si, align 4
%conv = sitofp i32 %0 to double
store double %conv, double* @floatsidf_result, align 8
@@ -190,7 +190,7 @@ entry:
define void @test_floatunsisf() nounwind {
entry:
-;16hf: test_floatunsisf:
+;16hf-LABEL: test_floatunsisf:
%0 = load i32* @ui, align 4
%conv = uitofp i32 %0 to float
store float %conv, float* @floatunsisf_result, align 4
@@ -200,7 +200,7 @@ entry:
define void @test_floatunsidf() nounwind {
entry:
-;16hf: test_floatunsidf:
+;16hf-LABEL: test_floatunsidf:
%0 = load i32* @ui, align 4
%conv = uitofp i32 %0 to double
store double %conv, double* @floatunsidf_result, align 8
@@ -210,7 +210,7 @@ entry:
define void @test_eqsf2() nounwind {
entry:
-;16hf: test_eqsf2:
+;16hf-LABEL: test_eqsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp oeq float %0, %1
@@ -222,7 +222,7 @@ entry:
define void @test_eqdf2() nounwind {
entry:
-;16hf: test_eqdf2:
+;16hf-LABEL: test_eqdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp oeq double %0, %1
@@ -234,7 +234,7 @@ entry:
define void @test_nesf2() nounwind {
entry:
-;16hf: test_nesf2:
+;16hf-LABEL: test_nesf2:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%cmp = fcmp une float %0, %1
@@ -246,7 +246,7 @@ entry:
define void @test_nedf2() nounwind {
entry:
-;16hf: test_nedf2:
+;16hf-LABEL: test_nedf2:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%cmp = fcmp une double %0, %1
@@ -258,7 +258,7 @@ entry:
define void @test_gesf2() nounwind {
entry:
-;16hf: test_gesf2:
+;16hf-LABEL: test_gesf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp oge float %0, %1
@@ -273,7 +273,7 @@ entry:
define void @test_gedf2() nounwind {
entry:
-;16hf: test_gedf2:
+;16hf-LABEL: test_gedf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp oge double %0, %1
@@ -288,7 +288,7 @@ entry:
define void @test_ltsf2() nounwind {
entry:
-;16hf: test_ltsf2:
+;16hf-LABEL: test_ltsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%lnot = fcmp uge float %0, %1
@@ -304,7 +304,7 @@ entry:
define void @test_ltdf2() nounwind {
entry:
-;16hf: test_ltdf2:
+;16hf-LABEL: test_ltdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%lnot = fcmp uge double %0, %1
@@ -320,7 +320,7 @@ entry:
define void @test_lesf2() nounwind {
entry:
-;16hf: test_lesf2:
+;16hf-LABEL: test_lesf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp ole float %0, %1
@@ -335,7 +335,7 @@ entry:
define void @test_ledf2() nounwind {
entry:
-;16hf: test_ledf2:
+;16hf-LABEL: test_ledf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp ole double %0, %1
@@ -350,7 +350,7 @@ entry:
define void @test_gtsf2() nounwind {
entry:
-;16hf: test_gtsf2:
+;16hf-LABEL: test_gtsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%lnot = fcmp ule float %0, %1
@@ -365,7 +365,7 @@ entry:
define void @test_gtdf2() nounwind {
entry:
-;16hf: test_gtdf2:
+;16hf-LABEL: test_gtdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%lnot = fcmp ule double %0, %1
Modified: llvm/trunk/test/CodeGen/Mips/mips64-f128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64-f128.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64-f128.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64-f128.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
@gf1 = external global float
@gd1 = external global double
-; CHECK: addLD:
+; CHECK-LABEL: addLD:
; CHECK: ld $25, %call16(__addtf3)
define fp128 @addLD() {
@@ -18,7 +18,7 @@ entry:
ret fp128 %add
}
-; CHECK: subLD:
+; CHECK-LABEL: subLD:
; CHECK: ld $25, %call16(__subtf3)
define fp128 @subLD() {
@@ -29,7 +29,7 @@ entry:
ret fp128 %sub
}
-; CHECK: mulLD:
+; CHECK-LABEL: mulLD:
; CHECK: ld $25, %call16(__multf3)
define fp128 @mulLD() {
@@ -40,7 +40,7 @@ entry:
ret fp128 %mul
}
-; CHECK: divLD:
+; CHECK-LABEL: divLD:
; CHECK: ld $25, %call16(__divtf3)
define fp128 @divLD() {
@@ -51,7 +51,7 @@ entry:
ret fp128 %div
}
-; CHECK: conv_LD_char:
+; CHECK-LABEL: conv_LD_char:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_char(i8 signext %a) {
@@ -60,7 +60,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_short:
+; CHECK-LABEL: conv_LD_short:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_short(i16 signext %a) {
@@ -69,7 +69,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_int:
+; CHECK-LABEL: conv_LD_int:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_int(i32 %a) {
@@ -78,7 +78,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_LL:
+; CHECK-LABEL: conv_LD_LL:
; CHECK: ld $25, %call16(__floatditf)
define fp128 @conv_LD_LL(i64 %a) {
@@ -87,7 +87,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_UChar:
+; CHECK-LABEL: conv_LD_UChar:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UChar(i8 zeroext %a) {
@@ -96,7 +96,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_UShort:
+; CHECK-LABEL: conv_LD_UShort:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UShort(i16 zeroext %a) {
@@ -105,7 +105,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_UInt:
+; CHECK-LABEL: conv_LD_UInt:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UInt(i32 %a) {
@@ -114,7 +114,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_ULL:
+; CHECK-LABEL: conv_LD_ULL:
; CHECK: ld $25, %call16(__floatunditf)
define fp128 @conv_LD_ULL(i64 %a) {
@@ -123,7 +123,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_char_LD:
+; CHECK-LABEL: conv_char_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define signext i8 @conv_char_LD(fp128 %a) {
@@ -132,7 +132,7 @@ entry:
ret i8 %conv
}
-; CHECK: conv_short_LD:
+; CHECK-LABEL: conv_short_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define signext i16 @conv_short_LD(fp128 %a) {
@@ -141,7 +141,7 @@ entry:
ret i16 %conv
}
-; CHECK: conv_int_LD:
+; CHECK-LABEL: conv_int_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define i32 @conv_int_LD(fp128 %a) {
@@ -150,7 +150,7 @@ entry:
ret i32 %conv
}
-; CHECK: conv_LL_LD:
+; CHECK-LABEL: conv_LL_LD:
; CHECK: ld $25, %call16(__fixtfdi)
define i64 @conv_LL_LD(fp128 %a) {
@@ -159,7 +159,7 @@ entry:
ret i64 %conv
}
-; CHECK: conv_UChar_LD:
+; CHECK-LABEL: conv_UChar_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define zeroext i8 @conv_UChar_LD(fp128 %a) {
@@ -168,7 +168,7 @@ entry:
ret i8 %conv
}
-; CHECK: conv_UShort_LD:
+; CHECK-LABEL: conv_UShort_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define zeroext i16 @conv_UShort_LD(fp128 %a) {
@@ -177,7 +177,7 @@ entry:
ret i16 %conv
}
-; CHECK: conv_UInt_LD:
+; CHECK-LABEL: conv_UInt_LD:
; CHECK: ld $25, %call16(__fixunstfsi)
define i32 @conv_UInt_LD(fp128 %a) {
@@ -186,7 +186,7 @@ entry:
ret i32 %conv
}
-; CHECK: conv_ULL_LD:
+; CHECK-LABEL: conv_ULL_LD:
; CHECK: ld $25, %call16(__fixunstfdi)
define i64 @conv_ULL_LD(fp128 %a) {
@@ -195,7 +195,7 @@ entry:
ret i64 %conv
}
-; CHECK: conv_LD_float:
+; CHECK-LABEL: conv_LD_float:
; CHECK: ld $25, %call16(__extendsftf2)
define fp128 @conv_LD_float(float %a) {
@@ -204,7 +204,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_LD_double:
+; CHECK-LABEL: conv_LD_double:
; CHECK: ld $25, %call16(__extenddftf2)
define fp128 @conv_LD_double(double %a) {
@@ -213,7 +213,7 @@ entry:
ret fp128 %conv
}
-; CHECK: conv_float_LD:
+; CHECK-LABEL: conv_float_LD:
; CHECK: ld $25, %call16(__trunctfsf2)
define float @conv_float_LD(fp128 %a) {
@@ -222,7 +222,7 @@ entry:
ret float %conv
}
-; CHECK: conv_double_LD:
+; CHECK-LABEL: conv_double_LD:
; CHECK: ld $25, %call16(__trunctfdf2)
define double @conv_double_LD(fp128 %a) {
@@ -231,7 +231,7 @@ entry:
ret double %conv
}
-; CHECK: libcall1_fabsl:
+; CHECK-LABEL: libcall1_fabsl:
; CHECK-DAG: ld $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
; CHECK-DAG: daddiu $[[R1:[0-9]+]], $zero, 1
; CHECK-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63
@@ -248,7 +248,7 @@ entry:
declare fp128 @fabsl(fp128) #1
-; CHECK: libcall1_ceill:
+; CHECK-LABEL: libcall1_ceill:
; CHECK: ld $25, %call16(ceill)
define fp128 @libcall1_ceill() {
@@ -260,7 +260,7 @@ entry:
declare fp128 @ceill(fp128) #1
-; CHECK: libcall1_sinl:
+; CHECK-LABEL: libcall1_sinl:
; CHECK: ld $25, %call16(sinl)
define fp128 @libcall1_sinl() {
@@ -272,7 +272,7 @@ entry:
declare fp128 @sinl(fp128) #2
-; CHECK: libcall1_cosl:
+; CHECK-LABEL: libcall1_cosl:
; CHECK: ld $25, %call16(cosl)
define fp128 @libcall1_cosl() {
@@ -284,7 +284,7 @@ entry:
declare fp128 @cosl(fp128) #2
-; CHECK: libcall1_expl:
+; CHECK-LABEL: libcall1_expl:
; CHECK: ld $25, %call16(expl)
define fp128 @libcall1_expl() {
@@ -296,7 +296,7 @@ entry:
declare fp128 @expl(fp128) #2
-; CHECK: libcall1_exp2l:
+; CHECK-LABEL: libcall1_exp2l:
; CHECK: ld $25, %call16(exp2l)
define fp128 @libcall1_exp2l() {
@@ -308,7 +308,7 @@ entry:
declare fp128 @exp2l(fp128) #2
-; CHECK: libcall1_logl:
+; CHECK-LABEL: libcall1_logl:
; CHECK: ld $25, %call16(logl)
define fp128 @libcall1_logl() {
@@ -320,7 +320,7 @@ entry:
declare fp128 @logl(fp128) #2
-; CHECK: libcall1_log2l:
+; CHECK-LABEL: libcall1_log2l:
; CHECK: ld $25, %call16(log2l)
define fp128 @libcall1_log2l() {
@@ -332,7 +332,7 @@ entry:
declare fp128 @log2l(fp128) #2
-; CHECK: libcall1_log10l:
+; CHECK-LABEL: libcall1_log10l:
; CHECK: ld $25, %call16(log10l)
define fp128 @libcall1_log10l() {
@@ -344,7 +344,7 @@ entry:
declare fp128 @log10l(fp128) #2
-; CHECK: libcall1_nearbyintl:
+; CHECK-LABEL: libcall1_nearbyintl:
; CHECK: ld $25, %call16(nearbyintl)
define fp128 @libcall1_nearbyintl() {
@@ -356,7 +356,7 @@ entry:
declare fp128 @nearbyintl(fp128) #1
-; CHECK: libcall1_floorl:
+; CHECK-LABEL: libcall1_floorl:
; CHECK: ld $25, %call16(floorl)
define fp128 @libcall1_floorl() {
@@ -368,7 +368,7 @@ entry:
declare fp128 @floorl(fp128) #1
-; CHECK: libcall1_sqrtl:
+; CHECK-LABEL: libcall1_sqrtl:
; CHECK: ld $25, %call16(sqrtl)
define fp128 @libcall1_sqrtl() {
@@ -380,7 +380,7 @@ entry:
declare fp128 @sqrtl(fp128) #2
-; CHECK: libcall1_rintl:
+; CHECK-LABEL: libcall1_rintl:
; CHECK: ld $25, %call16(rintl)
define fp128 @libcall1_rintl() {
@@ -392,7 +392,7 @@ entry:
declare fp128 @rintl(fp128) #1
-; CHECK: libcall_powil:
+; CHECK-LABEL: libcall_powil:
; CHECK: ld $25, %call16(__powitf2)
define fp128 @libcall_powil(fp128 %a, i32 %b) {
@@ -403,7 +403,7 @@ entry:
declare fp128 @llvm.powi.f128(fp128, i32) #3
-; CHECK: libcall2_copysignl:
+; CHECK-LABEL: libcall2_copysignl:
; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
; CHECK-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 63
; CHECK-DAG: ld $[[R0:[0-9]+]], %got_disp(gld1)
@@ -426,7 +426,7 @@ entry:
declare fp128 @copysignl(fp128, fp128) #1
-; CHECK: libcall2_powl:
+; CHECK-LABEL: libcall2_powl:
; CHECK: ld $25, %call16(powl)
define fp128 @libcall2_powl() {
@@ -439,7 +439,7 @@ entry:
declare fp128 @powl(fp128, fp128) #2
-; CHECK: libcall2_fmodl:
+; CHECK-LABEL: libcall2_fmodl:
; CHECK: ld $25, %call16(fmodl)
define fp128 @libcall2_fmodl() {
@@ -452,7 +452,7 @@ entry:
declare fp128 @fmodl(fp128, fp128) #2
-; CHECK: libcall3_fmal:
+; CHECK-LABEL: libcall3_fmal:
; CHECK: ld $25, %call16(fmal)
define fp128 @libcall3_fmal() {
@@ -466,7 +466,7 @@ entry:
declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4
-; CHECK: cmp_lt:
+; CHECK-LABEL: cmp_lt:
; CHECK: ld $25, %call16(__lttf2)
define i32 @cmp_lt(fp128 %a, fp128 %b) {
@@ -476,7 +476,7 @@ entry:
ret i32 %conv
}
-; CHECK: cmp_le:
+; CHECK-LABEL: cmp_le:
; CHECK: ld $25, %call16(__letf2)
define i32 @cmp_le(fp128 %a, fp128 %b) {
@@ -486,7 +486,7 @@ entry:
ret i32 %conv
}
-; CHECK: cmp_gt:
+; CHECK-LABEL: cmp_gt:
; CHECK: ld $25, %call16(__gttf2)
define i32 @cmp_gt(fp128 %a, fp128 %b) {
@@ -496,7 +496,7 @@ entry:
ret i32 %conv
}
-; CHECK: cmp_ge:
+; CHECK-LABEL: cmp_ge:
; CHECK: ld $25, %call16(__getf2)
define i32 @cmp_ge(fp128 %a, fp128 %b) {
@@ -506,7 +506,7 @@ entry:
ret i32 %conv
}
-; CHECK: cmp_eq:
+; CHECK-LABEL: cmp_eq:
; CHECK: ld $25, %call16(__eqtf2)
define i32 @cmp_eq(fp128 %a, fp128 %b) {
@@ -516,7 +516,7 @@ entry:
ret i32 %conv
}
-; CHECK: cmp_ne:
+; CHECK-LABEL: cmp_ne:
; CHECK: ld $25, %call16(__netf2)
define i32 @cmp_ne(fp128 %a, fp128 %b) {
@@ -526,7 +526,7 @@ entry:
ret i32 %conv
}
-; CHECK: load_LD_LD:
+; CHECK-LABEL: load_LD_LD:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $2, 0($[[R0]])
; CHECK: ld $4, 8($[[R0]])
@@ -537,7 +537,7 @@ entry:
ret fp128 %0
}
-; CHECK: load_LD_float:
+; CHECK-LABEL: load_LD_float:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gf1)
; CHECK: lw $4, 0($[[R0]])
; CHECK: ld $25, %call16(__extendsftf2)
@@ -550,7 +550,7 @@ entry:
ret fp128 %conv
}
-; CHECK: load_LD_double:
+; CHECK-LABEL: load_LD_double:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gd1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $25, %call16(__extenddftf2)
@@ -563,7 +563,7 @@ entry:
ret fp128 %conv
}
-; CHECK: store_LD_LD:
+; CHECK-LABEL: store_LD_LD:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]])
@@ -578,7 +578,7 @@ entry:
ret void
}
-; CHECK: store_LD_float:
+; CHECK-LABEL: store_LD_float:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $5, 8($[[R0]])
@@ -595,7 +595,7 @@ entry:
ret void
}
-; CHECK: store_LD_double:
+; CHECK-LABEL: store_LD_double:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $5, 8($[[R0]])
@@ -612,7 +612,7 @@ entry:
ret void
}
-; CHECK: select_LD:
+; CHECK-LABEL: select_LD:
; CHECK: movn $8, $6, $4
; CHECK: movn $9, $7, $4
; CHECK: move $2, $8
@@ -625,7 +625,7 @@ entry:
ret fp128 %cond
}
-; CHECK: selectCC_LD:
+; CHECK-LABEL: selectCC_LD:
; CHECK: move $[[R0:[0-9]+]], $11
; CHECK: move $[[R1:[0-9]+]], $10
; CHECK: move $[[R2:[0-9]+]], $9
Modified: llvm/trunk/test/CodeGen/Mips/mips64-libcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64-libcall.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64-libcall.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64-libcall.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Check that %add is not passed in an integer register.
;
-; HARD: callfloor:
+; HARD-LABEL: callfloor:
; HARD-NOT: dmfc1 $4
define double @callfloor(double %d) nounwind readnone {
@@ -19,7 +19,7 @@ declare double @floor(double) nounwind r
; Check call16.
;
-; SOFT: f64add:
+; SOFT-LABEL: f64add:
; SOFT: ld $25, %call16(__adddf3)
define double @f64add(double %a, double %b) {
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Sun Jul 14 01:24:09 2013
@@ -86,7 +86,7 @@ entry:
define i64 @f14(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
@@ -96,7 +96,7 @@ entry:
define i64 @f15(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
@@ -106,7 +106,7 @@ entry:
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
@@ -116,7 +116,7 @@ entry:
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
Modified: llvm/trunk/test/CodeGen/Mips/misha.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/misha.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/misha.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/misha.ll Sun Jul 14 01:24:09 2013
@@ -25,10 +25,10 @@ for.body:
%inc = add nsw i32 %i.010, 1
%cmp = icmp eq i32 %inc, %conv
br i1 %cmp, label %for.end, label %for.body
-; 16: sumc:
+; 16-LABEL: sumc:
; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
-; 16: sum:
+; 16-LABEL: sum:
; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
Modified: llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll Sun Jul 14 01:24:09 2013
@@ -8,16 +8,16 @@
@g0 = common global double 0.000000e+00, align 8
-; LE-PIC: test_ldc1:
+; LE-PIC-LABEL: test_ldc1:
; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
-; LE-STATIC: test_ldc1:
+; LE-STATIC-LABEL: test_ldc1:
; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_ldc1:
+; BE-PIC-LABEL: test_ldc1:
; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_ldc1:
+; CHECK-LDC1-SDC1-LABEL: test_ldc1:
; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
define double @test_ldc1() {
@@ -26,16 +26,16 @@ entry:
ret double %0
}
-; LE-PIC: test_sdc1:
+; LE-PIC-LABEL: test_sdc1:
; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
-; LE-STATIC: test_sdc1:
+; LE-STATIC-LABEL: test_sdc1:
; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_sdc1:
+; BE-PIC-LABEL: test_sdc1:
; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_sdc1:
+; CHECK-LDC1-SDC1-LABEL: test_sdc1:
; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
define void @test_sdc1(double %a) {
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Sun Jul 14 01:24:09 2013
@@ -27,7 +27,7 @@ entry:
%tmp = load i32* %b, align 4
ret i32 %tmp
-; CHECK: va1:
+; CHECK-LABEL: va1:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
@@ -53,7 +53,7 @@ entry:
%tmp = load double* %b, align 8
ret double %tmp
-; CHECK: va2:
+; CHECK-LABEL: va2:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
@@ -81,7 +81,7 @@ entry:
%tmp = load i32* %b, align 4
ret i32 %tmp
-; CHECK: va3:
+; CHECK-LABEL: va3:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
@@ -104,7 +104,7 @@ entry:
%tmp = load double* %b, align 8
ret double %tmp
-; CHECK: va4:
+; CHECK-LABEL: va4:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: sw $6, 32($sp)
@@ -132,7 +132,7 @@ entry:
%tmp = load i32* %d, align 4
ret i32 %tmp
-; CHECK: va5:
+; CHECK-LABEL: va5:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: lw $2, 36($sp)
@@ -158,7 +158,7 @@ entry:
%tmp = load double* %d, align 8
ret double %tmp
-; CHECK: va6:
+; CHECK-LABEL: va6:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
@@ -186,7 +186,7 @@ entry:
%tmp = load i32* %c, align 4
ret i32 %tmp
-; CHECK: va7:
+; CHECK-LABEL: va7:
; CHECK: addiu $sp, $sp, -24
; CHECK: lw $2, 40($sp)
}
@@ -209,7 +209,7 @@ entry:
%tmp = load double* %c, align 8
ret double %tmp
-; CHECK: va8:
+; CHECK-LABEL: va8:
; CHECK: addiu $sp, $sp, -32
; CHECK: addiu ${{[0-9]+}}, $sp, 48
; CHECK: ldc1 $f0, 48($sp)
@@ -235,7 +235,7 @@ entry:
%tmp = load i32* %d, align 4
ret i32 %tmp
-; CHECK: va9:
+; CHECK-LABEL: va9:
; CHECK: addiu $sp, $sp, -32
; CHECK: lw $2, 52($sp)
}
@@ -260,7 +260,7 @@ entry:
%tmp = load double* %d, align 8
ret double %tmp
-; CHECK: va10:
+; CHECK-LABEL: va10:
; CHECK: addiu $sp, $sp, -32
; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
Modified: llvm/trunk/test/CodeGen/Mips/private.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/private.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/private.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/private.ll Sun Jul 14 01:24:09 2013
@@ -3,14 +3,14 @@
; RUN: llc -march=mips < %s | FileCheck %s
define private void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
ret void
}
@baz = private global i32 4
define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: call16($foo)
; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
Modified: llvm/trunk/test/CodeGen/Mips/return-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/return-vector.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/return-vector.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/return-vector.ll Sun Jul 14 01:24:09 2013
@@ -30,7 +30,7 @@ entry:
%add7 = add i32 %add5, %add6
ret i32 %add7
-; CHECK: call_i8:
+; CHECK-LABEL: call_i8:
; CHECK: call16(i8)
; CHECK: addiu $4, $sp, 32
; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
@@ -56,7 +56,7 @@ entry:
%add3 = fadd float %add1, %add2
ret float %add3
-; CHECK: call_f4:
+; CHECK-LABEL: call_f4:
; CHECK: call16(f4)
; CHECK: addiu $4, $sp, 16
; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
@@ -78,7 +78,7 @@ entry:
%add3 = fadd double %add1, %add2
ret double %add3
-; CHECK: call_d4:
+; CHECK-LABEL: call_d4:
; CHECK: call16(d4)
; CHECK: addiu $4, $sp, 32
; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp)
@@ -109,7 +109,7 @@ entry:
%add3 = add i32 %add1, %add2
ret i32 %add3
-; CHECK: call_i4:
+; CHECK-LABEL: call_i4:
; CHECK: call16(i4)
; CHECK-NOT: lw
; CHECK: addu $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -126,7 +126,7 @@ entry:
%add1 = fadd float %v0, %v1
ret float %add1
-; CHECK: call_f2:
+; CHECK-LABEL: call_f2:
; CHECK: call16(f2)
; CHECK-NOT: lwc1
; CHECK: add.s $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -141,7 +141,7 @@ entry:
%add1 = fadd double %v0, %v1
ret double %add1
-; CHECK: call_d2:
+; CHECK-LABEL: call_d2:
; CHECK: call16(d2)
; CHECK-NOT: ldc1
; CHECK: add.d $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -158,7 +158,7 @@ define <8 x i32> @return_i8() {
entry:
ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK: return_i8:
+; CHECK-LABEL: return_i8:
; CHECK: sw $[[R0:[a-z0-9]+]], 28($4)
; CHECK: sw $[[R1:[a-z0-9]+]], 24($4)
; CHECK: sw $[[R2:[a-z0-9]+]], 20($4)
@@ -178,7 +178,7 @@ entry:
%vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
ret <4 x float> %vecins4
-; CHECK: return_f4:
+; CHECK-LABEL: return_f4:
; CHECK-DAG: lwc1 $[[R0:[a-z0-9]+]], 16($sp)
; CHECK-DAG: swc1 $[[R0]], 12($4)
; CHECK-DAG: sw $7, 8($4)
@@ -195,7 +195,7 @@ entry:
%vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
ret <4 x double> %vecins4
-; CHECK: return_d4:
+; CHECK-LABEL: return_d4:
; CHECK-DAG: sdc1 $[[R0:[a-z0-9]+]], 24($4)
; CHECK-DAG: sdc1 $[[R1:[a-z0-9]+]], 16($4)
; CHECK-DAG: sdc1 $[[R2:[a-z0-9]+]], 8($4)
@@ -212,7 +212,7 @@ define <4 x i32> @return_i4() {
entry:
ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK: return_i4:
+; CHECK-LABEL: return_i4:
; CHECK: addiu $2, $zero, 0
; CHECK: addiu $3, $zero, 1
; CHECK: addiu $4, $zero, 2
@@ -226,7 +226,7 @@ entry:
%vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
ret <2 x float> %vecins2
-; CHECK: return_f2:
+; CHECK-LABEL: return_f2:
; CHECK: mov.s $f0, $f12
; CHECK: mov.s $f2, $f14
}
@@ -238,7 +238,7 @@ entry:
%vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
ret <2 x double> %vecins2
-; CHECK: return_d2:
+; CHECK-LABEL: return_d2:
; CHECK: mov.d $f0, $f12
; CHECK: mov.d $f2, $f14
}
Modified: llvm/trunk/test/CodeGen/Mips/setcc-se.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setcc-se.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setcc-se.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setcc-se.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
@g1 = external global i32
-; CHECK: seteq0:
+; CHECK-LABEL: seteq0:
; CHECK: sltiu ${{[0-9]+}}, $4, 1
define i32 @seteq0(i32 %a) {
@@ -12,7 +12,7 @@ entry:
ret i32 %conv
}
-; CHECK: setne0:
+; CHECK-LABEL: setne0:
; CHECK: sltu ${{[0-9]+}}, $zero, $4
define i32 @setne0(i32 %a) {
@@ -22,7 +22,7 @@ entry:
ret i32 %conv
}
-; CHECK: slti_beq0:
+; CHECK-LABEL: slti_beq0:
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
@@ -39,7 +39,7 @@ if.end:
ret void
}
-; CHECK: slti_beq1:
+; CHECK-LABEL: slti_beq1:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq1(i32 %a) {
@@ -55,7 +55,7 @@ if.end:
ret void
}
-; CHECK: slti_beq2:
+; CHECK-LABEL: slti_beq2:
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
@@ -72,7 +72,7 @@ if.end:
ret void
}
-; CHECK: slti_beq3:
+; CHECK-LABEL: slti_beq3:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq3(i32 %a) {
@@ -88,7 +88,7 @@ if.end:
ret void
}
-; CHECK: sltiu_beq0:
+; CHECK-LABEL: sltiu_beq0:
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
@@ -105,7 +105,7 @@ if.end:
ret void
}
-; CHECK: sltiu_beq1:
+; CHECK-LABEL: sltiu_beq1:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq1(i32 %a) {
@@ -121,7 +121,7 @@ if.end:
ret void
}
-; CHECK: sltiu_beq2:
+; CHECK-LABEL: sltiu_beq2:
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
@@ -138,7 +138,7 @@ if.end:
ret void
}
-; CHECK: sltiu_beq3:
+; CHECK-LABEL: sltiu_beq3:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq3(i32 %a) {
Modified: llvm/trunk/test/CodeGen/Mips/sint-fp-store_pattern.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/sint-fp-store_pattern.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/sint-fp-store_pattern.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/sint-fp-store_pattern.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
@gint_ = external global i32
@gLL_ = external global i64
-; 32: store_int_float_:
+; 32-LABEL: store_int_float_:
; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: swc1 $f[[R0]],
@@ -15,10 +15,10 @@ entry:
ret void
}
-; 32: store_int_double_:
+; 32-LABEL: store_int_double_:
; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: swc1 $f[[R0]],
-; 64: store_int_double_:
+; 64-LABEL: store_int_double_:
; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: swc1 $f[[R0]],
@@ -29,7 +29,7 @@ entry:
ret void
}
-; 64: store_LL_float_:
+; 64-LABEL: store_LL_float_:
; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: sdc1 $f[[R0]],
@@ -40,7 +40,7 @@ entry:
ret void
}
-; 64: store_LL_double_:
+; 64-LABEL: store_LL_double_:
; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: sdc1 $f[[R0]],
Modified: llvm/trunk/test/CodeGen/Mips/stackcoloring.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/stackcoloring.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/stackcoloring.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/stackcoloring.ll Sun Jul 14 01:24:09 2013
@@ -2,7 +2,7 @@
@g1 = external global i32*
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
; CHECK: lw ${{[0-9]+}}, %got(g1)
; CHECK: # %for.body
; CHECK: # %for.end
Modified: llvm/trunk/test/CodeGen/Mips/stchar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/stchar.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/stchar.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/stchar.ll Sun Jul 14 01:24:09 2013
@@ -50,8 +50,8 @@ entry:
%conv1.i = sext i8 %3 to i32
%call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
ret void
-; 16_b: test:
-; 16_h: test:
+; 16_b-LABEL: test:
+; 16_h-LABEL: test:
; 16_b: sb ${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
; 16_b: lb ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
; 16_h: sh ${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
Modified: llvm/trunk/test/CodeGen/Mips/tls-models.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls-models.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tls-models.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tls-models.ll Sun Jul 14 01:24:09 2013
@@ -20,9 +20,9 @@ entry:
ret i32* @external_gd
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
- ; CHECK-NONPIC: f1:
+ ; CHECK-NONPIC-LABEL: f1:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f1:
+ ; CHECK-PIC-LABEL: f1:
; CHECK-PIC: %tlsgd
}
@@ -31,9 +31,9 @@ entry:
ret i32* @internal_gd
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; CHECK-NONPIC: f2:
+ ; CHECK-NONPIC-LABEL: f2:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f2:
+ ; CHECK-PIC-LABEL: f2:
; CHECK-PIC: %tlsldm
}
@@ -45,9 +45,9 @@ entry:
ret i32* @external_ld
; Non-PIC code can use initial exec, PIC should use local dynamic.
- ; CHECK-NONPIC: f3:
+ ; CHECK-NONPIC-LABEL: f3:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f3:
+ ; CHECK-PIC-LABEL: f3:
; CHECK-PIC: %tlsldm
}
@@ -56,9 +56,9 @@ entry:
ret i32* @internal_ld
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; CHECK-NONPIC: f4:
+ ; CHECK-NONPIC-LABEL: f4:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f4:
+ ; CHECK-PIC-LABEL: f4:
; CHECK-PIC: %tlsldm
}
@@ -70,9 +70,9 @@ entry:
ret i32* @external_ie
; Non-PIC and PIC code will use initial exec as specified.
- ; CHECK-NONPIC: f5:
+ ; CHECK-NONPIC-LABEL: f5:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f5:
+ ; CHECK-PIC-LABEL: f5:
; CHECK-PIC: %gottprel
}
@@ -81,9 +81,9 @@ entry:
ret i32* @internal_ie
; Non-PIC code can use local exec, PIC code use initial exec as specified.
- ; CHECK-NONPIC: f6:
+ ; CHECK-NONPIC-LABEL: f6:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f6:
+ ; CHECK-PIC-LABEL: f6:
; CHECK-PIC: %gottprel
}
@@ -95,9 +95,9 @@ entry:
ret i32* @external_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f7:
+ ; CHECK-NONPIC-LABEL: f7:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f7:
+ ; CHECK-PIC-LABEL: f7:
; CHECK-PIC: %tprel_hi
}
@@ -106,8 +106,8 @@ entry:
ret i32* @internal_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f8:
+ ; CHECK-NONPIC-LABEL: f8:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f8:
+ ; CHECK-PIC-LABEL: f8:
; CHECK-PIC: %tprel_hi
}
Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tls.ll Sun Jul 14 01:24:09 2013
@@ -13,14 +13,14 @@ entry:
%tmp = load i32* @t1, align 4
ret i32 %tmp
-; PIC: f1:
+; PIC-LABEL: f1:
; PIC-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
; PIC-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
; PIC-DAG: addiu $4, $[[R0]], %tlsgd(t1)
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
-; STATIC: f1:
+; STATIC-LABEL: f1:
; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
; STATIC: rdhwr $3, $29
@@ -36,19 +36,19 @@ entry:
%tmp = load i32* @t2, align 4
ret i32 %tmp
-; PIC: f2:
+; PIC-LABEL: f2:
; PIC-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
; PIC-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
; PIC-DAG: addiu $4, $[[R0]], %tlsgd(t2)
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
-; STATICGP: f2:
+; STATICGP-LABEL: f2:
; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
-; STATIC: f2:
+; STATIC-LABEL: f2:
; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATIC: rdhwr $3, $29
@@ -61,7 +61,7 @@ entry:
define i32 @f3() nounwind {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
; PIC: jalr $25
Modified: llvm/trunk/test/CodeGen/Mips/tnaked.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tnaked.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tnaked.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tnaked.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@ entry:
}
; CHECK: .ent tnaked
-; CHECK: tnaked:
+; CHECK-LABEL: tnaked:
; CHECK-NOT: .frame {{.*}}
; CHECK-NOT: .mask {{.*}}
; CHECK-NOT: .fmask {{.*}}
@@ -19,7 +19,7 @@ entry:
}
; CHECK: .ent tnonaked
-; CHECK: tnonaked:
+; CHECK-LABEL: tnonaked:
; CHECK: .frame $fp,8,$ra
; CHECK: .mask 0x40000000,-4
; CHECK: .fmask 0x00000000,0
Modified: llvm/trunk/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2009-09-18-carrybit.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2009-09-18-carrybit.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2009-09-18-carrybit.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6
define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: subfc
; CHECK: subfe
; CHECK: subfc
Modified: llvm/trunk/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8
define i32 @main() nounwind {
entry:
; Make sure we're generating references using the red zone
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: stw r2, -12(r1)
%retval = alloca i32
%0 = alloca i32
Modified: llvm/trunk/test/CodeGen/PowerPC/addc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addc.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounw
entry:
%tmp.2 = add i64 %b, %a ; <i64> [#uses=1]
ret i64 %tmp.2
-; CHECK: add_ll:
+; CHECK-LABEL: add_ll:
; CHECK: addc r4, r6, r4
; CHECK: adde r3, r5, r3
; CHECK: blr
@@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind {
entry:
%tmp.1 = add i64 %a, 5 ; <i64> [#uses=1]
ret i64 %tmp.1
-; CHECK: add_l_5:
+; CHECK-LABEL: add_l_5:
; CHECK: addic r4, r4, 5
; CHECK: addze r3, r3
; CHECK: blr
@@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind {
entry:
%tmp.1 = add i64 %a, -5 ; <i64> [#uses=1]
ret i64 %tmp.1
-; CHECK: add_l_m5:
+; CHECK-LABEL: add_l_m5:
; CHECK: addic r4, r4, -5
; CHECK: addme r3, r3
; CHECK: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll Sun Jul 14 01:24:09 2013
@@ -20,7 +20,7 @@ unequal:
ret i8* %ptr
}
-; CHECK: func1:
+; CHECK-LABEL: func1:
; CHECK: cmpld {{[0-9]+}}, 4, 5
; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
@@ -61,7 +61,7 @@ unequal:
ret i8* %array2_ptr
}
-; CHECK: func2:
+; CHECK-LABEL: func2:
; CHECK: addi [[REG1:[0-9]+]], 1, 64
; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
@@ -107,7 +107,7 @@ unequal:
ret i8* %array2_ptr
}
-; CHECK: func3:
+; CHECK-LABEL: func3:
; CHECK: addi [[REG1:[0-9]+]], 1, 64
; CHECK: addi [[REG2:[0-9]+]], 1, 48
; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
@@ -156,7 +156,7 @@ unequal:
ret i8* %array2_ptr
}
-; CHECK: func4:
+; CHECK-LABEL: func4:
; CHECK: addi [[REG1:[0-9]+]], 1, 128
; CHECK: ld [[REG2:[0-9]+]], 120(1)
; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s
define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
%tmp = atomicrmw add i32* %mem, i32 %val monotonic
; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem,
}
define i32 @exchange_and_cmp(i32* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
; CHECK: lwarx
%tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic
; CHECK: stwcx.
@@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem)
}
define i32 @exchange(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
; CHECK: lwarx
%tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
; CHECK: stwcx.
Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Sun Jul 14 01:24:09 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=ppc64 | FileCheck %s
define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
; CHECK: ldarx
%tmp = atomicrmw add i64* %mem, i64 %val monotonic
; CHECK: stdcx.
@@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem,
}
define i64 @exchange_and_cmp(i64* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
; CHECK: ldarx
%tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
; CHECK: stdcx.
@@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem)
}
define i64 @exchange(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
; CHECK: ldarx
%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
; CHECK: stdcx.
Modified: llvm/trunk/test/CodeGen/PowerPC/complex-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/complex-return.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/complex-return.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/complex-return.ll Sun Jul 14 01:24:09 2013
@@ -23,7 +23,7 @@ entry:
ret { ppc_fp128, ppc_fp128 } %0
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: lfd 3
; CHECK: lfd 4
; CHECK: lfd 2
@@ -49,7 +49,7 @@ entry:
ret { float, float } %0
}
-; CHECK: oof:
+; CHECK-LABEL: oof:
; CHECK: lfs 2
; CHECK: lfs 1
Modified: llvm/trunk/test/CodeGen/PowerPC/dbg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dbg.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/dbg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/dbg.ll Sun Jul 14 01:24:09 2013
@@ -1,5 +1,5 @@
; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll Sun Jul 14 01:24:09 2013
@@ -25,7 +25,7 @@ entry:
ret void
}
-; CHECK: callee:
+; CHECK-LABEL: callee:
; CHECK: std 4,
; CHECK-NOT: std 5,
; CHECK-NOT: std 6,
@@ -42,7 +42,7 @@ entry:
ret void
}
-; CHECK: caller:
+; CHECK-LABEL: caller:
; CHECK: addi 4,
; CHECK-NOT: std 5,
; CHECK-NOT: std 6,
Modified: llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Sun Jul 14 01:24:09 2013
@@ -6,9 +6,9 @@
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
-; PIC: foo:
-; STATIC: foo:
-; PPC64: foo:
+; PIC-LABEL: foo:
+; STATIC-LABEL: foo:
+; PPC64-LABEL: foo:
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64-toc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-toc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-toc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-toc.ll Sun Jul 14 01:24:09 2013
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux
define i64 @access_int64(i64 %a) nounwind readonly {
entry:
-; CHECK: access_int64:
+; CHECK-LABEL: access_int64:
; CHECK-NEXT: .align 3
; CHECK-NEXT: .quad .L.access_int64
; CHECK-NEXT: .quad .TOC. at tocbase
@@ -23,7 +23,7 @@ entry:
define i64 @internal_static_var(i64 %a) nounwind {
entry:
-; CHECK: internal_static_var:
+; CHECK-LABEL: internal_static_var:
; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
%0 = load i64* @internal_static_var.x, align 8
%cmp = icmp eq i64 %0, %a
@@ -33,7 +33,7 @@ entry:
define i32 @access_double(double %a) nounwind readnone {
entry:
-; CHECK: access_double:
+; CHECK-LABEL: access_double:
; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
%cmp = fcmp oeq double %a, 2.000000e+00
%conv = zext i1 %cmp to i32
@@ -43,7 +43,7 @@ entry:
define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
entry:
-; CHECK: access_double_array:
+; CHECK-LABEL: access_double_array:
%idxprom = sext i32 %i to i64
%arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
%0 = load double* %arrayidx, align 8
Modified: llvm/trunk/test/CodeGen/PowerPC/pr13891.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr13891.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr13891.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr13891.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux
%struct.foo = type { i8, i8 }
define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
-; CHECK: _Z5check3foos:
+; CHECK-LABEL: _Z5check3foos:
; CHECK: sth 3, {{[0-9]+}}(1)
; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
entry:
Modified: llvm/trunk/test/CodeGen/PowerPC/rounding-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/rounding-ops.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/rounding-ops.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/rounding-ops.ll Sun Jul 14 01:24:09 2013
@@ -10,7 +10,7 @@ define float @test1(float %x) nounwind
; CHECK-LABEL: test1:
; CHECK: frim 1, 1
-; CHECK-FM: test1:
+; CHECK-FM-LABEL: test1:
; CHECK-FM: frim 1, 1
}
@@ -23,7 +23,7 @@ define double @test2(double %x) nounwind
; CHECK-LABEL: test2:
; CHECK: frim 1, 1
-; CHECK-FM: test2:
+; CHECK-FM-LABEL: test2:
; CHECK-FM: frim 1, 1
}
@@ -36,7 +36,7 @@ define float @test3(float %x) nounwind
; CHECK-LABEL: test3:
; CHECK-NOT: frin
-; CHECK-FM: test3:
+; CHECK-FM-LABEL: test3:
; CHECK-FM: frin 1, 1
}
@@ -49,7 +49,7 @@ define double @test4(double %x) nounwind
; CHECK-LABEL: test4:
; CHECK-NOT: frin
-; CHECK-FM: test4:
+; CHECK-FM-LABEL: test4:
; CHECK-FM: frin 1, 1
}
@@ -62,7 +62,7 @@ define float @test5(float %x) nounwind
; CHECK-LABEL: test5:
; CHECK: frip 1, 1
-; CHECK-FM: test5:
+; CHECK-FM-LABEL: test5:
; CHECK-FM: frip 1, 1
}
@@ -75,7 +75,7 @@ define double @test6(double %x) nounwind
; CHECK-LABEL: test6:
; CHECK: frip 1, 1
-; CHECK-FM: test6:
+; CHECK-FM-LABEL: test6:
; CHECK-FM: frip 1, 1
}
@@ -88,7 +88,7 @@ define float @test9(float %x) nounwind
; CHECK-LABEL: test9:
; CHECK: friz 1, 1
-; CHECK-FM: test9:
+; CHECK-FM-LABEL: test9:
; CHECK-FM: friz 1, 1
}
@@ -101,7 +101,7 @@ define double @test10(double %x) nounwin
; CHECK-LABEL: test10:
; CHECK: friz 1, 1
-; CHECK-FM: test10:
+; CHECK-FM-LABEL: test10:
; CHECK-FM: friz 1, 1
}
@@ -115,7 +115,7 @@ define void @test11(float %x, float* %y)
; CHECK-LABEL: test11:
; CHECK-NOT: frin
-; CHECK-FM: test11:
+; CHECK-FM-LABEL: test11:
; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
@@ -134,7 +134,7 @@ define void @test12(double %x, double* %
; CHECK-LABEL: test12:
; CHECK-NOT: frin
-; CHECK-FM: test12:
+; CHECK-FM-LABEL: test12:
; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
Modified: llvm/trunk/test/CodeGen/PowerPC/svr4-redzone.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/svr4-redzone.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/svr4-redzone.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/svr4-redzone.ll Sun Jul 14 01:24:09 2013
@@ -7,11 +7,11 @@ entry:
%0 = add i32 1, 2
ret void
}
-; PPC32: regalloc:
+; PPC32-LABEL: regalloc:
; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
; PPC32: blr
-; PPC64: regalloc:
+; PPC64-LABEL: regalloc:
; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
; PPC64: blr
@@ -20,10 +20,10 @@ entry:
%0 = alloca i8, i32 4
ret void
}
-; PPC32: smallstack:
+; PPC32-LABEL: smallstack:
; PPC32: stwu 1, -16(1)
-; PPC64: smallstack:
+; PPC64-LABEL: smallstack:
; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
; PPC64: blr
@@ -32,8 +32,8 @@ entry:
%0 = alloca i8, i32 230
ret void
}
-; PPC32: bigstack:
+; PPC32-LABEL: bigstack:
; PPC32: stwu 1, -240(1)
-; PPC64: bigstack:
+; PPC64-LABEL: bigstack:
; PPC64: stdu 1, -352(1)
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-2.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-2.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freeb
@a = thread_local global i32 0, align 4
-;CHECK: localexec:
+;CHECK-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
;CHECK: addis [[REG1:[0-9]+]], 13, a at tprel@ha
Modified: llvm/trunk/test/CodeGen/PowerPC/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls.ll Sun Jul 14 01:24:09 2013
@@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freeb
@a = thread_local global i32 0, align 4
-;OPT0: localexec:
-;OPT1: localexec:
+;OPT0-LABEL: localexec:
+;OPT1-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
;OPT0: addis [[REG1:[0-9]+]], 13, a at tprel@ha
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_cmp.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_cmp.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_cmp.ll Sun Jul 14 01:24:09 2013
@@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x,
%sext = sext <2 x i1> %cmp to <2 x i8>
ret <2 x i8> %sext
}
-; CHECK: v2si8_cmp:
+; CHECK-LABEL: v2si8_cmp:
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x,
%sext = sext <4 x i1> %cmp to <4 x i8>
ret <4 x i8> %sext
}
-; CHECK: v4si8_cmp:
+; CHECK-LABEL: v4si8_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x,
%sext = sext <8 x i1> %cmp to <8 x i8>
ret <8 x i8> %sext
}
-; CHECK: v8si8_cmp:
+; CHECK-LABEL: v8si8_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_eq:
+; CHECK-LABEL: v16si8_cmp_eq:
; CHECK: vcmpequb 2, 2, 3
define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -52,7 +52,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_ne:
+; CHECK-LABEL: v16si8_cmp_ne:
; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
@@ -62,7 +62,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_le:
+; CHECK-LABEL: v16si8_cmp_le:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -73,7 +73,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_le:
+; CHECK-LABEL: v16ui8_cmp_le:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -84,7 +84,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_lt:
+; CHECK-LABEL: v16si8_cmp_lt:
; CHECK: vcmpgtsb 2, 3, 2
define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -93,7 +93,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_lt:
+; CHECK-LABEL: v16ui8_cmp_lt:
; CHECK: vcmpgtub 2, 3, 2
define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -102,7 +102,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_gt:
+; CHECK-LABEL: v16si8_cmp_gt:
; CHECK: vcmpgtsb 2, 2, 3
define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -111,7 +111,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_gt:
+; CHECK-LABEL: v16ui8_cmp_gt:
; CHECK: vcmpgtub 2, 2, 3
define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -120,7 +120,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_ge:
+; CHECK-LABEL: v16si8_cmp_ge:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -131,7 +131,7 @@ entry:
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_ge:
+; CHECK-LABEL: v16ui8_cmp_ge:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %
%sext = sext <32 x i1> %cmp to <32 x i8>
ret <32 x i8> %sext
}
-; CHECK: v32si8_cmp:
+; CHECK-LABEL: v32si8_cmp:
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %
%sext = sext <2 x i1> %cmp to <2 x i16>
ret <2 x i16> %sext
}
-; CHECK: v2si16_cmp:
+; CHECK-LABEL: v2si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %
%sext = sext <4 x i1> %cmp to <4 x i16>
ret <4 x i16> %sext
}
-; CHECK: v4si16_cmp:
+; CHECK-LABEL: v4si16_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -173,7 +173,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_eq:
+; CHECK-LABEL: v8si16_cmp_eq:
; CHECK: vcmpequh 2, 2, 3
define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -182,7 +182,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_ne:
+; CHECK-LABEL: v8si16_cmp_ne:
; CHECK: vcmpequh [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
@@ -192,7 +192,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_le:
+; CHECK-LABEL: v8si16_cmp_le:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -203,7 +203,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_le:
+; CHECK-LABEL: v8ui16_cmp_le:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -214,7 +214,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_lt:
+; CHECK-LABEL: v8si16_cmp_lt:
; CHECK: vcmpgtsh 2, 3, 2
define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -223,7 +223,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_lt:
+; CHECK-LABEL: v8ui16_cmp_lt:
; CHECK: vcmpgtuh 2, 3, 2
define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -232,7 +232,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_gt:
+; CHECK-LABEL: v8si16_cmp_gt:
; CHECK: vcmpgtsh 2, 2, 3
define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -241,7 +241,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_gt:
+; CHECK-LABEL: v8ui16_cmp_gt:
; CHECK: vcmpgtuh 2, 2, 3
define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -250,7 +250,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_ge:
+; CHECK-LABEL: v8si16_cmp_ge:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -261,7 +261,7 @@ entry:
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_ge:
+; CHECK-LABEL: v8ui16_cmp_ge:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16
%sext = sext <16 x i1> %cmp to <16 x i16>
ret <16 x i16> %sext
}
-; CHECK: v16si16_cmp:
+; CHECK-LABEL: v16si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16
%sext = sext <32 x i1> %cmp to <32 x i16>
ret <32 x i16> %sext
}
-; CHECK: v32si16_cmp:
+; CHECK-LABEL: v32si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %
%sext = sext <2 x i1> %cmp to <2 x i32>
ret <2 x i32> %sext
}
-; CHECK: v2si32_cmp:
+; CHECK-LABEL: v2si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -306,7 +306,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_eq:
+; CHECK-LABEL: v4si32_cmp_eq:
; CHECK: vcmpequw 2, 2, 3
define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -315,7 +315,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_ne:
+; CHECK-LABEL: v4si32_cmp_ne:
; CHECK: vcmpequw [[RCMP:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RCMP]], [[RCMP]]
@@ -325,7 +325,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_le:
+; CHECK-LABEL: v4si32_cmp_le:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -336,7 +336,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_le:
+; CHECK-LABEL: v4ui32_cmp_le:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -347,7 +347,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_lt:
+; CHECK-LABEL: v4si32_cmp_lt:
; CHECK: vcmpgtsw 2, 3, 2
define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -356,7 +356,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_lt:
+; CHECK-LABEL: v4ui32_cmp_lt:
; CHECK: vcmpgtuw 2, 3, 2
define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -365,7 +365,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_gt:
+; CHECK-LABEL: v4si32_cmp_gt:
; CHECK: vcmpgtsw 2, 2, 3
define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -374,7 +374,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_gt:
+; CHECK-LABEL: v4ui32_cmp_gt:
; CHECK: vcmpgtuw 2, 2, 3
define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -383,7 +383,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_ge:
+; CHECK-LABEL: v4si32_cmp_ge:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -394,7 +394,7 @@ entry:
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_ge:
+; CHECK-LABEL: v4ui32_cmp_ge:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
@@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %
%sext = sext <8 x i1> %cmp to <8 x i32>
ret <8 x i32> %sext
}
-; CHECK: v8si32_cmp:
+; CHECK-LABEL: v8si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32
%sext = sext <16 x i1> %cmp to <16 x i32>
ret <16 x i32> %sext
}
-; CHECK: v16si32_cmp:
+; CHECK-LABEL: v16si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32
%sext = sext <32 x i1> %cmp to <32 x i32>
ret <32 x i32> %sext
}
-; CHECK: v32si32_cmp:
+; CHECK-LABEL: v32si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -445,7 +445,7 @@ entry:
%0 = bitcast <2 x i32> %sext to <2 x float>
ret <2 x float> %0
}
-; CHECK: v2f32_cmp:
+; CHECK-LABEL: v2f32_cmp:
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -458,7 +458,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_eq:
+; CHECK-LABEL: v4f32_cmp_eq:
; CHECK: vcmpeqfp 2, 2, 3
define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -468,7 +468,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_ne:
+; CHECK-LABEL: v4f32_cmp_ne:
; CHECK: vcmpeqfp [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
@@ -479,7 +479,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_le:
+; CHECK-LABEL: v4f32_cmp_le:
; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
@@ -491,7 +491,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_lt:
+; CHECK-LABEL: v4f32_cmp_lt:
; CHECK: vcmpgtfp 2, 3, 2
define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -501,7 +501,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_ge:
+; CHECK-LABEL: v4f32_cmp_ge:
; CHECK: vcmpgefp 2, 2, 3
define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -511,7 +511,7 @@ entry:
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_gt:
+; CHECK-LABEL: v4f32_cmp_gt:
; CHECK: vcmpgtfp 2, 2, 3
@@ -522,6 +522,6 @@ entry:
%0 = bitcast <8 x i32> %sext to <8 x float>
ret <8 x float> %0
}
-; CHECK: v8f32_cmp:
+; CHECK-LABEL: v8f32_cmp:
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_conv.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_conv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_conv.ll Sun Jul 14 01:24:09 2013
@@ -17,7 +17,7 @@ entry:
store <4 x i32> %1, <4 x i32>* %y, align 16
ret void
}
-;CHECK: v4f32_to_v4i32:
+;CHECK-LABEL: v4f32_to_v4i32:
;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
@@ -29,7 +29,7 @@ entry:
store <4 x i32> %1, <4 x i32>* %y, align 16
ret void
}
-;CHECK: v4f32_to_v4u32:
+;CHECK-LABEL: v4f32_to_v4u32:
;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
@@ -41,7 +41,7 @@ entry:
store <4 x float> %1, <4 x float>* %y, align 16
ret void
}
-;CHECK: v4i32_to_v4f32:
+;CHECK-LABEL: v4i32_to_v4f32:
;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
@@ -53,5 +53,5 @@ entry:
store <4 x float> %1, <4 x float>* %y, align 16
ret void
}
-;CHECK: v4u32_to_v4f32:
+;CHECK-LABEL: v4u32_to_v4f32:
;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll Sun Jul 14 01:24:09 2013
@@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16
%c = sext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
@@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16
%c = zext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_zext_in_reg:
+; CHECK-LABEL: v16si8_zext_in_reg:
; CHECK: vspltisb [[VMASK:[0-9]+]], 15
; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8
%c = sext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
@@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8
%c = zext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_zext_in_reg:
+; CHECK-LABEL: v8si16_zext_in_reg:
; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4
%c = sext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
; CHECK: vslw
; CHECK: vsraw
; CHECK: blr
@@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4
%c = zext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_zext_in_reg:
+; CHECK-LABEL: v4si32_zext_in_reg:
; CHECK: vspltisw [[VMASK:[0-9]+]], -16
; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_rounding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_rounding.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_rounding.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_rounding.ll Sun Jul 14 01:24:09 2013
@@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x do
%t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: floor_v2f64:
+; CHECK-LABEL: floor_v2f64:
; CHECK: frim
; CHECK: frim
@@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x do
%t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: floor_v4f64:
+; CHECK-LABEL: floor_v4f64:
; CHECK: frim
; CHECK: frim
; CHECK: frim
@@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x dou
%t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: ceil_v2f64:
+; CHECK-LABEL: ceil_v2f64:
; CHECK: frip
; CHECK: frip
@@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x dou
%t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: ceil_v4f64:
+; CHECK-LABEL: ceil_v4f64:
; CHECK: frip
; CHECK: frip
; CHECK: frip
@@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x do
%t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: trunc_v2f64:
+; CHECK-LABEL: trunc_v2f64:
; CHECK: friz
; CHECK: friz
@@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x do
%t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: trunc_v4f64:
+; CHECK-LABEL: trunc_v4f64:
; CHECK: friz
; CHECK: friz
; CHECK: friz
@@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2
%t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: nearbyint_v2f64:
+; CHECK-LABEL: nearbyint_v2f64:
; CHECK: bl nearbyint
; CHECK: bl nearbyint
@@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4
%t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: nearbyint_v4f64:
+; CHECK-LABEL: nearbyint_v4f64:
; CHECK: bl nearbyint
; CHECK: bl nearbyint
; CHECK: bl nearbyint
@@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x flo
%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: floor_v4f32:
+; CHECK-LABEL: floor_v4f32:
; CHECK: vrfim
declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
@@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x flo
%t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: floor_v8f32:
+; CHECK-LABEL: floor_v8f32:
; CHECK: vrfim
; CHECK: vrfim
@@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x floa
%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: ceil_v4f32:
+; CHECK-LABEL: ceil_v4f32:
; CHECK: vrfip
declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
@@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x floa
%t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: ceil_v8f32:
+; CHECK-LABEL: ceil_v8f32:
; CHECK: vrfip
; CHECK: vrfip
@@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x flo
%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: trunc_v4f32:
+; CHECK-LABEL: trunc_v4f32:
; CHECK: vrfiz
declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
@@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x flo
%t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: trunc_v8f32:
+; CHECK-LABEL: trunc_v8f32:
; CHECK: vrfiz
; CHECK: vrfiz
@@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x
%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: nearbyint_v4f32:
+; CHECK-LABEL: nearbyint_v4f32:
; CHECK: vrfin
declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
@@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x
%t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: nearbyint_v8f32:
+; CHECK-LABEL: nearbyint_v8f32:
; CHECK: vrfin
; CHECK: vrfin
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_sqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_sqrt.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_sqrt.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_sqrt.ll Sun Jul 14 01:24:09 2013
@@ -18,7 +18,7 @@ entry:
ret <2 x float> %sqrt
}
; sqrt (<2 x float>) is promoted to sqrt (<4 x float>)
-; CHECK: v2f32_sqrt:
+; CHECK-LABEL: v2f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -29,7 +29,7 @@ entry:
%sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
ret <4 x float> %sqrt
}
-; CHECK: v4f32_sqrt:
+; CHECK-LABEL: v4f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -40,7 +40,7 @@ entry:
%sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
ret <8 x float> %sqrt
}
-; CHECK: v8f32_sqrt:
+; CHECK-LABEL: v8f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -55,7 +55,7 @@ entry:
%sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x)
ret <2 x double> %sqrt
}
-; CHECK: v2f64_sqrt:
+; CHECK-LABEL: v2f64_sqrt:
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
@@ -64,7 +64,7 @@ entry:
%sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
ret <4 x double> %sqrt
}
-; CHECK: v4f64_sqrt:
+; CHECK-LABEL: v4f64_sqrt:
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll Sun Jul 14 01:24:09 2013
@@ -109,7 +109,7 @@ declare i32 @func(i32*)
define i32 @restore_add(i32 %a, i32 %b) {
entry:
-;CHECK: restore_add:
+;CHECK-LABEL: restore_add:
;CHECK: jmp %i7+8
;CHECK: restore %o0, %i1, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
@@ -119,7 +119,7 @@ entry:
define i32 @restore_add_imm(i32 %a) {
entry:
-;CHECK: restore_add_imm:
+;CHECK-LABEL: restore_add_imm:
;CHECK: jmp %i7+8
;CHECK: restore %o0, 20, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
@@ -129,7 +129,7 @@ entry:
define i32 @restore_or(i32 %a) {
entry:
-;CHECK: restore_or:
+;CHECK-LABEL: restore_or:
;CHECK: jmp %i7+8
;CHECK: restore %g0, %o0, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
@@ -138,7 +138,7 @@ entry:
define i32 @restore_or_imm(i32 %a) {
entry:
-;CHECK: restore_or_imm:
+;CHECK-LABEL: restore_or_imm:
;CHECK: or %o0, 20, %i0
;CHECK: jmp %i7+8
;CHECK: restore %g0, %g0, %g0
Modified: llvm/trunk/test/CodeGen/SPARC/64bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/64bit.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/64bit.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/64bit.ll Sun Jul 14 01:24:09 2013
@@ -1,10 +1,10 @@
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
; RUN: llc < %s -march=sparcv9 | FileCheck %s -check-prefix=OPT
-; CHECK: ret2:
+; CHECK-LABEL: ret2:
; CHECK: or %g0, %i1, %i0
-; OPT: ret2:
+; OPT-LABEL: ret2:
; OPT: jmp %o7+8
; OPT: or %g0, %o1, %o0
define i64 @ret2(i64 %a, i64 %b) {
@@ -14,7 +14,7 @@ define i64 @ret2(i64 %a, i64 %b) {
; CHECK: shl_imm
; CHECK: sllx %i0, 7, %i0
-; OPT: shl_imm:
+; OPT-LABEL: shl_imm:
; OPT: jmp %o7+8
; OPT: sllx %o0, 7, %o0
define i64 @shl_imm(i64 %a) {
@@ -25,7 +25,7 @@ define i64 @shl_imm(i64 %a) {
; CHECK: sra_reg
; CHECK: srax %i0, %i1, %i0
-; OPT: sra_reg:
+; OPT-LABEL: sra_reg:
; OPT: jmp %o7+8
; OPT: srax %o0, %o1, %o0
define i64 @sra_reg(i64 %a, i64 %b) {
@@ -271,11 +271,11 @@ define double @bitcast_f64_i64(i64 %x) {
ret double %y
}
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
; CHECK: stx %g0, [%i0]
; CHECK: stx %g0, [%i1+8]
-; OPT: store_zero:
+; OPT-LABEL: store_zero:
; OPT: stx %g0, [%o0]
; OPT: stx %g0, [%o1+8]
define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
Modified: llvm/trunk/test/CodeGen/SPARC/basictest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/basictest.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/basictest.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/basictest.ll Sun Jul 14 01:24:09 2013
@@ -25,7 +25,7 @@ define i32 @test2(i32 %X, i32 %Y) {
; CHECK: xnor %o0, %o1, %o0
}
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
; CHECK: st %g0, [%o0]
; CHECK: st %g0, [%o1+4]
define i32 @store_zero(i32* %a, i32* %b) {
Modified: llvm/trunk/test/CodeGen/SPARC/blockaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/blockaddr.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/blockaddr.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/blockaddr.ll Sun Jul 14 01:24:09 2013
@@ -15,13 +15,13 @@ entry:
ret i8* %x
}
-; abs32: func_block_addr:
+; abs32-LABEL: func_block_addr:
; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs32: call dummy
; abs32: add [[R]], %lo([[BLK]]), %o0
; abs32: jmp %o0
-; abs44: func_block_addr:
+; abs44-LABEL: func_block_addr:
; abs44: sethi %h44([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs44: add [[R]], %m44([[BLK]]), [[R1:%[gilo][0-7]]]
; abs44: sllx [[R1]], 12, [[R2:%[gilo][0-7]]]
@@ -29,7 +29,7 @@ entry:
; abs44: add [[R2]], %l44([[BLK]]), %o0
; abs44: jmp %o0
-; abs64: func_block_addr:
+; abs64-LABEL: func_block_addr:
; abs64: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs64: add [[R]], %lo([[BLK]]), [[R1:%[gilo][0-7]]]
; abs64: sethi %hh([[BLK]]), [[R2:%[gilo][0-7]]]
Modified: llvm/trunk/test/CodeGen/SPARC/float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/float.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/float.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/float.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@
; V8: call get_double
; V8: fnegs %f0, %f0
-; V8-UNOPT: test_neg:
+; V8-UNOPT-LABEL: test_neg:
; V8-UNOPT: fnegs
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
@@ -26,7 +26,7 @@ entry:
; V8-LABEL: test_abs:
; V8: fabss %f0, %f0
-; V8-UNOPT: test_abs:
+; V8-UNOPT-LABEL: test_abs:
; V8-UNOPT: fabss
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
Modified: llvm/trunk/test/CodeGen/SPARC/leafproc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/leafproc.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/leafproc.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/leafproc.ll Sun Jul 14 01:24:09 2013
@@ -1,6 +1,6 @@
; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
-; CHECK: func_nobody:
+; CHECK-LABEL: func_nobody:
; CHECK: jmp %o7+8
; CHECK-NEXT: nop
define void @func_nobody() {
@@ -9,7 +9,7 @@ entry:
}
-; CHECK: return_int_const:
+; CHECK-LABEL: return_int_const:
; CHECK: jmp %o7+8
; CHECK-NEXT: or %g0, 1729, %o0
define i32 @return_int_const() {
@@ -17,7 +17,7 @@ entry:
ret i32 1729
}
-; CHECK: return_double_const:
+; CHECK-LABEL: return_double_const:
; CHECK: sethi
; CHECK: jmp %o7+8
; CHECK-NEXT: ldd {{.*}}, %f0
@@ -27,7 +27,7 @@ entry:
ret double 0.000000e+00
}
-; CHECK: leaf_proc_with_args:
+; CHECK-LABEL: leaf_proc_with_args:
; CHECK: add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
; CHECK: jmp %o7+8
; CHECK-NEXT: add [[R]], %o2, %o0
@@ -39,7 +39,7 @@ entry:
ret i32 %1
}
-; CHECK: leaf_proc_with_args_in_stack:
+; CHECK-LABEL: leaf_proc_with_args_in_stack:
; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
; CHECK: jmp %o7+8
@@ -56,7 +56,7 @@ entry:
ret i32 %6
}
-; CHECK: leaf_proc_with_local_array:
+; CHECK-LABEL: leaf_proc_with_local_array:
; CHECK: add %sp, -104, %sp
; CHECK: or %g0, 1, [[R1:%[go][0-7]]]
; CHECK: st [[R1]], [%sp+96]
Modified: llvm/trunk/test/CodeGen/SystemZ/addr-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/addr-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/addr-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/addr-01.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; A simple index address.
define void @f1(i64 %addr, i64 %index) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
%add = add i64 %addr, %index
@@ -16,7 +16,7 @@ define void @f1(i64 %addr, i64 %index) {
; An address with an index and a displacement (order 1).
define void @f2(i64 %addr, i64 %index) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
@@ -28,7 +28,7 @@ define void @f2(i64 %addr, i64 %index) {
; An address with an index and a displacement (order 2).
define void @f3(i64 %addr, i64 %index) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, 100
@@ -40,7 +40,7 @@ define void @f3(i64 %addr, i64 %index) {
; An address with an index and a subtracted displacement (order 1).
define void @f4(i64 %addr, i64 %index) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
@@ -52,7 +52,7 @@ define void @f4(i64 %addr, i64 %index) {
; An address with an index and a subtracted displacement (order 2).
define void @f5(i64 %addr, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = sub i64 %addr, 100
@@ -64,7 +64,7 @@ define void @f5(i64 %addr, i64 %index) {
; An address with an index and a displacement added using OR.
define void @f6(i64 %addr, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: lb %r0, 6(%r3,[[BASE]])
; CHECK: br %r14
@@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index) {
; Like f6, but without the masking. This OR doesn't count as a displacement.
define void @f7(i64 %addr, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oill %r2, 6
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index) {
; Like f6, but with the OR applied after the index. We don't know anything
; about the alignment of %add here.
define void @f8(i64 %addr, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: agr [[BASE]], %r3
; CHECK: oill [[BASE]], 6
Modified: llvm/trunk/test/CodeGen/SystemZ/addr-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/addr-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/addr-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/addr-02.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@
; A simple index address.
define void @f1(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
%add = add i64 %addr, %index
@@ -18,7 +18,7 @@ define void @f1(i64 %addr, i64 %index, i
; An address with an index and a displacement (order 1).
define void @f2(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
@@ -31,7 +31,7 @@ define void @f2(i64 %addr, i64 %index, i
; An address with an index and a displacement (order 2).
define void @f3(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, 100
@@ -44,7 +44,7 @@ define void @f3(i64 %addr, i64 %index, i
; An address with an index and a subtracted displacement (order 1).
define void @f4(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
@@ -57,7 +57,7 @@ define void @f4(i64 %addr, i64 %index, i
; An address with an index and a subtracted displacement (order 2).
define void @f5(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = sub i64 %addr, 100
@@ -70,7 +70,7 @@ define void @f5(i64 %addr, i64 %index, i
; An address with an index and a displacement added using OR.
define void @f6(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: lb %r0, 6(%r3,[[BASE]])
; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f6(i64 %addr, i64 %index, i
; Like f6, but without the masking. This OR doesn't count as a displacement.
define void @f7(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oill %r2, 6
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f7(i64 %addr, i64 %index, i
; Like f6, but with the OR applied after the index. We don't know anything
; about the alignment of %add here.
define void @f8(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: agr [[BASE]], %r3
; CHECK: oill [[BASE]], 6
Modified: llvm/trunk/test/CodeGen/SystemZ/addr-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/addr-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/addr-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/addr-03.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0
; CHECK: br %r14
%ptr = inttoptr i64 0 to i8 *
@@ -12,7 +12,7 @@ define void @f1() {
}
define void @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, -524288
; CHECK: br %r14
%ptr = inttoptr i64 -524288 to i8 *
@@ -21,7 +21,7 @@ define void @f2() {
}
define void @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: lb %r0, -524289
; CHECK: br %r14
%ptr = inttoptr i64 -524289 to i8 *
@@ -30,7 +30,7 @@ define void @f3() {
}
define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, 524287
; CHECK: br %r14
%ptr = inttoptr i64 524287 to i8 *
@@ -39,7 +39,7 @@ define void @f4() {
}
define void @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: lb %r0, 524288
; CHECK: br %r14
%ptr = inttoptr i64 524288 to i8 *
Modified: llvm/trunk/test/CodeGen/SystemZ/alloca-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/alloca-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/alloca-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/alloca-01.ll Sun Jul 14 01:24:09 2013
@@ -21,34 +21,34 @@ define i64 @f1(i64 %length, i64 %index)
; risbg %r1, %r1, 0, 188, 0
; lgr %r15, %r1
;
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
; CHECK: sgr [[REG3]], [[REG2]]
; CHECK: lgr %r15, [[REG3]]
;
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, %r1
; CHECK-A: la %r2, 176(%r1)
;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, %r1
; CHECK-B: la %r3, 177(%r1)
;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, %r1
; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, %r1
; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, %r1
; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: lgr %r11, %r15
; CHECK-FP: lmg %r6, %r15, 224(%r11)
%a = alloca i8, i64 %length
Modified: llvm/trunk/test/CodeGen/SystemZ/alloca-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/alloca-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/alloca-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/alloca-02.ll Sun Jul 14 01:24:09 2013
@@ -9,27 +9,27 @@
declare i64 @bar(i8 *%a)
define i64 @f1(i64 %length, i64 %index) {
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A: la %r2, 160([[ADDR]])
; CHECK-A: mvi 0(%r2), 0
;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B: la %r2, 160([[ADDR]])
; CHECK-B: mvi 4095(%r2), 1
;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-C: mvi 0([[TMP]]), 2
;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-D: mvi 4095([[TMP]]), 3
;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-E: mviy 4096([[TMP]]), 4
Modified: llvm/trunk/test/CodeGen/SystemZ/and-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-01.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i32 @foo()
; Check NR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: nr %r2, %r3
; CHECK: br %r14
%and = and i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
; Check the low end of the N range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
; Check the high end of the aligned N range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: n %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
; Check the next word up, which should use NY instead of N.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ny %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
; Check the high end of the aligned NY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ny %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
; Check the high end of the negative aligned NY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ny %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
; Check the low end of the NY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ny %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
; Check that N allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %i
; Check that NY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %i
; Check that ANDs of spilled values can use N rather than NR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo at PLT
; CHECK: n %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/and-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-02.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; ANDs with 1 should use RISBG
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r2, 63, 191, 0
; CHECK: br %r14
%and = and i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
; ...same for 2.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r2, 62, 190, 0
; CHECK: br %r14
%and = and i32 %a, 2
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
; ...and 3.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 62, 191, 0
; CHECK: br %r14
%and = and i32 %a, 3
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
; ...and 4.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 61, 189, 0
; CHECK: br %r14
%and = and i32 %a, 4
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
; Check the lowest useful NILF value.
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilf %r2, 5
; CHECK: br %r14
%and = and i32 %a, 5
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
; Check the highest 16-bit constant that must be handled by NILF.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilf %r2, 65533
; CHECK: br %r14
%and = and i32 %a, 65533
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
; ANDs of 0xffff are zero extensions from i16.
define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llhr %r2, %r2
; CHECK: br %r14
%and = and i32 %a, 65535
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
; Check the next value up, which can use RISBG.
define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg %r2, %r2, 47, 175, 0
; CHECK: br %r14
%and = and i32 %a, 65536
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
; Check the next value up, which must again use NILF.
define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilf %r2, 65537
; CHECK: br %r14
%and = and i32 %a, 65537
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
; This value is in range of NILH, but we use RISBG instead.
define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: risbg %r2, %r2, 47, 191, 0
; CHECK: br %r14
%and = and i32 %a, 131071
@@ -94,7 +94,7 @@ define i32 @f10(i32 %a) {
; Check the lowest useful NILH value.
define i32 @f11(i32 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r2, 2
; CHECK: br %r14
%and = and i32 %a, 196607
@@ -103,7 +103,7 @@ define i32 @f11(i32 %a) {
; Check the highest useful NILH value.
define i32 @f12(i32 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilh %r2, 65530
; CHECK: br %r14
%and = and i32 %a, -327681
@@ -112,7 +112,7 @@ define i32 @f12(i32 %a) {
; Check the equivalent of NILH of 65531, which can use RISBG.
define i32 @f13(i32 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: risbg %r2, %r2, 46, 172, 0
; CHECK: br %r14
%and = and i32 %a, -262145
@@ -121,7 +121,7 @@ define i32 @f13(i32 %a) {
; ...same for 65532.
define i32 @f14(i32 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: risbg %r2, %r2, 48, 173, 0
; CHECK: br %r14
%and = and i32 %a, -196609
@@ -130,7 +130,7 @@ define i32 @f14(i32 %a) {
; ...and 65533.
define i32 @f15(i32 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: risbg %r2, %r2, 47, 173, 0
; CHECK: br %r14
%and = and i32 %a, -131073
@@ -139,7 +139,7 @@ define i32 @f15(i32 %a) {
; Check the highest useful NILF value.
define i32 @f16(i32 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nilf %r2, 4294901758
; CHECK: br %r14
%and = and i32 %a, -65538
@@ -149,7 +149,7 @@ define i32 @f16(i32 %a) {
; Check the next value up, which is the equivalent of an NILH of 65534.
; We use RISBG instead.
define i32 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: risbg %r2, %r2, 48, 174, 0
; CHECK: br %r14
%and = and i32 %a, -65537
@@ -158,7 +158,7 @@ define i32 @f17(i32 %a) {
; Check the next value up, which can also use RISBG.
define i32 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: risbg %r2, %r2, 32, 175, 0
; CHECK: br %r14
%and = and i32 %a, -65536
@@ -167,7 +167,7 @@ define i32 @f18(i32 %a) {
; ...and again.
define i32 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: risbg %r2, %r2, 63, 175, 0
; CHECK: br %r14
%and = and i32 %a, -65535
@@ -176,7 +176,7 @@ define i32 @f19(i32 %a) {
; Check the next value up again, which is the lowest useful NILL value.
define i32 @f20(i32 %a) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: nill %r2, 2
; CHECK: br %r14
%and = and i32 %a, -65534
@@ -185,7 +185,7 @@ define i32 @f20(i32 %a) {
; Check the highest useful NILL value.
define i32 @f21(i32 %a) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: nill %r2, 65530
; CHECK: br %r14
%and = and i32 %a, -6
@@ -194,7 +194,7 @@ define i32 @f21(i32 %a) {
; Check the next value up, which can use RISBG.
define i32 @f22(i32 %a) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: risbg %r2, %r2, 62, 188, 0
; CHECK: br %r14
%and = and i32 %a, -5
@@ -203,7 +203,7 @@ define i32 @f22(i32 %a) {
; ...and again.
define i32 @f23(i32 %a) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: risbg %r2, %r2, 32, 189, 0
; CHECK: br %r14
%and = and i32 %a, -4
@@ -212,7 +212,7 @@ define i32 @f23(i32 %a) {
; ...and again.
define i32 @f24(i32 %a) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: risbg %r2, %r2, 63, 189, 0
; CHECK: br %r14
%and = and i32 %a, -3
@@ -221,7 +221,7 @@ define i32 @f24(i32 %a) {
; Check the last useful mask.
define i32 @f25(i32 %a) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK: risbg %r2, %r2, 32, 190, 0
; CHECK: br %r14
%and = and i32 %a, -2
Modified: llvm/trunk/test/CodeGen/SystemZ/and-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-03.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i64 @foo()
; Check NGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ngr %r2, %r3
; CHECK: br %r14
%and = and i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
; Check NG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
; Check the high end of the aligned NG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ng %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
; Check the high end of the negative aligned NG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ng %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
; Check the low end of the NG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ng %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
; Check that NG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %in
; Check that ANDs of spilled values can use NG rather than NGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo at PLT
; CHECK: ng %r2, 160(%r15)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/and-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Use RISBG for a single bit.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r2, 63, 191, 0
; CHECK: br %r14
%and = and i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
; Likewise 0xfffe.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r2, 48, 190, 0
; CHECK: br %r14
%and = and i64 %a, 65534
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
; ...but 0xffff is a 16-bit zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%and = and i64 %a, 65535
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
; Check the next value up, which can again use RISBG.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 47, 175, 0
; CHECK: br %r14
%and = and i64 %a, 65536
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
; Check 0xfffffffe, which can also use RISBG.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: risbg %r2, %r2, 32, 190, 0
; CHECK: br %r14
%and = and i64 %a, 4294967294
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
; Check the next value up, which is a 32-bit zero extension.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llgfr %r2, %r2
; CHECK: br %r14
%and = and i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
; Check the lowest useful NIHF value (0x00000002_ffffffff).
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nihf %r2, 2
; CHECK: br %r14
%and = and i64 %a, 12884901887
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nihh %r2, 2
; CHECK: br %r14
%and = and i64 %a, 844424930131967
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a) {
; Check the highest useful NIHH value (0xfffaffff_ffffffff).
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nihh %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -1407374883553281
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a) {
; Check the highest useful NIHF value (0xfffefffe_ffffffff).
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nihf %r2, 4294901758
; CHECK: br %r14
%and = and i64 %a, -281479271677953
@@ -94,7 +94,7 @@ define i64 @f10(i64 %a) {
; Check the lowest useful NIHL value (0xffff0002_ffffffff).
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nihl %r2, 2
; CHECK: br %r14
%and = and i64 %a, -281462091808769
@@ -103,7 +103,7 @@ define i64 @f11(i64 %a) {
; Check the highest useful NIHL value (0xfffffffa_ffffffff).
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nihl %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -21474836481
@@ -112,7 +112,7 @@ define i64 @f12(i64 %a) {
; Check the lowest useful NILF range (0xffffffff_00000002).
define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nilf %r2, 2
; CHECK: br %r14
%and = and i64 %a, -4294967294
@@ -121,7 +121,7 @@ define i64 @f13(i64 %a) {
; Check the low end of the NILH range (0xffffffff_0002ffff).
define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nilh %r2, 2
; CHECK: br %r14
%and = and i64 %a, -4294770689
@@ -130,7 +130,7 @@ define i64 @f14(i64 %a) {
; Check the next value up, which must use NILF.
define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nilf %r2, 196608
; CHECK: br %r14
%and = and i64 %a, -4294770688
@@ -139,7 +139,7 @@ define i64 @f15(i64 %a) {
; Check the highest useful NILH value (0xffffffff_fffaffff).
define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nilh %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -327681
@@ -148,7 +148,7 @@ define i64 @f16(i64 %a) {
; Check the maximum useful NILF value (0xffffffff_fffefffe).
define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: nilf %r2, 4294901758
; CHECK: br %r14
%and = and i64 %a, -65538
@@ -157,7 +157,7 @@ define i64 @f17(i64 %a) {
; Check the lowest useful NILL value (0xffffffff_ffff0002).
define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: nill %r2, 2
; CHECK: br %r14
%and = and i64 %a, -65534
@@ -166,7 +166,7 @@ define i64 @f18(i64 %a) {
; Check the highest useful NILL value.
define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: nill %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -6
Modified: llvm/trunk/test/CodeGen/SystemZ/and-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-05.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-05.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check the lowest useful constant, expressed as a signed integer.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ni 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
; Check the highest useful constant, expressed as a signed integer.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
; Check the lowest useful constant, expressed as an unsigned integer.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ni 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
; Check the highest useful constant, expressed as a unsigned integer.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
; Check the high end of the NI range.
define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ni 4095(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
; Check the next byte up, which should use NIY instead of NI.
define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: niy 4096(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
; Check the high end of the NIY range.
define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: niy 524287(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, 524288
; CHECK: ni 0(%r2), 127
; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
; Check the high end of the negative NIY range.
define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: niy -1(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
; Check the low end of the NIY range.
define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: niy -524288(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, -524289
; CHECK: ni 0(%r2), 127
; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
; Check that NI does not allow an index
define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r2, %r3
; CHECK: ni 4095(%r2), 127
; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
; Check that NIY does not allow an index
define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agr %r2, %r3
; CHECK: niy 4096(%r2), 127
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/and-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-06.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-06.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Zero extension to 32 bits, negative constant.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
; Zero extension to 64 bits, negative constant.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
; Zero extension to 32 bits, positive constant.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
; Zero extension to 64 bits, positive constant.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
; Sign extension to 32 bits, negative constant.
define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
; Sign extension to 64 bits, negative constant.
define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
; Sign extension to 32 bits, positive constant.
define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
; Sign extension to 64 bits, positive constant.
define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
Modified: llvm/trunk/test/CodeGen/SystemZ/args-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-01.ll Sun Jul 14 01:24:09 2013
@@ -20,7 +20,7 @@ declare void @bar(i8, i16, i32, i64, flo
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lhi %r2, 1
; CHECK-INT-DAG: lhi %r3, 2
; CHECK-INT-DAG: lhi %r4, 3
@@ -28,31 +28,31 @@ define void @foo() {
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar at PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar at PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar at PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar at PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar at PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
Modified: llvm/trunk/test/CodeGen/SystemZ/args-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-02.ll Sun Jul 14 01:24:09 2013
@@ -21,7 +21,7 @@ declare void @bar(i8 signext, i16 signex
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lghi %r2, -1
; CHECK-INT-DAG: lghi %r3, -2
; CHECK-INT-DAG: lghi %r4, -3
@@ -29,31 +29,31 @@ define void @foo() {
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar at PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar at PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar at PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar at PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar at PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
Modified: llvm/trunk/test/CodeGen/SystemZ/args-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-03.ll Sun Jul 14 01:24:09 2013
@@ -21,7 +21,7 @@ declare void @bar(i8 zeroext, i16 zeroex
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lghi %r2, 255
; CHECK-INT-DAG: llill %r3, 65534
; CHECK-INT-DAG: llilf %r4, 4294967293
@@ -29,31 +29,31 @@ define void @foo() {
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar at PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar at PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar at PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar at PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar at PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
Modified: llvm/trunk/test/CodeGen/SystemZ/args-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-04.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Do some arithmetic so that we can see the register being used.
define i8 @f1(i8 %r2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ahi %r2, 1
; CHECK: br %r14
%y = add i8 %r2, 1
@@ -13,21 +13,21 @@ define i8 @f1(i8 %r2) {
}
define i16 @f2(i8 %r2, i16 %r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: {{lr|lgr}} %r2, %r3
; CHECK: br %r14
ret i16 %r3
}
define i32 @f3(i8 %r2, i16 %r3, i32 %r4) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: {{lr|lgr}} %r2, %r4
; CHECK: br %r14
ret i32 %r4
}
define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: {{lr|lgr}} %r2, %r5
; CHECK: br %r14
ret i64 %r5
@@ -35,7 +35,7 @@ define i64 @f4(i8 %r2, i16 %r3, i32 %r4,
; Do some arithmetic so that we can see the register being used.
define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aebr %f0, %f0
; CHECK: br %r14
%y = fadd float %f0, %f0
@@ -43,7 +43,7 @@ define float @f5(i8 %r2, i16 %r3, i32 %r
}
define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldr %f0, %f2
; CHECK: br %r14
ret double %f2
@@ -54,7 +54,7 @@ define double @f6(i8 %r2, i16 %r3, i32 %
; be copied.
define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ld %f0, 0(%r6)
; CHECK: ld %f2, 8(%r6)
; CHECK: axbr %f0, %f0
@@ -68,7 +68,7 @@ define void @f7(fp128 *%r2, i16 %r3, i32
define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lg %r2, 160(%r15)
; CHECK: br %r14
ret i64 %s1
@@ -76,7 +76,7 @@ define i64 @f8(i8 %r2, i16 %r3, i32 %r4,
define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ler %f0, %f4
; CHECK: br %r14
ret float %f4
@@ -84,7 +84,7 @@ define float @f9(i8 %r2, i16 %r3, i32 %r
define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ldr %f0, %f6
; CHECK: br %r14
ret double %f6
@@ -92,7 +92,7 @@ define double @f10(i8 %r2, i16 %r3, i32
define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lg %r2, 168(%r15)
; CHECK: br %r14
ret i64 %s2
@@ -102,7 +102,7 @@ define i64 @f11(i8 %r2, i16 %r3, i32 %r4
define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
float %s3) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: le %f0, 180(%r15)
; CHECK: br %r14
ret float %s3
@@ -112,7 +112,7 @@ define float @f12(i8 %r2, i16 %r3, i32 %
define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
float %s3, fp128 %s4) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15)
; CHECK: ld %f0, 0([[REGISTER]])
; CHECK: ld %f2, 8([[REGISTER]])
Modified: llvm/trunk/test/CodeGen/SystemZ/args-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-05.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-05.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Zero extension of something that is already zero-extended.
define void @f1(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: stg %r2, 0(%r3)
; CHECK: br %r14
@@ -15,7 +15,7 @@ define void @f1(i32 zeroext %r2, i64 *%r
; Sign extension of something that is already sign-extended.
define void @f2(i32 signext %r2, i64 *%r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: stg %r2, 0(%r3)
; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i32 signext %r2, i64 *%r
; Sign extension of something that is already zero-extended.
define void @f3(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
; CHECK: stg [[REGISTER]], 0(%r3)
; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f3(i32 zeroext %r2, i64 *%r
; Zero extension of something that is already sign-extended.
define void @f4(i32 signext %r2, i64 *%r3) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
; CHECK: stg [[REGISTER]], 0(%r3)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/args-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/args-06.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/args-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/args-06.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
@@ -22,7 +22,7 @@ define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d
}
define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
@@ -40,7 +40,7 @@ define i16 @f2(i16 %a, i16 %b, i16 %c, i
}
define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
@@ -58,7 +58,7 @@ define i32 @f3(i32 %a, i32 %b, i32 %c, i
}
define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agr %r2, %r3
; CHECK: agr %r2, %r4
; CHECK: agr %r2, %r5
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-01.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Check the lowest range.
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
; Check the next lowest byte.
define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r2, -1
; CHECK: blah 0(%r2)
; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
; Check the highest range.
define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah 4095(%r2)
; CHECK: br %r14
%add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
; Check the next highest byte.
define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: blah 0(%r2)
; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f4(i64 %base) {
; Check that indices aren't allowed
define void @f5(i64 %base, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agr %r2, %r3
; CHECK: blah 0(%r2)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-02.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; Check the lowest range.
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
; Check the next lowest byte.
define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r2, -1
; CHECK: blah 0(%r2)
; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
; Check the highest range.
define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah 4095(%r2)
; CHECK: br %r14
%add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
; Check the next highest byte.
define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: blah 0(%r2)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-05.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-05.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-06.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-06.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r1, 1
; CHECK: blah %r2 %r1
; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r1, 2
; CHECK: blah %r2 %r1
; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r1, 3
; CHECK: blah %r2 %r1
; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r1, 4
; CHECK: blah %r2 %r1
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-07.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-07.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 1
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 2
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 3
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r0, 4
; CHECK: blah %r2 %r0
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-08.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-08.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-08.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-08.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 1
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 2
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 3
; CHECK: blah %r2 %r0
; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r0, 4
; CHECK: blah %r2 %r0
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-09.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-09.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-09.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-09.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 100
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
@@ -14,7 +14,7 @@ define void @f1(i32 *%dst) {
}
define void @f2(i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 101
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
@@ -25,7 +25,7 @@ define void @f2(i32 *%dst) {
}
define void @f3(i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 102
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
@@ -37,7 +37,7 @@ define void @f3(i32 *%dst) {
; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103".
define void @f4(i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
; CHECK: br %r14
@@ -47,7 +47,7 @@ define void @f4(i32 *%dst) {
}
define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lghi %r2, 104
; CHECK: blah %r2
; CHECK: br %r14
@@ -56,7 +56,7 @@ define i64 @f5() {
}
define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lghi %r2, 105
; CHECK: blah %r2
; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f6() {
}
define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lghi %r2, 106
; CHECK: blah %r2
; CHECK: br %r14
@@ -74,7 +74,7 @@ define i64 @f7() {
}
define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lghi %r2, 107
; CHECK: blah %r2
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-10.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-10.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-10.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lzer %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1() {
}
define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lzdr %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
@@ -21,7 +21,7 @@ define double @f2() {
}
define double @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzxr %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-11.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-11.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-11.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 0
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 255
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
@@ -32,7 +32,7 @@ define i32 @f3() {
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lhi [[REG:%r[0-5]]], 256
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-12.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-12.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-12.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-12.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 0
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 4095
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095)
@@ -32,7 +32,7 @@ define i32 @f3() {
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lhi [[REG:%r[0-5]]], 4096
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-13.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-13.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-13.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-13.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294934527
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 -32768
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 32767
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767)
@@ -32,7 +32,7 @@ define i32 @f3() {
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llill [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-14.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-14.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-14.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-14.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294443007
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 -524288
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 524287
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287)
@@ -32,7 +32,7 @@ define i32 @f3() {
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llilh [[REG:%r[0-5]]], 8
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-15.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-15.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-15.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-15.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 2147483647
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test 1 above the valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llilh [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-16.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-16.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-16.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test 1 below the valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 2147483647
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
; Test 1 above the valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llilh [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-17.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-17.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-17.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-17.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Test i32 GPRs.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r4, 1
; CHECK: blah %r4
; CHECK: lr %r2, %r4
@@ -15,7 +15,7 @@ define i32 @f1() {
; Test i64 GPRs.
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lghi %r4, 1
; CHECK: blah %r4
; CHECK: lgr %r2, %r4
@@ -26,7 +26,7 @@ define i64 @f2() {
; Test i32 FPRs.
define float @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzer %f4
; CHECK: blah %f4
; CHECK: ler %f0, %f4
@@ -37,7 +37,7 @@ define float @f3() {
; Test i64 FPRs.
define double @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lzdr %f4
; CHECK: blah %f4
; CHECK: ldr %f0, %f4
@@ -48,7 +48,7 @@ define double @f4() {
; Test i128 FPRs.
define void @f5(fp128 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lzxr %f4
; CHECK: blah %f4
; CHECK-DAG: std %f4, 0(%r2)
@@ -61,7 +61,7 @@ define void @f5(fp128 *%dest) {
; Test clobbers of GPRs and CC.
define i32 @f6(i32 %in) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lr [[REG:%r[01345]]], %r2
; CHECK: blah
; CHECK: lr %r2, [[REG]]
@@ -72,7 +72,7 @@ define i32 @f6(i32 %in) {
; Test clobbers of FPRs and CC.
define float @f7(float %in) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ler [[REG:%f[1-7]]], %f0
; CHECK: blah
; CHECK: ler %f0, [[REG]]
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-load-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-load-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-load-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-load-01.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that loads are handled.
; The CS-based sequence is probably far too conservative.
define i8 @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
%val = load atomic i8 *%src seq_cst, align 1
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-load-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-load-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-load-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-load-02.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that loads are handled.
; The CS-based sequence is probably far too conservative.
define i16 @f1(i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
%val = load atomic i16 *%src seq_cst, align 2
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-load-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-load-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-load-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-load-03.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that loads are handled.
; Using CS is probably too conservative.
define i32 @f1(i32 %dummy, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r2, 0
; CHECK: cs %r2, %r2, 0(%r3)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-load-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-load-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-load-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-load-04.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that loads are handled.
; Using CSG is probably too conservative.
define i64 @f1(i64 %dummy, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lghi %r2, 0
; CHECK: csg %r2, %r2, 0(%r3)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-store-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-store-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-store-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-store-01.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that stores are handled.
; The CS-based sequence is probably far too conservative.
define void @f1(i8 %val, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
store atomic i8 %val, i8 *%src seq_cst, align 1
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-store-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-store-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-store-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-store-02.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that stores are handled.
; The CS-based sequence is probably far too conservative.
define void @f1(i16 %val, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
store atomic i16 %val, i16 *%src seq_cst, align 2
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-store-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-store-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-store-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-store-03.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that stores are handled.
; Using CS is probably too conservative.
define void @f1(i32 %val, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r0, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r0, %r2, 0(%r3)
Modified: llvm/trunk/test/CodeGen/SystemZ/atomic-store-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomic-store-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomic-store-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-store-04.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; This is just a placeholder to make sure that stores are handled.
; Using CS is probably too conservative.
define void @f1(i64 %val, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r0, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: csg %r0, %r2, 0(%r3)
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
; Check addition of -1. We add 0xff000000 to the rotated word.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], -16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 -1 seq_cst
ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
; Check addition of 1. We add 0x01000000 to the rotated word.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We add 0x7f000000 to the rotated word.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], 2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
; Check addition of a large unsigned value. We add 0xfe000000 to the
; rotated word, expressed as a negative AFI operand.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], -33554432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 254 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
; Check addition of -1. We add 0xffff0000 to the rotated word.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], -65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 -1 seq_cst
ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
; Check addition of 1. We add 0x00010000 to the rotated word.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We add 0x7fff0000 to the rotated word.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], 2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
; Check addition of a large unsigned value. We add 0xfffe0000 to the
; rotated word, expressed as a negative AFI operand.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], -131072
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 65534 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check addition of 1, which can use AHI.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check the high end of the AHI range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ahi %r0, 32767
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 32767 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check the next value up, which must use AFI.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi %r0, 32768
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 32768 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
; Check the high end of the AFI range.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
; Check the next value up, which gets treated as a negative operand.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
; Check addition of -1, which can use AHI.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahi %r0, -1
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
; Check the low end of the AHI range.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ahi %r0, -32768
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -32768 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
; Check the next value down, which must use AFI instead.
define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r0, -32769
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -32769 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check addition of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check addition of 1, which can use AGHI.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the high end of the AGHI range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r0, 32767
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 32767 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the next value up, which must use AGFI.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r0, 32768
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 32768 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the high end of the AGFI range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register addition.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agr
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check addition of -1, which can use AGHI.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: aghi %r0, -1
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
; Check the low end of the AGHI range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r0, -32768
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -32768 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
; Check the next value down, which must use AGFI instead.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r0, -32769
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -32769 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
; Check the low end of the AGFI range.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
; Check the next value down, which must use a register addition.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agr
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: oilf %r3, 16777215
; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -77,13 +77,13 @@ define i8 @f2(i8 *%src) {
; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65279
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 -2 seq_cst
ret i8 %res
@@ -91,13 +91,13 @@ define i8 @f3(i8 *%src) {
; Check ANDs of 1. We AND the rotated word with 0x01ffffff.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 511
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -105,13 +105,13 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -120,13 +120,13 @@ define i8 @f5(i8 *%src) {
; Check ANDs of a large unsigned value. We AND the rotated word with
; 0xfdffffff.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65023
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 253 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: oill %r3, 65535
; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -77,13 +77,13 @@ define i16 @f2(i16 *%src) {
; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65534
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 -2 seq_cst
ret i16 %res
@@ -91,13 +91,13 @@ define i16 @f3(i16 *%src) {
; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 1
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -105,13 +105,13 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -120,13 +120,13 @@ define i16 @f5(i16 *%src) {
; Check ANDs of a large unsigned value. We AND the rotated word with
; 0xfffdffff.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65533
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 65533 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check ANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check ANDs of 1.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check ANDs of the low end of the NILH range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check the next value up, which must use NILF.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilf %r0, 65536
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
; Check the largest useful NILL value.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nill %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -2 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
; Check the low end of the NILL range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nill %r0, 0
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
; Check the largest useful NILH value, which is one less than the above.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nilh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65537 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
; Check the highest useful NILF value, which is one less than the above.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nilf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65538 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check ANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check ANDs of 1, which must be done using a register.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 1 seq_cst
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the low end of the NIHF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 4294967296 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the low end of the NIHH range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nihh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check the highest useful NILL value.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nill %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -2 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
; Check the low end of the NILL range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nill %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65536 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
; Check the highest useful NILH value, which is one less than the above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65537 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
; Check the highest useful NILF value, which is one less than the above.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nilf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65538 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
; Check the low end of the NILH range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst
@@ -113,7 +113,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
; Check the low end of the NILF range.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilf %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst
@@ -122,7 +122,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
; Check the highest useful NIHL value, which is one less than the above.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nihl %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst
@@ -131,7 +131,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
; Check the low end of the NIHL range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nihl %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst
@@ -140,7 +140,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
; Check the highest useful NIHH value, which is 1<<32 less than the above.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nihh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst
@@ -149,7 +149,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
; Check the highest useful NIHF value, which is 1<<32 less than the above.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nihf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check signed maximum.
define i8 @f2(i8 *%src, i8 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i8 @f2(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i8 @f2(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i8 @f2(i8 *%src, i8 %b) {
; Check unsigned minimum.
define i8 @f3(i8 *%src, i8 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i8 @f3(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i8 @f3(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i8 @f3(i8 *%src, i8 %b) {
; Check unsigned maximum.
define i8 @f4(i8 *%src, i8 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i8 @f4(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i8 @f4(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i8 @f4(i8 *%src, i8 %b) {
; Check the lowest useful signed minimum value. We need to load 0x81000000
; into the source register.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw min i8 *%src, i8 -127 seq_cst
ret i8 %res
@@ -177,15 +177,15 @@ define i8 @f5(i8 *%src) {
; Check the highest useful signed maximum value. We need to load 0x7e000000
; into the source register.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw max i8 *%src, i8 126 seq_cst
ret i8 %res
@@ -194,15 +194,15 @@ define i8 @f6(i8 *%src) {
; Check the lowest useful unsigned minimum value. We need to load 0x01000000
; into the source register.
define i8 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilh [[SRC2:%r[0-9]+]], 256
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umin i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -211,15 +211,15 @@ define i8 @f7(i8 *%src) {
; Check the highest useful unsigned maximum value. We need to load 0xfe000000
; into the source register.
define i8 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umax i8 *%src, i8 254 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check signed maximum.
define i16 @f2(i16 *%src, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i16 @f2(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i16 @f2(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i16 @f2(i16 *%src, i16 %b) {
; Check unsigned minimum.
define i16 @f3(i16 *%src, i16 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i16 @f3(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i16 @f3(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i16 @f3(i16 *%src, i16 %b) {
; Check unsigned maximum.
define i16 @f4(i16 *%src, i16 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i16 @f4(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i16 @f4(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i16 @f4(i16 *%src, i16 %b) {
; Check the lowest useful signed minimum value. We need to load 0x80010000
; into the source register.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw min i16 *%src, i16 -32767 seq_cst
ret i16 %res
@@ -177,15 +177,15 @@ define i16 @f5(i16 *%src) {
; Check the highest useful signed maximum value. We need to load 0x7ffe0000
; into the source register.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw max i16 *%src, i16 32766 seq_cst
ret i16 %res
@@ -194,15 +194,15 @@ define i16 @f6(i16 *%src) {
; Check the lowest useful unsigned maximum value. We need to load 0x00010000
; into the source register.
define i16 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilh [[SRC2:%r[0-9]+]], 1
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umin i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -211,15 +211,15 @@ define i16 @f7(i16 *%src) {
; Check the highest useful unsigned maximum value. We need to load 0xfffe0000
; into the source register.
define i16 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umax i16 *%src, i16 65534 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check signed minium.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check signed maximum.
define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i3
; Check unsigned minimum.
define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clr %r2, %r4
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i3
; Check unsigned maximum.
define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clr %r2, %r4
@@ -66,7 +66,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i3
; Check the high end of the aligned CS range.
define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: l %r2, 4092(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i3
; Check the next word up, which requires CSY.
define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ly %r2, 4096(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
; CHECK: br %r14
@@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i3
; Check the high end of the aligned CSY range.
define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ly %r2, 524284(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i3
; Check the next word up, which needs separate address logic.
define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, 524288
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -111,7 +111,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i3
; Check the high end of the negative aligned CSY range.
define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ly %r2, -4(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i3
; Check the low end of the CSY range.
define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ly %r2, -524288(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
@@ -133,7 +133,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i
; Check the next word down, which needs separate address logic.
define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r3, -524292
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -145,7 +145,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i
; Check that indexed addresses are not allowed.
define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r3, %r4
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -158,7 +158,7 @@ define i32 @f12(i32 %dummy, i64 %base, i
; Check that constants are handled.
define i32 @f13(i32 %dummy, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check signed minium.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check signed maximum.
define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i6
; Check unsigned minimum.
define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clgr %r2, %r4
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i6
; Check unsigned maximum.
define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clgr %r2, %r4
@@ -66,7 +66,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i6
; Check the high end of the aligned CSG range.
define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lg %r2, 524280(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i6
; Check the next doubleword up, which requires separate address logic.
define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -89,7 +89,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i6
; Check the low end of the CSG range.
define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lg %r2, -524288(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
@@ -100,7 +100,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i6
; Check the next doubleword down, which requires separate address logic.
define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524296
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -112,7 +112,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i6
; Check that indexed addresses are not allowed.
define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r3, %r4
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -125,7 +125,7 @@ define i64 @f9(i64 %dummy, i64 %base, i6
; Check that constants are handled.
define i64 @f10(i64 %dummy, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: oilf %r3, 16777215
; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -79,14 +79,14 @@ define i8 @f2(i8 *%src) {
; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65279
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 -2 seq_cst
ret i8 %res
@@ -94,14 +94,14 @@ define i8 @f3(i8 *%src) {
; Check NANDs of 1. We AND the rotated word with 0x01ffffff.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 511
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -109,14 +109,14 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -125,14 +125,14 @@ define i8 @f5(i8 *%src) {
; Check NANDs of a large unsigned value. We AND the rotated word with
; 0xfdffffff.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65023
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 253 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: oill %r3, 65535
; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -79,14 +79,14 @@ define i16 @f2(i16 *%src) {
; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65534
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 -2 seq_cst
ret i16 %res
@@ -94,14 +94,14 @@ define i16 @f3(i16 *%src) {
; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 1
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -109,14 +109,14 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -125,14 +125,14 @@ define i16 @f5(i16 *%src) {
; Check NANDs of a large unsigned value. We AND the rotated word with
; 0xfffdffff.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65533
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 65533 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check NANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check NANDs of 1.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check NANDs of the low end of the NILH range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh %r0, 0
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
@@ -44,7 +44,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check the next value up, which must use NILF.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilf %r0, 65536
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
@@ -54,7 +54,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
; Check the largest useful NILL value.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nill %r0, 65534
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
@@ -64,7 +64,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
; Check the low end of the NILL range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nill %r0, 0
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
@@ -74,7 +74,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
; Check the largest useful NILH value, which is one less than the above.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nilh %r0, 65534
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
; Check the highest useful NILF value, which is one less than the above.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nilf %r0, 4294901758
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check NANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -20,7 +20,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check NANDs of 1, which must be done using a register.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 1 seq_cst
@@ -29,7 +29,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the low end of the NIHF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -45,7 +45,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst
@@ -54,7 +54,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the low end of the NIHH range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nihh %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
@@ -74,7 +74,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check the highest useful NILL value.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nill %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -85,7 +85,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
; Check the low end of the NILL range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nill %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -96,7 +96,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
; Check the highest useful NILH value, which is one less than the above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilh %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -107,7 +107,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
; Check the highest useful NILF value, which is one less than the above.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nilf %r0, 4294901758
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -118,7 +118,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
; Check the low end of the NILH range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -129,7 +129,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
; Check the low end of the NILF range.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilf %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -140,7 +140,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
; Check the highest useful NIHL value, which is one less than the above.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nihl %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -151,7 +151,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
; Check the low end of the NIHL range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nihl %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -162,7 +162,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
; Check the highest useful NIHH value, which is 1<<32 less than the above.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nihh %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
@@ -173,7 +173,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
; Check the highest useful NIHF value, which is 1<<32 less than the above.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nihf %r0, 4294901758
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We OR the rotated word with 0x80000000.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfe000000.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh [[ROT]], 65024
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 -2 seq_cst
ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
; Check ORs of 1. We OR the rotated word with 0x01000000.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh [[ROT]], 256
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We OR the rotated word with 0x7f000000.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh [[ROT]], 32512
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
; Check ORs of a large unsigned value. We OR the rotated word with
; 0xfd000000.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh [[ROT]], 64768
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 253 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We OR the rotated word with 0x80000000.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfffe0000.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh [[ROT]], 65534
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 -2 seq_cst
ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
; Check ORs of 1. We OR the rotated word with 0x00010000.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh [[ROT]], 1
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We OR the rotated word with 0x7fff0000.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
; Check ORs of a large unsigned value. We OR the rotated word with
; 0xfffd0000.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh [[ROT]], 65533
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 65533 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check ORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check the lowest useful OILL value.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check the high end of the OILL range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oill %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check the lowest useful OILH value, which is the next value up.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
; Check the lowest useful OILF value, which is the next value up.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65537 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
; Check the high end of the OILH range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
; Check the next value up, which must use OILF.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oilf %r0, 4294901761
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -65535 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
; Check the largest useful OILF value.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oilf %r0, 4294967294
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -2 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check ORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check the lowest useful OILL value.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the high end of the OILL range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oill %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65535 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the lowest useful OILH value, which is the next value up.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65536 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the lowest useful OILF value, which is the next value up again.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65537 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the high end of the OILH range.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294901760 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check the next value up, which must use OILF.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oilf %r0, 4294901761
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294901761 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
; Check the high end of the OILF range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967295 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
; Check the lowest useful OIHL value, which is one greater than above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: oihl %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967296 seq_cst
@@ -96,7 +96,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register. (We could use
; combinations of OIH* and OIL* instead, but that isn't implemented.)
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ogr
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967297 seq_cst
@@ -105,7 +105,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
; Check the high end of the OIHL range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: oihl %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst
@@ -114,7 +114,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
; Check the lowest useful OIHH value, which is 1<<32 greater than above.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: oihh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst
@@ -123,7 +123,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
; Check the lowest useful OIHF value, which is 1<<32 greater again.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: oihf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst
@@ -132,7 +132,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
; Check the high end of the OIHH range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: oihh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst
@@ -141,7 +141,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: ogr
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst
@@ -150,7 +150,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
; Check the high end of the OIHF range.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: oihf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
; Check subtraction of -1. We add 0x01000000 to the rotated word.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 -1 seq_cst
ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
; Check subtraction of -1. We add 0xff000000 to the rotated word.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], -16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We add 0x81000000 to the rotated word.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], -2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
; Check subtraction of a large unsigned value. We add 0x02000000 to the
; rotated word.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], 33554432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 254 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
; Check subtraction of -1. We add 0x00010000 to the rotated word.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 -1 seq_cst
ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
; Check subtraction of 1. We add 0xffff0000 to the rotated word.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], -65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We add 0x80010000 to the rotated word.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], -2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
; Check subtraction of a large unsigned value. We add 0x00020000 to the
; rotated word.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], 131072
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 65534 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check subtraction of 1, which can use AHI.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check the low end of the AHI range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ahi %r0, -32768
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 32768 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check the next value down, which must use AFI.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi %r0, -32769
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 32769 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
; Check the low end of the AFI range.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
; Check the next value up, which gets treated as a positive operand.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
; Check subtraction of -1, which can use AHI.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahi %r0, 1
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
; Check the high end of the AHI range.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ahi %r0, 32767
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -32767 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
; Check the next value down, which must use AFI instead.
define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r0, 32768
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -32768 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check subtraction of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check subtraction of 1, which can use AGHI.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the low end of the AGHI range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r0, -32768
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 32768 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the next value up, which must use AGFI.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r0, -32769
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 32769 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the low end of the AGFI range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register operation.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sgr
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check subtraction of -1, which can use AGHI.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: aghi %r0, 1
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
; Check the high end of the AGHI range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r0, 32767
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -32767 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
; Check the next value down, which must use AGFI instead.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r0, 32768
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -32768 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
; Check the high end of the AGFI range.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
; Check the next value down, which must use a register operation.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sgr
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check exchange with a constant. We should force the constant into
; a register and use the sequence above.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[VALUE:%r[0-9]+]], 88
; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: br %r14
%res = atomicrmw xchg i8 *%src, i8 88 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check exchange with a constant. We should force the constant into
; a register and use the sequence above.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: br %r14
%res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check register exchange.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check the high end of the aligned CS range.
define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 4092(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
; CHECK: br %r14
@@ -27,7 +27,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i3
; Check the next word up, which requires CSY.
define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ly %r2, 4096(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
; CHECK: br %r14
@@ -38,7 +38,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i3
; Check the high end of the aligned CSY range.
define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ly %r2, 524284(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
; CHECK: br %r14
@@ -49,7 +49,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i3
; Check the next word up, which needs separate address logic.
define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -61,7 +61,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i3
; Check the high end of the negative aligned CSY range.
define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ly %r2, -4(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
; CHECK: br %r14
@@ -72,7 +72,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i3
; Check the low end of the CSY range.
define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ly %r2, -524288(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
@@ -83,7 +83,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i3
; Check the next word down, which needs separate address logic.
define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524292
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -95,7 +95,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i3
; Check that indexed addresses are not allowed.
define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r3, %r4
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -109,7 +109,7 @@ define i32 @f9(i32 %dummy, i64 %base, i6
; Check exchange of a constant. We should force it into a register and
; use the sequence above.
define i32 @f10(i32 %dummy, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llill [[VALUE:%r[0-9+]]], 40000
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check register exchange.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: csg %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check the high end of the aligned CSG range.
define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 524280(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
; CHECK: br %r14
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i6
; Check the next doubleword up, which requires separate address logic.
define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r3, 524288
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -39,7 +39,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i6
; Check the low end of the CSG range.
define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, -524288(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i6
; Check the next doubleword down, which requires separate address logic.
define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, -524296
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -62,7 +62,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i6
; Check that indexed addresses are not allowed.
define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agr %r3, %r4
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -76,7 +76,7 @@ define i64 @f6(i64 %dummy, i64 %base, i6
; Check exchange of a constant. We should force it into a register and
; use the sequence above.
define i64 @f7(i64 %dummy, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-01.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
; Check the minimum signed value. We XOR the rotated word with 0x80000000.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 -128 seq_cst
ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
; Check XORs of -1. We XOR the rotated word with 0xff000000.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 -1 seq_cst
ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
; Check XORs of 1. We XOR the rotated word with 0x01000000.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 1 seq_cst
ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xilf [[ROT]], 2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 127 seq_cst
ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
; Check XORs of a large unsigned value. We XOR the rotated word with
; 0xfd000000.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xilf [[ROT]], 4244635648
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 253 seq_cst
ret i8 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-02.ll Sun Jul 14 01:24:09 2013
@@ -13,7 +13,7 @@
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
; Check the minimum signed value. We XOR the rotated word with 0x80000000.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 -32768 seq_cst
ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
; Check XORs of -1. We XOR the rotated word with 0xffff0000.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 -1 seq_cst
ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
; Check XORs of 1. We XOR the rotated word with 0x00010000.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 1 seq_cst
ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xilf [[ROT]], 2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 32767 seq_cst
ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
; Check XORs of a large unsigned value. We XOR the rotated word with
; 0xfffd0000.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xilf [[ROT]], 4294770688
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 65533 seq_cst
ret i16 %res
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check XORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i3
; Check the lowest useful constant.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
; Check an arbitrary constant.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf %r0, 3000000000
; CHECK: br %r14
%res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
; Check bitwise negation.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i32 *%src, i32 -1 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check XORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i6
; Check the lowest useful XILF value.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
; Check the high end of the XILF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
; Check the lowest useful XIHF value, which is one greater than above.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xihf %r0, 1
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst
@@ -51,7 +51,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register. (We could use
; combinations of XIH* and XIL* instead, but that isn't implemented.)
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xgr
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst
@@ -60,7 +60,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
; Check the high end of the XIHF range.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xihf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst
@@ -69,7 +69,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
; Check the next value up, which must use a register.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xgr
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-01.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .L[[LABEL:.*]]:
; CHECK: mvi 0(%r2), 1
; CHECK: j .L[[LABEL]]
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-02.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
@@ -20,7 +20,7 @@ exit:
}
define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
@@ -35,7 +35,7 @@ exit:
}
define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
@@ -50,7 +50,7 @@ exit:
}
define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
@@ -65,7 +65,7 @@ exit:
}
define void @f5(i32 *%src, i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
@@ -80,7 +80,7 @@ exit:
}
define void @f6(i32 *%src, i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-03.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
@@ -18,7 +18,7 @@ exit:
}
define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
@@ -33,7 +33,7 @@ exit:
}
define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
@@ -48,7 +48,7 @@ exit:
}
define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(float *%src, float %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -19,7 +19,7 @@ exit:
}
define void @f2(float *%src, float %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -34,7 +34,7 @@ exit:
}
define void @f3(float *%src, float %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -49,7 +49,7 @@ exit:
}
define void @f4(float *%src, float %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -64,7 +64,7 @@ exit:
}
define void @f5(float *%src, float %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -79,7 +79,7 @@ exit:
}
define void @f6(float *%src, float %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -94,7 +94,7 @@ exit:
}
define void @f7(float *%src, float %target) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -109,7 +109,7 @@ exit:
}
define void @f8(float *%src, float %target) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -124,7 +124,7 @@ exit:
}
define void @f9(float *%src, float %target) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -139,7 +139,7 @@ exit:
}
define void @f10(float *%src, float %target) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -154,7 +154,7 @@ exit:
}
define void @f11(float *%src, float %target) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -169,7 +169,7 @@ exit:
}
define void @f12(float *%src, float %target) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -186,7 +186,7 @@ exit:
; "jno" == "jump if no overflow", which corresponds to "jump if ordered"
; rather than "jump if not ordered" after a floating-point comparison.
define void @f13(float *%src, float %target) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
@@ -203,7 +203,7 @@ exit:
; "jo" == "jump if overflow", which corresponds to "jump if not ordered"
; rather than "jump if ordered" after a floating-point comparison.
define void @f14(float *%src, float %target) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-05.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-05.ll Sun Jul 14 01:24:09 2013
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i32 @f1(i32 %x, i32 %y, i32 %op) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ahi %r4, -1
; CHECK: clfi %r4, 5
; CHECK-NEXT: jh
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-06.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-06.ll Sun Jul 14 01:24:09 2013
@@ -5,7 +5,7 @@
declare i32 @foo()
define void @f1(i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -19,7 +19,7 @@ exit:
}
define void @f2(i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -33,7 +33,7 @@ exit:
}
define void @f3(i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -47,7 +47,7 @@ exit:
}
define void @f4(i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -61,7 +61,7 @@ exit:
}
define void @f5(i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -75,7 +75,7 @@ exit:
}
define void @f6(i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
Modified: llvm/trunk/test/CodeGen/SystemZ/branch-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/branch-07.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/branch-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/branch-07.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i64 @foo()
; Test EQ.
define void @f1(i64 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -21,7 +21,7 @@ exit:
; Test NE.
define void @f2(i64 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -36,7 +36,7 @@ exit:
; Test SLE.
define void @f3(i64 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -51,7 +51,7 @@ exit:
; Test SLT.
define void @f4(i64 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -66,7 +66,7 @@ exit:
; Test SGT.
define void @f5(i64 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -81,7 +81,7 @@ exit:
; Test SGE.
define void @f6(i64 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -96,7 +96,7 @@ exit:
; Test a vector of 0/-1 results for i32 EQ.
define i64 @f7(i64 %a, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: crje {{%r[0-5]}}
; CHECK: lhi [[REG]], 0
@@ -112,7 +112,7 @@ define i64 @f7(i64 %a, i64 %b) {
; Test a vector of 0/-1 results for i32 NE.
define i64 @f8(i64 %a, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: crjlh {{%r[0-5]}}
; CHECK: lhi [[REG]], 0
@@ -128,7 +128,7 @@ define i64 @f8(i64 %a, i64 %b) {
; Test a vector of 0/-1 results for i64 EQ.
define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lghi [[REG:%r[0-5]]], -1
; CHECK: crje {{%r[0-5]}}
; CHECK: lghi [[REG]], 0
@@ -144,7 +144,7 @@ define void @f9(i64 %a, i64 %b, <2 x i64
; Test a vector of 0/-1 results for i64 NE.
define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lghi [[REG:%r[0-5]]], -1
; CHECK: crjlh {{%r[0-5]}}
; CHECK: lghi [[REG]], 0
Modified: llvm/trunk/test/CodeGen/SystemZ/bswap-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/bswap-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/bswap-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/bswap-01.ll Sun Jul 14 01:24:09 2013
@@ -7,7 +7,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
; Check 32-bit register-to-register byteswaps.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
; CHECK: br %r14
%swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
; Check 64-bit register-to-register byteswaps.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrvgr %r2, %r2
; CHECK: br %r14
%swapped = call i64 @llvm.bswap.i64(i64 %a)
Modified: llvm/trunk/test/CodeGen/SystemZ/bswap-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/bswap-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/bswap-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/bswap-02.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
; Check LRV with no displacement.
define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
%a = load i32 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 *%src) {
; Check the high end of the aligned LRV range.
define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrv %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
@@ -28,7 +28,7 @@ define i32 @f2(i32 *%src) {
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
@@ -40,7 +40,7 @@ define i32 @f3(i32 *%src) {
; Check the high end of the negative aligned LRV range.
define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lrv %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
@@ -51,7 +51,7 @@ define i32 @f4(i32 *%src) {
; Check the low end of the LRV range.
define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lrv %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
@@ -63,7 +63,7 @@ define i32 @f5(i32 *%src) {
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
@@ -75,7 +75,7 @@ define i32 @f6(i32 *%src) {
; Check that LRV allows an index.
define i32 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i32 @f7(i64 %src, i64 %index) {
; Check that volatile accesses do not use LRV, which might access the
; storage multple times.
define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: l [[REG:%r[0-5]]], 0(%r2)
; CHECK: lrvr %r2, [[REG]]
; CHECK: br %r14
@@ -101,7 +101,7 @@ define i32 @f8(i32 *%src) {
; Test a case where we spill the source of at least one LRVR. We want
; to use LRV if possible.
define void @f9(i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
Modified: llvm/trunk/test/CodeGen/SystemZ/bswap-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/bswap-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/bswap-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/bswap-03.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
; Check LRVG with no displacement.
define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
%a = load i64 *%src
@@ -16,7 +16,7 @@ define i64 @f1(i64 *%src) {
; Check the high end of the aligned LRVG range.
define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrvg %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
@@ -28,7 +28,7 @@ define i64 @f2(i64 *%src) {
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 *%src) {
; Check the high end of the negative aligned LRVG range.
define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lrvg %r2, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
@@ -51,7 +51,7 @@ define i64 @f4(i64 *%src) {
; Check the low end of the LRVG range.
define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lrvg %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
@@ -63,7 +63,7 @@ define i64 @f5(i64 *%src) {
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
@@ -75,7 +75,7 @@ define i64 @f6(i64 *%src) {
; Check that LRVG allows an index.
define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i64 @f7(i64 %src, i64 %index) {
; Check that volatile accesses do not use LRVG, which might access the
; storage multple times.
define i64 @f8(i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
; CHECK: lrvgr %r2, [[REG]]
; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f8(i64 *%src) {
; Test a case where we spill the source of at least one LRVGR. We want
; to use LRVG if possible.
define void @f9(i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
Modified: llvm/trunk/test/CodeGen/SystemZ/bswap-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/bswap-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/bswap-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/bswap-04.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
; Check STRV with no displacement.
define void @f1(i32 *%dst, i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
%swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define void @f1(i32 *%dst, i32 %a) {
; Check the high end of the aligned STRV range.
define void @f2(i32 *%dst, i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strv %r3, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 131071
@@ -28,7 +28,7 @@ define void @f2(i32 *%dst, i32 %a) {
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i32 *%dst, i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i32 *%dst, i32 %a) {
; Check the high end of the negative aligned STRV range.
define void @f4(i32 *%dst, i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strv %r3, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i32 *%dst, i32 %a) {
; Check the low end of the STRV range.
define void @f5(i32 *%dst, i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strv %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -131072
@@ -63,7 +63,7 @@ define void @f5(i32 *%dst, i32 %a) {
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i32 *%dst, i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i32 *%dst, i32 %a) {
; Check that STRV allows an index.
define void @f7(i64 %src, i64 %index, i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i3
; Check that volatile stores do not use STRV, which might access the
; storage multple times.
define void @f8(i32 *%dst, i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lrvr [[REG:%r[0-5]]], %r3
; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/bswap-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/bswap-05.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/bswap-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/bswap-05.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
; Check STRVG with no displacement.
define void @f1(i64 *%dst, i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
%swapped = call i64 @llvm.bswap.i64(i64 %a)
@@ -16,7 +16,7 @@ define void @f1(i64 *%dst, i64 %a) {
; Check the high end of the aligned STRVG range.
define void @f2(i64 *%dst, i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strvg %r3, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 65535
@@ -28,7 +28,7 @@ define void @f2(i64 *%dst, i64 %a) {
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i64 *%dst, i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i64 *%dst, i64 %a) {
; Check the high end of the negative aligned STRVG range.
define void @f4(i64 *%dst, i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strvg %r3, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i64 *%dst, i64 %a) {
; Check the low end of the STRVG range.
define void @f5(i64 *%dst, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strvg %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -65536
@@ -63,7 +63,7 @@ define void @f5(i64 *%dst, i64 %a) {
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 *%dst, i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i64 *%dst, i64 %a) {
; Check that STRVG allows an index.
define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i6
; Check that volatile stores do not use STRVG, which might access the
; storage multple times.
define void @f8(i64 *%dst, i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lrvgr [[REG:%r[0-5]]], %r3
; CHECK: stg [[REG]], 0(%r2)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/call-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/call-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/call-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/call-01.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare i64 @bar()
; We must allocate 160 bytes for the callee and save and restore %r14.
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: aghi %r15, -160
; CHECK: brasl %r14, bar at PLT
Modified: llvm/trunk/test/CodeGen/SystemZ/call-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/call-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/call-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/call-02.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; We must allocate 160 bytes for the callee and save and restore %r14.
define i64 @f1(i64() *%bar) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: aghi %r15, -160
; CHECK: basr %r14, %r2
Modified: llvm/trunk/test/CodeGen/SystemZ/cmpxchg-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cmpxchg-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cmpxchg-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cmpxchg-01.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %c
; CHECK-MAIN-NOT: %r2
; CHECK-MAIN: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %c
; Check compare and swap with constants. We should force the constants into
; registers and use the sequence above.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[CMP:%r[0-9]+]], 42
; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
; CHECK: risbg
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
; CHECK-SHIFT: risbg
; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
Modified: llvm/trunk/test/CodeGen/SystemZ/cmpxchg-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cmpxchg-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cmpxchg-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cmpxchg-02.ll Sun Jul 14 01:24:09 2013
@@ -11,7 +11,7 @@
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 %dummy, i16 *%src, i1
; CHECK-MAIN-NOT: %r2
; CHECK-MAIN: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i16 @f1(i16 %dummy, i16 *%src, i1
; Check compare and swap with constants. We should force the constants into
; registers and use the sequence above.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[CMP:%r[0-9]+]], 42
; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0
; CHECK: risbg
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
; CHECK-SHIFT: risbg
; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0
Modified: llvm/trunk/test/CodeGen/SystemZ/cmpxchg-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cmpxchg-03.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cmpxchg-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cmpxchg-03.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check the low end of the CS range.
define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
%val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
@@ -13,7 +13,7 @@ define i32 @f1(i32 %cmp, i32 %swap, i32
; Check the high end of the aligned CS range.
define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cs %r2, %r3, 4092(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32
; Check the next word up, which should use CSY instead of CS.
define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: csy %r2, %r3, 4096(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32
; Check the high end of the aligned CSY range.
define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: csy %r2, %r3, 524284(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r4, 524288
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32
; Check the high end of the negative aligned CSY range.
define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: csy %r2, %r3, -4(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32
; Check the low end of the CSY range.
define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: csy %r2, %r3, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, -524292
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32
; Check that CS does not allow an index.
define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r4, %r5
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f9(i32 %cmp, i32 %swap, i64
; Check that CSY does not allow an index.
define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r4, %r5
; CHECK: csy %r2, %r3, 4096(%r4)
; CHECK: br %r14
@@ -112,7 +112,7 @@ define i32 @f10(i32 %cmp, i32 %swap, i64
; Check that a constant %cmp value is loaded into a register first.
define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lhi %r2, 1001
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f11(i32 %dummy, i32 %swap, i
; Check that a constant %swap value is loaded into a register first.
define i32 @f12(i32 %cmp, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
; CHECK: cs %r2, [[SWAP]], 0(%r3)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/cmpxchg-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cmpxchg-04.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cmpxchg-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cmpxchg-04.ll Sun Jul 14 01:24:09 2013
@@ -4,7 +4,7 @@
; Check CSG without a displacement.
define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
%val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst
@@ -13,7 +13,7 @@ define i64 @f1(i64 %cmp, i64 %swap, i64
; Check the high end of the aligned CSG range.
define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: csg %r2, %r3, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r4, 524288
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64
; Check the high end of the negative aligned CSG range.
define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: csg %r2, %r3, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64
; Check the low end of the CSG range.
define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: csg %r2, %r3, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r4, -524296
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64
; Check that CSG does not allow an index.
define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agr %r4, %r5
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -79,7 +79,7 @@ define i64 @f7(i64 %cmp, i64 %swap, i64
; Check that a constant %cmp value is loaded into a register first.
define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lghi %r2, 1001
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %dummy, i64 %swap, i6
; Check that a constant %swap value is loaded into a register first.
define i64 @f9(i64 %cmp, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
; CHECK: csg %r2, [[SWAP]], 0(%r3)
; CHECK: br %r14
Modified: llvm/trunk/test/CodeGen/SystemZ/cond-store-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-store-01.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-store-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-store-01.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare void @foo(i8 *)
; Test the simple case, with the loaded value first.
define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %
; ...and with the loaded value second
define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %
; Test cases where the value is explicitly sign-extended to 32 bits, with the
; loaded value first.
define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32
; ...and with the loaded value second
define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i8 *%ptr, i32 %alt, i32
; Test cases where the value is explicitly zero-extended to 32 bits, with the
; loaded value first.
define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32
; ...and with the loaded value second
define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i8 *%ptr, i32 %alt, i32
; Test cases where the value is explicitly sign-extended to 64 bits, with the
; loaded value first.
define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32
; ...and with the loaded value second
define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i8 *%ptr, i64 %alt, i32
; Test cases where the value is explicitly zero-extended to 64 bits, with the
; loaded value first.
define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32
; ...and with the loaded value second
define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i8 *%ptr, i64 %alt, i32
; Check the high end of the STC range.
define void @f11(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i8 *%base, i8 %alt, i32
; Check the next byte up, which should use STCY instead of STC.
define void @f12(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i8 *%base, i8 %alt, i32
; Check the high end of the STCY range.
define void @f13(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i8 *%base, i8 %alt, i32
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f14(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i8 *%base, i8 %alt, i32
; Check the low end of the STCY range.
define void @f15(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i8 *%base, i8 %alt, i32
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f16(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i8 *%base, i8 %alt, i32
; Check that STCY allows an index.
define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index,
; Check that volatile loads are not matched.
define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: lb {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lb %r3, 0(%r2)
; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i8 *%ptr, i8 %alt, i32
; to restrict the test to a stronger ordering.
define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: cs {{%r[0-9]+}},
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32
; ...likewise stores.
define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lb %r3, 0(%r2)
; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32
; Try a frame index base.
define void @f22(i8 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: brasl %r14, foo at PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
Modified: llvm/trunk/test/CodeGen/SystemZ/cond-store-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-store-02.ll?rev=186280&r1=186279&r2=186280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-store-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-store-02.ll Sun Jul 14 01:24:09 2013
@@ -6,7 +6,7 @@ declare void @foo(i16 *)
; Test the simple case, with the loaded value first.
define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32
; ...and with the loaded value second
define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i16 *%ptr, i16 %alt, i32
; Test cases where the value is explicitly sign-extended to 32 bits, with the
; loaded value first.
define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32
; ...and with the loaded value second
define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i16 *%ptr, i32 %alt, i32
; Test cases where the value is explicitly zero-extended to 32 bits, with the
; loaded value first.
define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32
; ...and with the loaded value second
define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i16 *%ptr, i32 %alt, i32
; Test cases where the value is explicitly sign-extended to 64 bits, with the
; loaded value first.
define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32
; ...and with the loaded value second
define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i16 *%ptr, i64 %alt, i32
; Test cases where the value is explicitly zero-extended to 64 bits, with the
; loaded value first.
define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32
; ...and with the loaded value second
define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i16 *%ptr, i64 %alt, i3
; Check the high end of the aligned STH range.
define void @f11(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i16 *%base, i16 %alt, i
; Check the next halfword up, which should use STHY instead of STH.
define void @f12(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i16 *%base, i16 %alt, i
; Check the high end of the aligned STHY range.
define void @f13(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i16 *%base, i16 %alt, i
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f14(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i16 *%base, i16 %alt, i
; Check the low end of the STHY range.
define void @f15(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i16 *%base, i16 %alt, i
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f16(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i16 *%base, i16 %alt, i
; Check that STHY allows an index.
define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index,
; Check that volatile loads are not matched.
define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: lh {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i16 *%ptr, i16 %alt, i3
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lh %r3, 0(%r2)
; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i16 *%ptr, i16 %alt, i3
; to restrict the test to a stronger ordering.
define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: cs {{%r[0-9]+}},
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i16 *%ptr, i16 %alt, i3
; ...likewise stores.
define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lh %r3, 0(%r2)
; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i16 *%ptr, i16 %alt, i3
; Try a frame index base.
define void @f22(i16 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: brasl %r14, foo at PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
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