[llvm] r186032 - Remove trailing whitespac

[Stephen Lin]

Author: stephenwlin
Date: Wed Jul 10 15:47:39 2013
New Revision: 186032

URL: http://llvm.org/viewvc/llvm-project?rev=186032&view=rev
Log:
Remove trailing whitespac

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=186032&r1=186031&r2=186032&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jul 10 15:47:39 2013
@@ -6151,7 +6151,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N
       if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
                                           &DAG.getTarget().Options))
         return GetNegatedExpression(N11, DAG, LegalOperations);
-      
+
       if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
                                           &DAG.getTarget().Options))
         return GetNegatedExpression(N10, DAG, LegalOperations);
@@ -6172,7 +6172,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N
 
     // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
     // Note: Commutes FSUB operands.
-    if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) 
+    if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
       return DAG.getNode(ISD::FMA, dl, VT,
                          DAG.getNode(ISD::FNEG, dl, VT,
                          N1.getOperand(0)),