[llvm] r186009 - R600/SI: Initial support for LDS/GDS instructions
Michel Danzer
michel.daenzer at amd.com
Wed Jul 10 09:36:43 PDT 2013
Author: daenzer
Date: Wed Jul 10 11:36:43 2013
New Revision: 186009
URL: http://llvm.org/viewvc/llvm-project?rev=186009&view=rev
Log:
R600/SI: Initial support for LDS/GDS instructions
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Modified:
llvm/trunk/lib/Target/R600/SIInsertWaits.cpp
llvm/trunk/lib/Target/R600/SIInstrFormats.td
llvm/trunk/lib/Target/R600/SIInstrInfo.td
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp
Modified: llvm/trunk/lib/Target/R600/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInsertWaits.cpp?rev=186009&r1=186008&r2=186009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInsertWaits.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInsertWaits.cpp Wed Jul 10 11:36:43 2013
@@ -134,6 +134,8 @@ Counters SIInsertWaits::getHwCounts(Mach
if (TSFlags & SIInstrFlags::LGKM_CNT) {
MachineOperand &Op = MI.getOperand(0);
+ if (!Op.isReg())
+ Op = MI.getOperand(1);
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=186009&r1=186008&r2=186009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Wed Jul 10 11:36:43 2013
@@ -281,6 +281,30 @@ class VINTRP <bits <2> op, dag outs, dag
let Uses = [EXEC] in {
+class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
+ Enc64 <outs, ins, asm, pattern> {
+
+ bits<8> vdst;
+ bits<1> gds;
+ bits<8> addr;
+ bits<8> data0;
+ bits<8> data1;
+ bits<8> offset0;
+ bits<8> offset1;
+
+ let Inst{7-0} = offset0;
+ let Inst{15-8} = offset1;
+ let Inst{17} = gds;
+ let Inst{25-18} = op;
+ let Inst{31-26} = 0x36; //encoding
+ let Inst{39-32} = addr;
+ let Inst{47-40} = data0;
+ let Inst{55-48} = data1;
+ let Inst{63-56} = vdst;
+
+ let LGKM_CNT = 1;
+}
+
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64<outs, ins, asm, pattern> {
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=186009&r1=186008&r2=186009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Wed Jul 10 11:36:43 2013
@@ -287,6 +287,29 @@ class VOP3_64 <bits<9> op, string opName
// Vector I/O classes
//===----------------------------------------------------------------------===//
+class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
+ op,
+ (outs regClass:$vdst),
+ (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1),
+ asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
+ []> {
+ let mayLoad = 1;
+ let mayStore = 0;
+}
+
+class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
+ op,
+ (outs),
+ (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1),
+ asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
+ []> {
+ let mayStore = 1;
+ let mayLoad = 0;
+ let vdst = 0;
+}
+
class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs),
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=186009&r1=186008&r2=186009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Wed Jul 10 11:36:43 2013
@@ -391,6 +391,9 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x00000
} // End isCompare = 1
+def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
+def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
+
//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
Modified: llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp?rev=186009&r1=186008&r2=186009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp Wed Jul 10 11:36:43 2013
@@ -411,6 +411,7 @@ bool SILowerControlFlowPass::runOnMachin
TRI = MF.getTarget().getRegisterInfo();
bool HaveKill = false;
+ bool NeedM0 = false;
bool NeedWQM = false;
unsigned Depth = 0;
@@ -482,6 +483,13 @@ bool SILowerControlFlowPass::runOnMachin
IndirectDst(MI);
break;
+ case AMDGPU::DS_READ_B32:
+ NeedWQM = true;
+ // Fall through
+ case AMDGPU::DS_WRITE_B32:
+ NeedM0 = true;
+ break;
+
case AMDGPU::V_INTERP_P1_F32:
case AMDGPU::V_INTERP_P2_F32:
case AMDGPU::V_INTERP_MOV_F32:
@@ -492,6 +500,14 @@ bool SILowerControlFlowPass::runOnMachin
}
}
+ if (NeedM0) {
+ MachineBasicBlock &MBB = MF.front();
+ // Initialize M0 to a value that won't cause LDS access to be discarded
+ // due to offset clamping
+ BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
+ AMDGPU::M0).addImm(0xffffffff);
+ }
+
if (NeedWQM) {
MachineBasicBlock &MBB = MF.front();
BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
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