[llvm] r186000 - Reverting commit r185999 due to buildboot failure.

[Vladimir Medic]

Author: vmedic
Date: Wed Jul 10 07:26:26 2013
New Revision: 186000

URL: http://llvm.org/viewvc/llvm-project?rev=186000&view=rev
Log:
Reverting commit r185999 due to buildboot failure.

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=186000&r1=185999&r2=186000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Jul 10 07:26:26 2013
@@ -491,34 +491,6 @@ class TEQ_FM<bits<6> funct> {
 }
 
 //===----------------------------------------------------------------------===//
-//  System calls format <op|code_|funct>
-//===----------------------------------------------------------------------===//
-
-class SYS_FM<bits<6> funct>
-{
-  bits<20> code_;
-  bits<32> Inst;
-  let Inst{31-26} = 0x0;
-  let Inst{25-6} = code_;
-  let Inst{5-0}  = funct;
-}
-
-//===----------------------------------------------------------------------===//
-//  Break instruction format <op|code_1|funct>
-//===----------------------------------------------------------------------===//
-
-class BRK_FM<bits<6> funct>
-{
-  bits<10> code_1;
-  bits<10> code_2;
-  bits<32> Inst;
-  let Inst{31-26} = 0x0;
-  let Inst{25-16} = code_1;
-  let Inst{15-6}  = code_2;
-  let Inst{5-0}   = funct;
-}
-
-//===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS
 //

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=186000&r1=185999&r2=186000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Jul 10 07:26:26 2013
@@ -250,12 +250,6 @@ def simm16      : Operand<i32> {
 def simm20      : Operand<i32> {
 }
 
-def uimm20      : Operand<i32> {
-}
-
-def uimm10      : Operand<i32> {
-}
-
 def simm16_64   : Operand<i64>;
 def shamt       : Operand<i32>;
 
@@ -643,14 +637,6 @@ class BAL_FT :
   let hasDelaySlot = 1;
   let Defs = [RA];
 }
-// Syscall
-class SYS_FT<string opstr> :
-  InstSE<(outs), (ins uimm20:$code_),
-         !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
-// Break
-class BRK_FT<string opstr> :
-  InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
-         !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
 
 // Sync
 let hasSideEffects = 1 in
@@ -955,9 +941,6 @@ defm SWR : StoreLeftRightM<"swr", MipsSW
 def SYNC : SYNC_FT, SYNC_FM;
 def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
 
-def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
-def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
-
 /// Load-linked, Store-conditional
 let Predicates = [NotN64, HasStdEnc] in {
   def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
@@ -1136,10 +1119,6 @@ def : InstAlias<"bnez $rs,$offset",
 def : InstAlias<"beqz $rs,$offset",
                  (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
                  Requires<[NotMips64]>;
-def : InstAlias<"syscall", (SYSCALL 0), 1>;
-
-def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
-def : InstAlias<"break", (BREAK 0, 0), 1>;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//