[llvm] r185912 - InstCombine: X & -C != -C -> X <= u ~C

[David Majnemer]

Author: majnemer
Date: Tue Jul  9 03:09:32 2013
New Revision: 185912

URL: http://llvm.org/viewvc/llvm-project?rev=185912&view=rev
Log:
InstCombine: X & -C != -C -> X <= u ~C

Tests were added in r185910 somehow.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
    llvm/trunk/test/Transforms/InstCombine/icmp.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=185912&r1=185911&r2=185912&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Tue Jul  9 03:09:32 2013
@@ -1277,6 +1277,15 @@ Instruction *InstCombiner::visitICmpInst
               return Res;
           }
     }
+
+    // X & -C == -C -> X >  u ~C
+    // X & -C != -C -> X <= u ~C
+    //   iff C is a power of 2
+    if (ICI.isEquality() && RHS == LHSI->getOperand(1) && (-RHSV).isPowerOf2())
+      return new ICmpInst(
+          ICI.getPredicate() == ICmpInst::ICMP_EQ ? ICmpInst::ICMP_UGT
+                                                  : ICmpInst::ICMP_ULE,
+          LHSI->getOperand(0), SubOne(RHS));
     break;
 
   case Instruction::Or: {

Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=185912&r1=185911&r2=185912&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Tue Jul  9 03:09:32 2013
@@ -1164,46 +1164,6 @@ define i1 @icmp_sub_3_X_uge_2(i32 %X) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_add_X_-14_ult_2
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
-; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 14
-; CHECK-NEXT: ret i1 [[CMP]]
-define i1 @icmp_add_X_-14_ult_2(i32 %X) {
-  %add = add i32 %X, -14
-  %cmp = icmp ult i32 %add, 2
-  ret i1 %cmp
-}
-
-; CHECK: @icmp_sub_3_X_ult_2
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
-; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[OR]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
-define i1 @icmp_sub_3_X_ult_2(i32 %X) {
-  %add = sub i32 3, %X
-  %cmp = icmp ult i32 %add, 2
-  ret i1 %cmp
-}
-
-; CHECK: @icmp_add_X_-14_uge_2
-; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
-; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 14
-; CHECK-NEXT: ret i1 [[CMP]]
-define i1 @icmp_add_X_-14_uge_2(i32 %X) {
-  %add = add i32 %X, -14
-  %cmp = icmp uge i32 %add, 2
-  ret i1 %cmp
-}
-
-; CHECK: @icmp_sub_3_X_uge_2
-; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
-; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[OR]], 3
-; CHECK-NEXT: ret i1 [[CMP]]
-define i1 @icmp_sub_3_X_uge_2(i32 %X) {
-  %add = sub i32 3, %X
-  %cmp = icmp uge i32 %add, 2
-  ret i1 %cmp
-}
-
 ; CHECK: @icmp_and_X_-16_eq-16
 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -17
 ; CHECK-NEXT: ret i1 [[CMP]]