[llvm] r185527 - ARM: relax the atomic release barrier to "dmb ishst" on Swift

[Tim Northover]

> I suppose a mention of the section number in the commit message
> wouldn't be out of place though in the more esoteric cases. I'll try
> to remember in future.

Oh, and this one is mostly A3.8.3 in case anyone wants to follow
along. My favourite bit is the second item in "Group A" (things that
happen before the barrier):

"...All loads of required access type from observer..."

where "required access type" is essentially one of "load, store,
both". Suggestions of what a "load of store type" is on the back of a
postcard, please.

Tim.