[llvm] r185533 - [PowerPC] Make specialized AltiVec patterns isCodeGenOnly

[Ulrich Weigand]

Author: uweigand
Date: Wed Jul  3 07:51:09 2013
New Revision: 185533

URL: http://llvm.org/viewvc/llvm-project?rev=185533&view=rev
Log:

[PowerPC] Make specialized AltiVec patterns isCodeGenOnly

A couple of AltiVec patterns are just specialized forms of the
generic instruction pattern, and should therefore be marked
isCodeGenOnly to avoid confusing the asm parser:
VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES.

Noticed by inspection of the generated PPCGenAsmMatcher.inc.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=185533&r1=185532&r2=185533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Wed Jul  3 07:51:09 2013
@@ -392,7 +392,7 @@ def VCTUXS : VXForm_1<906, (outs vrrc:$v
 // Defines with the UIM field set to 0 for floating-point
 // to integer (fp_to_sint/fp_to_uint) conversions and integer
 // to floating-point (sint_to_fp/uint_to_fp) conversions.
-let VA = 0 in {
+let isCodeGenOnly = 1, VA = 0 in {
 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
                        "vcfsx $vD, $vB, 0", VecFP,
                        [(set v4f32:$vD,
@@ -664,7 +664,7 @@ def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $v
 def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
                       
-let isCodeGenOnly = 1 in
+let isCodeGenOnly = 1 in {
 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
                       "vxor $vD, $vD, $vD", VecFP,
                       [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
@@ -673,6 +673,7 @@ def V_SETALLONES : VXForm_3<908, (outs v
                       "vspltisw $vD, -1", VecFP,
                       [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
 }
+}
 } // VALU Operations.
 
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