[llvm] r185373 - [mips] Increase the number of floating point control registers available to 32.

[Akira Hatanaka]

Author: ahatanak
Date: Mon Jul  1 15:31:44 2013
New Revision: 185373

URL: http://llvm.org/viewvc/llvm-project?rev=185373&view=rev
Log:
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.


Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
    llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
    llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
    llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
    llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=185373&r1=185372&r2=185373&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Mon Jul  1 15:31:44 2013
@@ -248,8 +248,9 @@ let Namespace = "Mips" in {
   def LO64  : RegisterWithSubRegs<"lo", [LO]>;
   }
 
-  // Status flags register
-  def FCR31 : Register<"31">;
+  // FP control registers.
+  foreach I = 0-31 in
+  def FCR#I : MipsReg<#I, ""#I>;
 
   // fcc0 register
   def FCC0 : MipsReg<0, "fcc0">;
@@ -357,8 +358,12 @@ def AFGR64 : RegisterClass<"Mips", [f64]
 
 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
 
-// Condition Register for floating point operations
-def CCR  : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
+// FP control registers.
+def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
+          Unallocatable;
+
+// FP condition code registers.
+def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
 
 // Hi/Lo Registers
 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;

Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=185373&r1=185372&r2=185373&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Mon Jul  1 15:31:44 2013
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x46 0x00 0x39 0x8e
 
-# CHECK: cfc1  $6, $fcc0
-0x44 0x46 0x08 0x00
+# CHECK: cfc1  $6, $7
+0x44 0x46 0x38 0x00
 
 # CHECK: clo  $6, $7
 0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x70 0xe6 0x30 0x20
 
-# CHECK: ctc1  $6, $fcc0
-0x44 0xc6 0x08 0x00
+# CHECK: ctc1  $6, $7
+0x44 0xc6 0x38 0x00
 
 # CHECK: cvt.d.s $f6, $f7
 0x46 0x00 0x39 0xa1

Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=185373&r1=185372&r2=185373&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Mon Jul  1 15:31:44 2013
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x8e 0x39 0x00 0x46
 
-# CHECK: cfc1  $6, $fcc0
-0x00 0x08 0x46 0x44
+# CHECK: cfc1  $6, $7
+0x00 0x38 0x46 0x44
 
 # CHECK: clo  $6, $7
 0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x20 0x30 0xe6 0x70
 
-# CHECK: ctc1  $6, $fcc0
-0x00 0x08 0xc6 0x44
+# CHECK: ctc1  $6, $7
+0x00 0x38 0xc6 0x44
 
 # CHECK: cvt.d.s $f6, $f7
 0xa1 0x39 0x00 0x46

Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt?rev=185373&r1=185372&r2=185373&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt Mon Jul  1 15:31:44 2013
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x46 0x00 0x39 0x8e
 
-# CHECK: cfc1  $6, $fcc0
-0x44 0x46 0x08 0x00
+# CHECK: cfc1  $6, $7
+0x44 0x46 0x38 0x00
 
 # CHECK: clo  $6, $7
 0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x70 0xe6 0x30 0x20
 
-# CHECK: ctc1  $6, $fcc0
-0x44 0xc6 0x08 0x00
+# CHECK: ctc1  $6, $7
+0x44 0xc6 0x38 0x00
 
 # CHECK: cvt.d.s $f6, $f7
 0x46 0x00 0x39 0xa1

Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt?rev=185373&r1=185372&r2=185373&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt Mon Jul  1 15:31:44 2013
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x8e 0x39 0x00 0x46
 
-# CHECK: cfc1  $6, $fcc0
-0x00 0x08 0x46 0x44
+# CHECK: cfc1  $6, $7
+0x00 0x38 0x46 0x44
 
 # CHECK: clo  $6, $7
 0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x20 0x30 0xe6 0x70
 
-# CHECK: ctc1  $6, $fcc0
-0x00 0x08 0xc6 0x44
+# CHECK: ctc1  $6, $7
+0x00 0x38 0xc6 0x44
 
 # CHECK: cvt.d.s $f6, $f7
 0xa1 0x39 0x00 0x46