[llvm] r185344 - [PowerPC] Add variants of "sync" instruction
Ulrich Weigand
ulrich.weigand at de.ibm.com
Mon Jul 1 09:37:53 PDT 2013
Author: uweigand
Date: Mon Jul 1 11:37:52 2013
New Revision: 185344
URL: http://llvm.org/viewvc/llvm-project?rev=185344&view=rev
Log:
[PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=185344&r1=185343&r2=185344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Mon Jul 1 11:37:52 2013
@@ -473,8 +473,11 @@ class XForm_24<bits<6> opcode, bits<10>
class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
+ bits<2> L;
+
let Pattern = pattern;
- let Inst{6-10} = 0;
+ let Inst{6-8} = 0;
+ let Inst{9-10} = L;
let Inst{11-15} = 0;
let Inst{16-20} = 0;
let Inst{21-30} = xo;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=185344&r1=185343&r2=185344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Jul 1 11:37:52 2013
@@ -1508,9 +1508,9 @@ def : Pat<(pre_store f32:$rS, iPTR:$ptrr
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STFDUX $rS, $ptrreg, $ptroff)>;
-def SYNC : XForm_24_sync<31, 598, (outs), (ins),
- "sync", LdStSync,
- [(int_ppc_sync)]>;
+def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+ "sync $L", LdStSync, []>;
+def : Pat<(int_ppc_sync), (SYNC 0)>;
//===----------------------------------------------------------------------===//
// PPC32 Arithmetic Instructions.
@@ -2231,7 +2231,7 @@ def : Pat<(f64 (extloadf32 xaddr:$src)),
def : Pat<(f64 (fextend f32:$src)),
(COPY_TO_REGCLASS $src, F8RC)>;
-def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
+def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
@@ -2279,6 +2279,10 @@ class PPCAsmPseudo<string asm, dag iops>
def : InstAlias<"sc", (SC 0)>;
+def : InstAlias<"sync", (SYNC 0)>;
+def : InstAlias<"lwsync", (SYNC 1)>;
+def : InstAlias<"ptesync", (SYNC 2)>;
+
def : InstAlias<"xnop", (XORI R0, R0, 0)>;
def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s?rev=185344&r1=185343&r2=185344&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s Mon Jul 1 11:37:52 2013
@@ -30,7 +30,8 @@
# CHECK: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad]
stdcx. 2, 3, 4
-# FIXME: sync 2
+# CHECK: sync 2 # encoding: [0x7c,0x40,0x04,0xac]
+ sync 2
# FIXME: eieio
# FIXME: wait 2
@@ -47,10 +48,12 @@
# CHECK: ldarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xa8]
ldarx 2, 3, 4
-# CHECK: sync # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK: sync 0 # encoding: [0x7c,0x00,0x04,0xac]
sync
-# FIXME: lwsync
-# FIXME: ptesync
+# CHECK: sync 1 # encoding: [0x7c,0x20,0x04,0xac]
+ lwsync
+# CHECK: sync 2 # encoding: [0x7c,0x40,0x04,0xac]
+ ptesync
# FIXME: wait
# FIXME: waitrsv
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