[llvm] r185333 - [NVPTX] 64-bit ADDC/ADDE are not legal

[Justin Holewinski]

Author: jholewinski
Date: Mon Jul  1 07:59:04 2013
New Revision: 185333

URL: http://llvm.org/viewvc/llvm-project?rev=185333&view=rev
Log:
[NVPTX] 64-bit ADDC/ADDE are not legal

Added:
    llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll
Modified:
    llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=185333&r1=185332&r2=185333&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Mon Jul  1 07:59:04 2013
@@ -204,6 +204,9 @@ NVPTXTargetLowering::NVPTXTargetLowering
   // TRAP can be lowered to PTX trap
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
+  setOperationAction(ISD::ADDC, MVT::i64, Expand);
+  setOperationAction(ISD::ADDE, MVT::i64, Expand);
+
   // Register custom handling for vector loads/stores
   for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
        ++i) {

Added: llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll?rev=185333&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll (added)
+++ llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll Mon Jul  1 07:59:04 2013
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+
+define void @foo(i64 %a, i64 %add, i128* %retptr) {
+; CHECK:        add.s64
+; CHECK:        setp.lt.u64
+; CHECK:        setp.lt.u64
+; CHECK:        selp.b64
+; CHECK:        selp.b64
+; CHECK:        add.s64
+  %t1 = sext i64 %a to i128
+  %add2 = zext i64 %add to i128
+  %val = add i128 %t1, %add2
+  store i128 %val, i128* %retptr
+  ret void
+}