[llvm] r185331 - [NVPTX] Handle signext/zeroext attributes properly
Justin Holewinski
jholewinski at nvidia.com
Mon Jul 1 05:58:59 PDT 2013
Author: jholewinski
Date: Mon Jul 1 07:58:58 2013
New Revision: 185331
URL: http://llvm.org/viewvc/llvm-project?rev=185331&view=rev
Log:
[NVPTX] Handle signext/zeroext attributes properly
Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.
Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions
Added:
llvm/trunk/test/CodeGen/NVPTX/sext-params.ll
Modified:
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=185331&r1=185330&r2=185331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Mon Jul 1 07:58:58 2013
@@ -713,7 +713,7 @@ SDValue NVPTXTargetLowering::LowerCall(T
sz = 8;
SDValue StVal = OutVals[OIdx];
if (elemtype.getSizeInBits() < 16) {
- StVal = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, StVal);
+ StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
}
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain,
@@ -947,7 +947,7 @@ SDValue NVPTXTargetLowering::LowerCall(T
MachinePointerInfo(), false, false, false,
0);
if (elemtype.getSizeInBits() < 16) {
- theVal = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, theVal);
+ theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
}
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
@@ -1382,9 +1382,9 @@ NVPTXTargetLowering::LowerSTOREVector(SD
// Since StoreV2 is a target node, we cannot rely on DAG type legalization.
// Therefore, we must ensure the type is legal. For i1 and i8, we set the
// stored type to i16 and propogate the "real" type as the memory type.
- bool NeedSExt = false;
+ bool NeedExt = false;
if (EltVT.getSizeInBits() < 16)
- NeedSExt = true;
+ NeedExt = true;
switch (NumElts) {
default:
@@ -1407,8 +1407,8 @@ NVPTXTargetLowering::LowerSTOREVector(SD
for (unsigned i = 0; i < NumElts; ++i) {
SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
DAG.getIntPtrConstant(i));
- if (NeedSExt)
- ExtVal = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i16, ExtVal);
+ if (NeedExt)
+ ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Ops.push_back(ExtVal);
}
@@ -1614,15 +1614,18 @@ SDValue NVPTXTargetLowering::LowerFormal
aggregateIsPacked ? 1
: TD->getABITypeAlignment(
partVT.getTypeForEVT(F->getContext()));
- SDValue p;
- if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits())
- p = DAG.getExtLoad(ISD::SEXTLOAD, dl, Ins[InsIdx].VT, Root, srcAddr,
+ SDValue p;
+ if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
+ ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
+ ISD::SEXTLOAD : ISD::ZEXTLOAD;
+ p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
MachinePointerInfo(srcValue), partVT, false,
false, partAlign);
- else
+ } else {
p = DAG.getLoad(partVT, dl, Root, srcAddr,
MachinePointerInfo(srcValue), false, false, false,
partAlign);
+ }
if (p.getNode())
p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
@@ -1657,7 +1660,7 @@ SDValue NVPTXTargetLowering::LowerFormal
P.getNode()->setIROrder(idx + 1);
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
- P = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, P);
+ P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
InVals.push_back(P);
Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
++InsIdx;
@@ -1682,8 +1685,8 @@ SDValue NVPTXTargetLowering::LowerFormal
DAG.getIntPtrConstant(1));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
- Elt0 = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt0);
- Elt1 = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt1);
+ Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
+ Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
}
InVals.push_back(Elt0);
@@ -1726,7 +1729,7 @@ SDValue NVPTXTargetLowering::LowerFormal
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
DAG.getIntPtrConstant(j));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
- Elt = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt);
+ Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
InVals.push_back(Elt);
}
Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
@@ -1745,14 +1748,17 @@ SDValue NVPTXTargetLowering::LowerFormal
Value *srcValue = Constant::getNullValue(PointerType::get(
ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
SDValue p;
- if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits())
- p = DAG.getExtLoad(ISD::SEXTLOAD, dl, Ins[InsIdx].VT, Root, Arg,
+ if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
+ ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
+ ISD::SEXTLOAD : ISD::ZEXTLOAD;
+ p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
MachinePointerInfo(srcValue), ObjectVT, false, false,
- TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
- else
+ TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
+ } else {
p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
MachinePointerInfo(srcValue), false, false, false,
- TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
+ TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
+ }
if (p.getNode())
p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
Added: llvm/trunk/test/CodeGen/NVPTX/sext-params.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/sext-params.ll?rev=185331&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sext-params.ll (added)
+++ llvm/trunk/test/CodeGen/NVPTX/sext-params.ll Mon Jul 1 07:58:58 2013
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+define i8 @foo(i8 signext %a) {
+; CHECK: ld.param.s8
+ %ret = add i8 %a, 3
+ ret i8 %ret
+}
+
+define i8 @bar(i8 zeroext %a) {
+; CHECK: ld.param.u8
+ %ret = add i8 %a, 3
+ ret i8 %ret
+}
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