[llvm] r185328 - [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value

[Justin Holewinski]

Author: jholewinski
Date: Mon Jul  1 07:58:48 2013
New Revision: 185328

URL: http://llvm.org/viewvc/llvm-project?rev=185328&view=rev
Log:
[NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value

Added:
    llvm/trunk/test/CodeGen/NVPTX/ldu-i8.ll
Modified:
    llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=185328&r1=185327&r2=185328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Mon Jul  1 07:58:48 2013
@@ -2373,7 +2373,8 @@ static void ReplaceINTRINSIC_W_CHAIN(SDN
           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, &Ops[0],
                                   Ops.size(), MVT::i8, MemSD->getMemOperand());
 
-      Results.push_back(NewLD.getValue(0));
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
+                                    NewLD.getValue(0)));
       Results.push_back(NewLD.getValue(1));
     }
   }

Added: llvm/trunk/test/CodeGen/NVPTX/ldu-i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/ldu-i8.ll?rev=185328&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/ldu-i8.ll (added)
+++ llvm/trunk/test/CodeGen/NVPTX/ldu-i8.ll Mon Jul  1 07:58:48 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare i8 @llvm.nvvm.ldu.global.i.i8(i8*)
+
+define i8 @foo(i8* %a) {
+; Ensure we properly truncate off the high-order 24 bits
+; CHECK:        ldu.global.u8
+; CHECK:        cvt.u32.u16
+; CHECK:        and.b32         %r{{[0-9]+}}, %r{{[0-9]+}}, 255
+  %val = tail call i8 @llvm.nvvm.ldu.global.i.i8(i8* %a)
+  ret i8 %val
+}