[llvm] r185169 - Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
Eric Christopher
echristo at gmail.com
Fri Jun 28 11:05:44 PDT 2013
You left a bunch of warnings for unused variables in, I've fixed them
for you here:
M lib/Target/ARM/ARMISelDAGToDAG.cpp
Committed r185180
-eric
On Fri, Jun 28, 2013 at 10:26 AM, Weiming Zhao <weimingz at codeaurora.org> wrote:
> Author: weimingz
> Date: Fri Jun 28 12:26:02 2013
> New Revision: 185169
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185169&view=rev
> Log:
> Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
>
> This patch assigns paired GPRs for inline asm with
> 64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers
> like %H, %Q, %R.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=185169&r1=185168&r2=185169&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jun 28 12:26:02 2013
> @@ -464,8 +464,14 @@ bool ARMAsmPrinter::PrintAsmOperand(cons
> // This takes advantage of the 2 operand-ness of ldm/stm and that we've
> // already got the operands in registers that are operands to the
> // inline asm statement.
> -
> - O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
> + O << "{";
> + if (ARM::GPRPairRegClass.contains(RegBegin)) {
> + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
> + unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
> + O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
> + RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
> + }
> + O << ARMInstPrinter::getRegisterName(RegBegin);
>
> // FIXME: The register allocator not only may not have given us the
> // registers in sequence, but may not be in ascending registers. This
> @@ -491,6 +497,20 @@ bool ARMAsmPrinter::PrintAsmOperand(cons
> return true;
> unsigned Flags = FlagsOP.getImm();
> unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
> + unsigned RC;
> + InlineAsm::hasRegClassConstraint(Flags, RC);
> + if (RC == ARM::GPRPairRegClassID) {
> + if (NumVals != 1)
> + return true;
> + const MachineOperand &MO = MI->getOperand(OpNum);
> + if (!MO.isReg())
> + return true;
> + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
> + unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
> + ARM::gsub_0 : ARM::gsub_1);
> + O << ARMInstPrinter::getRegisterName(Reg);
> + return false;
> + }
> if (NumVals != 2)
> return true;
> unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=185169&r1=185168&r2=185169&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jun 28 12:26:02 2013
> @@ -3472,16 +3472,16 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
> // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
> // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
> // respectively. Since there is no constraint to explicitly specify a
> - // reg pair, we search %H operand inside the asm string. If it is found, the
> - // transformation below enforces a GPRPair reg class for "%r" for 64-bit data.
> - if (AsmString.find(":H}") == StringRef::npos)
> - return NULL;
> + // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
> + // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
> + // them into a GPRPair.
>
> SDLoc dl(N);
> - SDValue Glue = N->getOperand(NumOps-1);
> + SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
>
> + SmallVector<bool, 8> OpChanged;
> // Glue node will be appended late.
> - for(unsigned i = 0; i < NumOps -1; ++i) {
> + for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
> SDValue op = N->getOperand(i);
> AsmNodeOperands.push_back(op);
>
> @@ -3495,17 +3495,28 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
> else
> continue;
>
> + unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
> + if (NumRegs)
> + OpChanged.push_back(false);
> +
> + unsigned DefIdx = 0;
> + bool IsTiedToChangedOp = false;
> + // If it's a use that is tied with a previous def, it has no
> + // reg class constraint.
> + if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
> + IsTiedToChangedOp = OpChanged[DefIdx];
> +
> if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
> && Kind != InlineAsm::Kind_RegDefEarlyClobber)
> continue;
>
> - unsigned RegNum = InlineAsm::getNumOperandRegisters(Flag);
> unsigned RC;
> bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
> - if (!HasRC || RC != ARM::GPRRegClassID || RegNum != 2)
> + if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
> + || NumRegs != 2)
> continue;
>
> - assert((i+2 < NumOps-1) && "Invalid number of operands in inline asm");
> + assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
> SDValue V0 = N->getOperand(i+1);
> SDValue V1 = N->getOperand(i+2);
> unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
> @@ -3566,6 +3577,7 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
> Changed = true;
>
> if(PairedReg.getNode()) {
> + OpChanged[OpChanged.size() -1 ] = true;
> Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
> Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
> // Replace the current flag.
> @@ -3578,7 +3590,8 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
> }
> }
>
> - AsmNodeOperands.push_back(Glue);
> + if (Glue.getNode())
> + AsmNodeOperands.push_back(Glue);
> if (!Changed)
> return NULL;
>
>
> Modified: llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll?rev=185169&r1=185168&r2=185169&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/inlineasm-64bit.ll Fri Jun 28 12:26:02 2013
> @@ -1,5 +1,5 @@
> ; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi | FileCheck %s
> -
> +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
> ; check if regs are passing correctly
> define void @i64_write(i64* %p, i64 %val) nounwind {
> ; CHECK: i64_write:
> @@ -45,10 +45,43 @@ entry:
> ; check if callee-saved registers used by inline asm are saved/restored
> define void @foo(i64* %p, i64 %i) nounwind {
> ; CHECK:foo:
> -; CHECK: push {{{r[4-9]|r10|r11}}
> +; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
> ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
> ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
> -; CHECK: pop {{{r[4-9]|r10|r11}}
> +; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}
> %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind
> ret void
> }
> +
> +; return *p;
> +define i64 @ldrd_test(i64* %p) nounwind {
> +; CHECK: ldrd_test:
> + %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
> + ret i64 %1
> +}
> +
> +define i64 @QR_test(i64* %p) nounwind {
> +; CHECK: QR_test:
> +; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
> + %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
> + ret i64 %1
> +}
> +
> +define i64 @defuse_test(i64 %p) nounwind {
> +; CHECK: defuse_test:
> +; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
> + %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
> + ret i64 %1
> +}
> +
> +; *p = (hi << 32) | lo;
> +define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
> +; CHECK: strd_test:
> +; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
> + %1 = zext i32 %hi to i64
> + %2 = shl nuw i64 %1, 32
> + %3 = sext i32 %lo to i64
> + %4 = or i64 %2, %3
> + tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind
> + ret void
> +}
>
>
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