[PATCH] R600/SI: Expand v[24]i32 SETCC nodes

[Tom Stellard]

From: Tom Stellard <thomas.stellard at amd.com>

https://bugs.freedesktop.org/show_bug.cgi?id=66175
---
 lib/Target/R600/AMDGPUISelLowering.cpp |  1 +
 lib/Target/R600/R600ISelLowering.cpp   |  1 -
 lib/Target/R600/SIISelLowering.cpp     |  5 ++++-
 test/CodeGen/R600/setcc.ll             | 17 +++++++++++++++++
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 6d73590..2a22d00 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -84,6 +84,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
     setOperationAction(ISD::AND,  VT, Expand);
     setOperationAction(ISD::MUL,  VT, Expand);
     setOperationAction(ISD::OR,   VT, Expand);
+    setOperationAction(ISD::SETCC, VT, Expand);
     setOperationAction(ISD::SHL,  VT, Expand);
     setOperationAction(ISD::SRL,  VT, Expand);
     setOperationAction(ISD::SRA,  VT, Expand);
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index b898af1..9ad71bc 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -42,7 +42,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
   setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
   setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
-  setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
 
   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 9d4cfef..70be749 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -297,7 +297,10 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
   return BB;
 }
 
-EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
+EVT SITargetLowering::getSetCCResultType(LLVMContext &Ctx, EVT VT) const {
+  if (VT.isVector()) {
+    return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
+  }
   return MVT::i1;
 }
 
diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
index e3f77b1..4d9c8b2 100644
--- a/test/CodeGen/R600/setcc.ll
+++ b/test/CodeGen/R600/setcc.ll
@@ -1,9 +1,16 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ;EG-CHECK: @test2
 ;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
+;SI-CHECK: @test2
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[X:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]}}, 0, -1, [[X]]
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[Y:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]}}, 0, -1, [[Y]]
+
 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
   %a = load <2 x i32> addrspace(1) * %in
@@ -20,6 +27,16 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
 ;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
+;SI-CHECK: @test4
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[X:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]+}}, 0, -1, [[X]]
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[Y:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]+}}, 0, -1, [[Y]]
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[Z:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]+}}, 0, -1, [[Z]]
+;SI-CHECK: V_CMP_EQ_I32_e{{(32|64)}} [[W:SGPR[0-9]_SGPR[0-9]]]
+;SI-CHECK: V_CNDMASK_B32_e{{(32|64)}} VGPR{{[0-9]+}}, 0, -1, [[W]]
+
 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
-- 
1.7.11.4