[llvm] r185026 - [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
Chad Rosier
mcrosier at apple.com
Wed Jun 26 15:23:32 PDT 2013
Author: mcrosier
Date: Wed Jun 26 17:23:32 2013
New Revision: 185026
URL: http://llvm.org/viewvc/llvm-project?rev=185026&view=rev
Log:
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=185026&r1=185025&r2=185026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Jun 26 17:23:32 2013
@@ -405,7 +405,10 @@ static DecodeStatus DecodeCCRRegisterCla
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+ unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
+ Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=185026&r1=185025&r2=185026&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Wed Jun 26 17:23:32 2013
@@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e
-# CHECK: cfc1 $6, $7
-0x44 0x46 0x38 0x00
+# CHECK: cfc1 $6, $fcc0
+0x44 0x46 0x08 0x00
# CHECK: clo $6, $7
0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x70 0xe6 0x30 0x20
-# CHECK: ctc1 $6, $7
-0x44 0xc6 0x38 0x00
+# CHECK: ctc1 $6, $fcc0
+0x44 0xc6 0x08 0x00
# CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=185026&r1=185025&r2=185026&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Wed Jun 26 17:23:32 2013
@@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46
-# CHECK: cfc1 $6, $7
-0x00 0x38 0x46 0x44
+# CHECK: cfc1 $6, $fcc0
+0x00 0x08 0x46 0x44
# CHECK: clo $6, $7
0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x20 0x30 0xe6 0x70
-# CHECK: ctc1 $6, $7
-0x00 0x38 0xc6 0x44
+# CHECK: ctc1 $6, $fcc0
+0x00 0x08 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt?rev=185026&r1=185025&r2=185026&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt Wed Jun 26 17:23:32 2013
@@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e
-# CHECK: cfc1 $6, $7
-0x44 0x46 0x38 0x00
+# CHECK: cfc1 $6, $fcc0
+0x44 0x46 0x08 0x00
# CHECK: clo $6, $7
0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x70 0xe6 0x30 0x20
-# CHECK: ctc1 $6, $7
-0x44 0xc6 0x38 0x00
+# CHECK: ctc1 $6, $fcc0
+0x44 0xc6 0x08 0x00
# CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt?rev=185026&r1=185025&r2=185026&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt Wed Jun 26 17:23:32 2013
@@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46
-# CHECK: cfc1 $6, $7
-0x00 0x38 0x46 0x44
+# CHECK: cfc1 $6, $fcc0
+0x00 0x08 0x46 0x44
# CHECK: clo $6, $7
0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x20 0x30 0xe6 0x70
-# CHECK: ctc1 $6, $7
-0x00 0x38 0xc6 0x44
+# CHECK: ctc1 $6, $fcc0
+0x00 0x08 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46
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