[PATCH][TableGen][MC]Allow instruction mnemonic to contain dot character

[Vladimir Medic]

Mips FPU instructions have a size modifier that determines the size of the operand used. This modifier is introduced as a part of mnemonic marked with a dot character. For example, add.s means 32 bit FPU register addition, add.d uses 64 bit register, while add.l means that operators are fixed point registers. RegsiterOperand class is normally uset to resolve these kind of ambiguities, but currently llvm does not support dot character in mnemonic. This means that the add.s for example is in matcher tables treated as add which is integer addition, thus creating ambiguities when dedicated parser methods are called. In this patch we propose a solution to allow mnemonics in matcher tables to contain dot character. The bit field MnemonicContainsDot is added in class Instruction definition, defaulting to 0 so there is no change for targets that don't need this feature. The AsmMatcherEmitter.cpp code is modified to check for this field and allow matcher to emit dot as a part of mnemonic if set. The rest of the patch contains changes in Mips target definition files and MipsAsmParser.cpp which utilize this feature to parse FPU register operands.

I'm looking forward to your comments and remarks.

Vladimir
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