[llvm] r184822 - R600/SI: Report unaligned memory accesses as legal for > 32-bit types
Tom Stellard
thomas.stellard at amd.com
Mon Jun 24 19:39:35 PDT 2013
Author: tstellar
Date: Mon Jun 24 21:39:35 2013
New Revision: 184822
URL: http://llvm.org/viewvc/llvm-project?rev=184822&view=rev
Log:
R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space. Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.
https://bugs.freedesktop.org/show_bug.cgi?id=65873
Modified:
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/lib/Target/R600/SIISelLowering.h
llvm/trunk/test/CodeGen/R600/store.ll
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=184822&r1=184821&r2=184822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Mon Jun 24 21:39:35 2013
@@ -87,6 +87,18 @@ SITargetLowering::SITargetLowering(Targe
setSchedulingPreference(Sched::RegPressure);
}
+//===----------------------------------------------------------------------===//
+// TargetLowering queries
+//===----------------------------------------------------------------------===//
+
+bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
+ bool *IsFast) const {
+ // XXX: This depends on the address space and also we may want to revist
+ // the alignment values we specify in the DataLayout.
+ return VT.bitsGT(MVT::i32);
+}
+
+
SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT,
SDLoc DL, SDValue Chain,
unsigned Offset) const {
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.h?rev=184822&r1=184821&r2=184822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.h (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.h Mon Jun 24 21:39:35 2013
@@ -40,6 +40,7 @@ class SITargetLowering : public AMDGPUTa
public:
SITargetLowering(TargetMachine &tm);
+ bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
Modified: llvm/trunk/test/CodeGen/R600/store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store.ll?rev=184822&r1=184821&r2=184822&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store.ll Mon Jun 24 21:39:35 2013
@@ -14,3 +14,35 @@ define void @store_f32(float addrspace(1
store float %in, float addrspace(1)* %out
ret void
}
+
+; The stores in this function are combined by the optimizer to create a
+; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
+; should not try to split the 64-bit store back into 2 32-bit stores.
+;
+; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
+; be two 32-bit stores.
+
+; EG-CHECK: @vecload2
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
+; CM-CHECK: @vecload2
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; SI-CHECK: @vecload2
+; SI-CHECK: BUFFER_STORE_DWORDX2
+define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
+entry:
+ %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
+ %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
+ %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
+ store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
+ %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
+ store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
+ ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!5 = metadata !{metadata !"int", metadata !6}
+!6 = metadata !{metadata !"omnipotent char", metadata !7}
+!7 = metadata !{metadata !"Simple C/C++ TBAA"}
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