[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Weiming Zhao]

+ Tim

 

After I rebased the patch, I found 2 unit test fails:

test/CodeGen/ARM/gpr-paired-spill.ll

test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll

 

This is because now we don’t require paired GPR for thumb mode
ldrexd/strexd. 

So I updated unit test.  Tim, could you help to review it?

 

Thanks,

Weiming

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Renato Golin [mailto:renato.golin at linaro.org] 
Sent: Saturday, June 22, 2013 12:57 PM
To: Zhao
Cc: Jakob Stoklund Olesen; Måns Rullgård; Jim Grosbach; Kristof Beyls; Eric
Christopher; LLVM Commits
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

 

On 22 June 2013 18:58, <weimingz at codeaurora.org> wrote:

My patch can make integrated-as's job easier because it guarantees that an
even reg is emitted for %0 place holder and the consecutive odd reg is
available to be used.

 

Looks good to me. We can worry about %0 later.

 

cheers,

--renato

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20130624/57d06a1f/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0003-Enable-GPRPair-for-all-i64-operands-for-ARM-mode.patch
Type: application/octet-stream
Size: 8047 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20130624/57d06a1f/attachment.obj>