[llvm] r184703 - ARM: fix thumb1 nop decoding

[Amaury de la Vieuville]

Author: amaury.dlv
Date: Mon Jun 24 04:11:53 2013
New Revision: 184703

URL: http://llvm.org/viewvc/llvm-project?rev=184703&view=rev
Log:
ARM: fix thumb1 nop decoding

In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

Modified:
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/MC/ARM/thumb-nop.s
    llvm/trunk/test/MC/ARM/thumb.s
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=184703&r1=184702&r2=184703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Jun 24 04:11:53 2013
@@ -243,15 +243,6 @@ void ARMInstPrinter::printInst(const MCI
     return;
   }
 
-  // Thumb1 NOP
-  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
-      MI->getOperand(1).getReg() == ARM::R8) {
-    O << "\tnop";
-    printPredicateOperand(MI, 2, O);
-    printAnnotation(O, Annot);
-    return;
-  }
-
   // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
   // a single GPRPair reg operand is used in the .td file to replace the two

Modified: llvm/trunk/test/MC/ARM/thumb-nop.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-nop.s?rev=184703&r1=184702&r2=184703&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-nop.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-nop.s Mon Jun 24 04:11:53 2013
@@ -5,5 +5,5 @@
 
         nop
 
-@ CHECK-V6: nop                            @ encoding: [0xc0,0x46]
+@ CHECK-V6: mov r8, r8                     @ encoding: [0xc0,0x46]
 @ CHECK-V7: nop                            @ encoding: [0x00,0xbf]

Modified: llvm/trunk/test/MC/ARM/thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb.s?rev=184703&r1=184702&r2=184703&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb.s (original)
+++ llvm/trunk/test/MC/ARM/thumb.s Mon Jun 24 04:11:53 2013
@@ -42,7 +42,7 @@
 @ CHECK: bkpt  #2                       @ encoding: [0x02,0xbe]
 
         nop
-@ CHECK: nop @ encoding: [0xc0,0x46]
+@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]
 
         cpsie aif
 @ CHECK: cpsie aif                      @ encoding: [0x67,0xb6]

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=184703&r1=184702&r2=184703&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Mon Jun 24 04:11:53 2013
@@ -279,9 +279,11 @@
 #------------------------------------------------------------------------------
 # CHECK: mov r3, r4
 # CHECK: movs r1, r3
+# CHECK: mov r8, r8
 
 0x23 0x46
 0x19 0x00
+0xc0 0x46
 
 
 #------------------------------------------------------------------------------
@@ -310,14 +312,6 @@
 
 
 #------------------------------------------------------------------------------
-# NOP
-#------------------------------------------------------------------------------
-# CHECK: nop
-
-0xc0 0x46
-
-
-#------------------------------------------------------------------------------
 # ORR
 #------------------------------------------------------------------------------
 # CHECK: orrs  r3, r4