[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Måns Rullgård]

weimingz at codeaurora.org writes:

> My understanding is, To implement the %0 syntax, Integrated-AS needs to treat
> ldrd r0, [4] as
> ldrd r0, r1, [4]
>
> My patch can make integrated-as's job easier because it guarantees that an
> even reg is emitted for %0 place holder and the consecutive odd reg is
> available to be used.

Note that the first destination register MUST be even here in ARM
state.  That's an architectural requirement.

-- 
Måns Rullgård
mans at mansr.com