[Mesa-dev] [PATCH 04/12] R600/SI: Expand shl of v2i32/v4i32 for SI

[Tom Stellard]

On Thu, Jun 20, 2013 at 06:43:42PM -0500, Aaron Watry wrote:
> Also add lit test for both cases on SI, and v2i32 for evergreen.
> 
> Signed-off-by: Aaron Watry <awatry at gmail.com>
> ---
>  lib/Target/R600/SIISelLowering.cpp |  3 +++
>  test/CodeGen/R600/shl.ll           | 47 ++++++++++++++++++++++++++++++--------
>  2 files changed, 40 insertions(+), 10 deletions(-)
> 
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 30a7de5..515c7a4 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -77,6 +77,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
>    setOperationAction(ISD::OR, MVT::v2i32, Expand);
>    setOperationAction(ISD::OR, MVT::v4i32, Expand);
>  
> +  setOperationAction(ISD::SHL, MVT::v2i32, Expand);
> +  setOperationAction(ISD::SHL, MVT::v4i32, Expand);
> +
>    setOperationAction(ISD::SUB, MVT::v2i32, Expand);
>    setOperationAction(ISD::SUB, MVT::v4i32, Expand);
>  
> diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll
> index db970e9..d68730a 100644
> --- a/test/CodeGen/R600/shl.ll
> +++ b/test/CodeGen/R600/shl.ll
> @@ -1,16 +1,43 @@
> -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
> +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
>  
> -; CHECK: @shl_v4i32
> -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are
> +; supported.
> +
> +;EG-CHECK: @shl_v2i32
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +
> +;SI-CHECK: @shl_v2i32
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +
> +define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
> +  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
> +  %a = load <2 x i32> addrspace(1) * %in
> +  %b = load <2 x i32> addrspace(1) * %b_ptr
> +  %result = shl <2 x i32> %a, %b
> +  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
> +  ret void
> +}
> +
> +;EG-CHECK: @shl_v4i32
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +
> +;SI-CHECK: @shl_v4i32
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
>  
> -define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
> +define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> +  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
> +  %a = load <4 x i32> addrspace(1) * %in
> +  %b = load <4 x i32> addrspace(1) * %b_ptr
>    %result = shl <4 x i32> %a, %b
>    store <4 x i32> %result, <4 x i32> addrspace(1)* %out
>    ret void
>  }
> -
> -; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are
> -; supported.

We should leave this comment here.

-Tom