[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Weiming Zhao]

The syntax of %0 is not changed. 
When %0 is encountered, the first reg of GPRPair will be emitted.
GAS accepts ASM like "ldrd r0, [r4]" , but we won't replace "%0" with "r0,
r1"

Thanks,
Weiming

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-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Friday, June 21, 2013 4:43 PM
To: Renato Golin
Cc: Zhao; Måns Rullgård; Jim Grosbach; Kristof Beyls; Eric Christopher; LLVM
Commits
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM


On Jun 21, 2013, at 3:42 PM, Renato Golin <renato.golin at linaro.org> wrote:

> Folks,
> 
> Sorry for resurrecting an old thread, but this patch is really getting in
the way of building Linux with LLVM.
> 
> Can anyone that knows more about the inline asm issue review it? It looks
good to me, but I might be missing something.
> 
> Attaching the last known patch again, just in case someone missed it.

I am fine with the part that constrains all i64 asm operands to GPRPair.

I don’t understand the issues around the %0 syntax well enough to have an
opinion.

/jakob



> 
> cheers,
> --renato
> 
> 
> On 28 March 2013 17:35, Weiming Zhao <weimingz at codeaurora.org> wrote:
> 
> 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
> hosted by The Linux Foundation
> 
> 
> -----Original Message-----
> From: Måns Rullgård [mailto:mans at mansr.com]
> Sent: Wednesday, March 27, 2013 6:41 PM
> To: weimingz at codeaurora.org
> Cc: 'Måns Rullgård'; 'Jim Grosbach'; 'Renato Golin'; 'Kristof Beyls';
'Eric Christopher'; 'Jakob Stoklund Olesen'; 'LLVM Commits'
> Subject: Re: [LLVMdev] Problems with 64-bit register operands of 
> inline asm on ARM
> 
> "Weiming Zhao" <weimingz at codeaurora.org> writes:
> 
> > Hi Måns,
> >
> > If you try my patch, it supports "ldrd %0, [%1]" although my test 
> > case doesn't include that.
> >
> > The current logic is, for inline asm, LLVM just emits one reg for %x 
> > place holders.
> > For a GPRPair, when it sees %0, it emits the first sub reg.
> > When it sees %H0, it emits the second sub reg.
> 
> That matches the gcc behaviour and is what people would expect.
> 
> > On the other side, it's hard for LLVM to give a warning diagnose for 
> > your test because LLVM doesn’t even parse the instruction string 
> > inside the inline asm.
> 
> It currently fails if using the integrated assembler.  When using gas it
obviously works exactly as with gcc.
> 
> [Weiming] Exactly. But if we decide to fix it, it should be fixed by
integrated assembler. From inline asm part, we can't simply expand %0 to
(Rt, Rt+1) because it will break other cases (ldrexd/strexd) as I mentioned
before. It is also hard to specialize for ldrd/strd cse because we don't
parse the inline asm string.
> 
> Thanks,
> Weiming
> --
> Måns Rullgård
> mans at mansr.com
> 
> 
> <0002-Enable-GPRPair-for-all-i64-operands-for-ARM-mode.patch>