[llvm] r184552 - [PowerPC] Support R_PPC_REL16 family of relocations
Ulrich Weigand
ulrich.weigand at de.ibm.com
Fri Jun 21 07:44:37 PDT 2013
Author: uweigand
Date: Fri Jun 21 09:44:37 2013
New Revision: 184552
URL: http://llvm.org/viewvc/llvm-project?rev=184552&view=rev
Log:
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
Modified:
llvm/trunk/include/llvm/Object/ELF.h
llvm/trunk/include/llvm/Support/ELF.h
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
Modified: llvm/trunk/include/llvm/Object/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ELF.h?rev=184552&r1=184551&r2=184552&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ELF.h (original)
+++ llvm/trunk/include/llvm/Object/ELF.h Fri Jun 21 09:44:37 2013
@@ -2053,6 +2053,10 @@ StringRef ELFObjectFile<ELFT>::getReloca
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_LO_DS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_HI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT_DTPREL16_HA);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_LO);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_HI);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL16_HA);
default: break;
}
break;
@@ -2127,6 +2131,10 @@ StringRef ELFObjectFile<ELFT>::getReloca
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_DTPREL16_HIGHESTA);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSGD);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSLD);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_LO);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_HI);
+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL16_HA);
default: break;
}
break;
Modified: llvm/trunk/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=184552&r1=184551&r2=184552&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELF.h (original)
+++ llvm/trunk/include/llvm/Support/ELF.h Fri Jun 21 09:44:37 2013
@@ -484,7 +484,11 @@ enum {
R_PPC_GOT_DTPREL16_DS = 91,
R_PPC_GOT_DTPREL16_LO_DS = 92,
R_PPC_GOT_DTPREL16_HI = 93,
- R_PPC_GOT_DTPREL16_HA = 94
+ R_PPC_GOT_DTPREL16_HA = 94,
+ R_PPC_REL16 = 249,
+ R_PPC_REL16_LO = 250,
+ R_PPC_REL16_HI = 251,
+ R_PPC_REL16_HA = 252
};
// ELF Relocation types for PPC64
@@ -557,7 +561,11 @@ enum {
R_PPC64_DTPREL16_HIGHEST = 105,
R_PPC64_DTPREL16_HIGHESTA = 106,
R_PPC64_TLSGD = 107,
- R_PPC64_TLSLD = 108
+ R_PPC64_TLSLD = 108,
+ R_PPC64_REL16 = 249,
+ R_PPC64_REL16_LO = 250,
+ R_PPC64_REL16_HI = 251,
+ R_PPC64_REL16_HA = 252
};
// ELF Relocation types for AArch64
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=184552&r1=184551&r2=184552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Fri Jun 21 09:44:37 2013
@@ -63,6 +63,23 @@ unsigned PPCELFObjectWriter::getRelocTyp
case PPC::fixup_ppc_brcond14:
Type = ELF::R_PPC_REL14;
break;
+ case PPC::fixup_ppc_half16:
+ switch (Modifier) {
+ default: llvm_unreachable("Unsupported Modifier");
+ case MCSymbolRefExpr::VK_None:
+ Type = ELF::R_PPC_REL16;
+ break;
+ case MCSymbolRefExpr::VK_PPC_LO:
+ Type = ELF::R_PPC_REL16_LO;
+ break;
+ case MCSymbolRefExpr::VK_PPC_HI:
+ Type = ELF::R_PPC_REL16_HI;
+ break;
+ case MCSymbolRefExpr::VK_PPC_HA:
+ Type = ELF::R_PPC_REL16_HA;
+ break;
+ }
+ break;
case FK_Data_4:
case FK_PCRel_4:
Type = ELF::R_PPC_REL32;
Modified: llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-fixups.s?rev=184552&r1=184551&r2=184552&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-fixups.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-fixups.s Fri Jun 21 09:44:37 2013
@@ -87,6 +87,32 @@
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
ld 1, target at l(3)
+# CHECK: ld 1, target(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0
+ ld 1, target(3)
+
+base:
+# CHECK: li 3, target-base # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2
+ li 3, target-base
+
+# CHECK: li 3, target-base at h # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: target-base at h, kind: fixup_ppc_half16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6
+ li 3, target-base at h
+
+# CHECK: li 3, target-base at l # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: target-base at l, kind: fixup_ppc_half16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA
+ li 3, target-base at l
+
+# CHECK: li 3, target-base at ha # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT: # fixup A - offset: 2, value: target-base at ha, kind: fixup_ppc_half16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE
+ li 3, target-base at ha
+
# CHECK: ld 1, target at toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 2, value: target at toc, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
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