[llvm] r184346 - Don't cache the TLI object since we have access to it through TargetMachine already.
Bill Wendling
isanbard at gmail.com
Wed Jun 19 13:32:16 PDT 2013
Author: void
Date: Wed Jun 19 15:32:16 2013
New Revision: 184346
URL: http://llvm.org/viewvc/llvm-project?rev=184346&view=rev
Log:
Don't cache the TLI object since we have access to it through TargetMachine already.
Modified:
llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=184346&r1=184345&r2=184346&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Wed Jun 19 15:32:16 2013
@@ -50,7 +50,6 @@ class Value;
///
class FunctionLoweringInfo {
const TargetMachine &TM;
- const TargetLowering *TLI;
public:
const Function *Fn;
MachineFunction *MF;
@@ -116,7 +115,7 @@ public:
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
- explicit FunctionLoweringInfo(const TargetMachine &TM);
+ explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
/// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=184346&r1=184345&r2=184346&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Jun 19 15:32:16 2013
@@ -55,15 +55,12 @@ static bool isUsedOutsideOfDefiningBlock
return false;
}
-FunctionLoweringInfo::FunctionLoweringInfo(const TargetMachine &TM)
- : TM(TM), TLI(0) {
-}
-
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
+ const TargetLowering *TLI = TM.getTargetLowering();
+
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
- TLI = TM.getTargetLowering();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
@@ -209,7 +206,8 @@ void FunctionLoweringInfo::clear() {
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
- return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT));
+ return RegInfo->
+ createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
}
/// CreateRegs - Allocate the appropriate number of virtual registers of
@@ -220,6 +218,8 @@ unsigned FunctionLoweringInfo::CreateReg
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
+ const TargetLowering *TLI = TM.getTargetLowering();
+
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
@@ -267,6 +267,8 @@ void FunctionLoweringInfo::ComputePHILiv
if (!Ty->isIntegerTy() || Ty->isVectorTy())
return;
+ const TargetLowering *TLI = TM.getTargetLowering();
+
SmallVector<EVT, 1> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
assert(ValueVTs.size() == 1 &&
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