[PATCH 3/3] R600/SI: Expand sub for v2i32 and v4i32 for SI

[Tom Stellard]

On Mon, Jun 17, 2013 at 04:11:40PM -0500, Aaron Watry wrote:
> Also add a v2i32 test to the existing v4i32 test.
> 
> Note: v2i32 for EG seems slightly out of order based on the normal
> ordering. i.e. "SUB_INT * T..." comes before the "SUB_INT T..."
> I am not sure if this is correct, but it's how the current R600 back-end
> emits the operation order.
> 
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> Signed-off-by: Aaron Watry<awatry at gmail.com>
> ---
>  lib/Target/R600/SIISelLowering.cpp |  3 +++
>  test/CodeGen/R600/sub.ll           | 37 +++++++++++++++++++++++++++++++------
>  2 files changed, 34 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index bf4918a..ea2b123 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -68,6 +68,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
>    setOperationAction(ISD::ADD, MVT::v4i32, Expand);
>    setOperationAction(ISD::ADD, MVT::v2i32, Expand);
>  
> +  setOperationAction(ISD::SUB, MVT::v2i32, Expand);
> +  setOperationAction(ISD::SUB, MVT::v4i32, Expand);
> +
>    setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
>    setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
>  
> diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll
> index 12bfba3..10fce6c 100644
> --- a/test/CodeGen/R600/sub.ll
> +++ b/test/CodeGen/R600/sub.ll
> @@ -1,11 +1,36 @@
> -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
> +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
>  
> -;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: @test2
> +;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>  
> -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> +;SI-CHECK: @test2
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +
> +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
> +  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
> +  %a = load <2 x i32> addrspace(1) * %in
> +  %b = load <2 x i32> addrspace(1) * %b_ptr
> +  %result = sub <2 x i32> %a, %b
> +  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
> +  ret void
> +}
> +
> +;EG-CHECK: @test4
> +;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +
> +;SI-CHECK: @test4
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
> +
> +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
>    %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
>    %a = load <4 x i32> addrspace(1) * %in
>    %b = load <4 x i32> addrspace(1) * %b_ptr
> -- 
> 1.8.1.2
>