[llvm] r184175 - Use pointers to the MCAsmInfo and MCRegInfo.
David Blaikie
dblaikie at gmail.com
Tue Jun 18 11:13:20 PDT 2013
On Tue, Jun 18, 2013 at 12:20 AM, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Tue Jun 18 02:20:20 2013
> New Revision: 184175
>
> URL: http://llvm.org/viewvc/llvm-project?rev=184175&view=rev
> Log:
> Use pointers to the MCAsmInfo and MCRegInfo.
>
> Someone may want to do something crazy, like replace these objects if they
> change or something.
Reasonable people may disagree, but for myself I'd rather we keep
references wherever possible (eg: in parameters where there's no
intention to support null values) & only use pointers where we need to
be able to re-point the value. (honestly, if I were being pedantic,
I'd prefer to write a non-nullable non-owning pointer of a sort (can
only be assigned from a value/reference, not a pointer) to document
that these things can't be null - a concern I have whenever I see a
pointer)
>
> No functionality change intended.
>
> Modified:
> llvm/trunk/include/llvm/MC/MCContext.h
> llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
> llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
> llvm/trunk/lib/MC/MCAsmStreamer.cpp
> llvm/trunk/lib/MC/MCContext.cpp
> llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
> llvm/trunk/lib/MC/MCDwarf.cpp
> llvm/trunk/lib/MC/MCParser/AsmParser.cpp
> llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp
> llvm/trunk/lib/MC/MCStreamer.cpp
> llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> llvm/trunk/lib/Target/Mangler.cpp
> llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
> llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
> llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
> llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
> llvm/trunk/tools/lto/LTOCodeGenerator.cpp
> llvm/trunk/tools/lto/LTOModule.cpp
>
> Modified: llvm/trunk/include/llvm/MC/MCContext.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCContext.h (original)
> +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 18 02:20:20 2013
> @@ -52,10 +52,10 @@ namespace llvm {
> const SourceMgr *SrcMgr;
>
> /// The MCAsmInfo for this target.
> - const MCAsmInfo &MAI;
> + const MCAsmInfo *MAI;
>
> /// The MCRegisterInfo for this target.
> - const MCRegisterInfo &MRI;
> + const MCRegisterInfo *MRI;
>
> /// The MCObjectFileInfo for this target.
> const MCObjectFileInfo *MOFI;
> @@ -164,16 +164,16 @@ namespace llvm {
> MCSymbol *CreateSymbol(StringRef Name);
>
> public:
> - explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
> + explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI,
> const MCObjectFileInfo *MOFI, const SourceMgr *Mgr = 0,
> bool DoAutoReset = true);
> ~MCContext();
>
> const SourceMgr *getSourceManager() const { return SrcMgr; }
>
> - const MCAsmInfo &getAsmInfo() const { return MAI; }
> + const MCAsmInfo *getAsmInfo() const { return MAI; }
>
> - const MCRegisterInfo &getRegisterInfo() const { return MRI; }
> + const MCRegisterInfo *getRegisterInfo() const { return MRI; }
>
> const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }
>
>
> Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Jun 18 02:20:20 2013
> @@ -51,7 +51,7 @@ MCSymbol *MachineBasicBlock::getSymbol()
> if (!CachedMCSymbol) {
> const MachineFunction *MF = getParent();
> MCContext &Ctx = MF->getContext();
> - const char *Prefix = Ctx.getAsmInfo().getPrivateGlobalPrefix();
> + const char *Prefix = Ctx.getAsmInfo()->getPrivateGlobalPrefix();
> CachedMCSymbol = Ctx.GetOrCreateSymbol(Twine(Prefix) + "BB" +
> Twine(MF->getFunctionNumber()) +
> "_" + Twine(getNumber()));
>
> Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Tue Jun 18 02:20:20 2013
> @@ -253,13 +253,12 @@ void MMIAddrLabelMapCallbackPtr::allUses
> MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
> const MCRegisterInfo &MRI,
> const MCObjectFileInfo *MOFI)
> - : ImmutablePass(ID), Context(MAI, MRI, MOFI, 0, false) {
> + : ImmutablePass(ID), Context(&MAI, &MRI, MOFI, 0, false) {
> initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
> }
>
> MachineModuleInfo::MachineModuleInfo()
> - : ImmutablePass(ID),
> - Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) {
> + : ImmutablePass(ID), Context(0, 0, 0) {
> llvm_unreachable("This MachineModuleInfo constructor should never be called, "
> "MMI should always be explicitly constructed by "
> "LLVMTargetMachine");
>
> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jun 18 02:20:20 2013
> @@ -38,7 +38,7 @@ namespace {
> class MCAsmStreamer : public MCStreamer {
> protected:
> formatted_raw_ostream &OS;
> - const MCAsmInfo &MAI;
> + const MCAsmInfo *MAI;
> private:
> OwningPtr<MCInstPrinter> InstPrinter;
> OwningPtr<MCCodeEmitter> Emitter;
> @@ -312,9 +312,9 @@ void MCAsmStreamer::EmitCommentsAndEOL()
> "Comment array not newline terminated");
> do {
> // Emit a line of comments.
> - OS.PadToColumn(MAI.getCommentColumn());
> + OS.PadToColumn(MAI->getCommentColumn());
> size_t Position = Comments.find('\n');
> - OS << MAI.getCommentString() << ' ' << Comments.substr(0, Position) << '\n';
> + OS << MAI->getCommentString() << ' ' << Comments.substr(0, Position) <<'\n';
>
> Comments = Comments.substr(Position+1);
> } while (!Comments.empty());
> @@ -332,7 +332,7 @@ static inline int64_t truncateToSize(int
> void MCAsmStreamer::ChangeSection(const MCSection *Section,
> const MCExpr *Subsection) {
> assert(Section && "Cannot switch to a null section!");
> - Section->PrintSwitchToSection(MAI, OS, Subsection);
> + Section->PrintSwitchToSection(*MAI, OS, Subsection);
> }
>
> void MCAsmStreamer::EmitEHSymAttributes(const MCSymbol *Symbol,
> @@ -354,7 +354,7 @@ void MCAsmStreamer::EmitLabel(MCSymbol *
> assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
> MCStreamer::EmitLabel(Symbol);
>
> - OS << *Symbol << MAI.getLabelSuffix();
> + OS << *Symbol << MAI->getLabelSuffix();
> EmitEOL();
> }
>
> @@ -362,7 +362,7 @@ void MCAsmStreamer::EmitDebugLabel(MCSym
> assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
> MCStreamer::EmitDebugLabel(Symbol);
>
> - OS << *Symbol << MAI.getDebugLabelSuffix();
> + OS << *Symbol << MAI->getDebugLabelSuffix();
> EmitEOL();
> }
>
> @@ -370,9 +370,9 @@ void MCAsmStreamer::EmitAssemblerFlag(MC
> switch (Flag) {
> case MCAF_SyntaxUnified: OS << "\t.syntax unified"; break;
> case MCAF_SubsectionsViaSymbols: OS << ".subsections_via_symbols"; break;
> - case MCAF_Code16: OS << '\t'<< MAI.getCode16Directive(); break;
> - case MCAF_Code32: OS << '\t'<< MAI.getCode32Directive(); break;
> - case MCAF_Code64: OS << '\t'<< MAI.getCode64Directive(); break;
> + case MCAF_Code16: OS << '\t'<< MAI->getCode16Directive();break;
> + case MCAF_Code32: OS << '\t'<< MAI->getCode32Directive();break;
> + case MCAF_Code64: OS << '\t'<< MAI->getCode64Directive();break;
> }
> EmitEOL();
> }
> @@ -388,9 +388,7 @@ void MCAsmStreamer::EmitLinkerOptions(Ar
> }
>
> void MCAsmStreamer::EmitDataRegion(MCDataRegionType Kind) {
> - MCContext &Ctx = getContext();
> - const MCAsmInfo &MAI = Ctx.getAsmInfo();
> - if (!MAI.doesSupportDataRegionDirectives())
> + if (!MAI->doesSupportDataRegionDirectives())
> return;
> switch (Kind) {
> case MCDR_DataRegion: OS << "\t.data_region"; break;
> @@ -407,7 +405,7 @@ void MCAsmStreamer::EmitThumbFunc(MCSymb
> // MCSymbols when they have spaces in them.
> OS << "\t.thumb_func";
> // Only Mach-O hasSubsectionsViaSymbols()
> - if (MAI.hasSubsectionsViaSymbols())
> + if (MAI->hasSubsectionsViaSymbols())
> OS << '\t' << *Func;
> EmitEOL();
> }
> @@ -452,9 +450,9 @@ void MCAsmStreamer::EmitSymbolAttribute(
> case MCSA_ELF_TypeCommon: /// .type _foo, STT_COMMON # aka @common
> case MCSA_ELF_TypeNoType: /// .type _foo, STT_NOTYPE # aka @notype
> case MCSA_ELF_TypeGnuUniqueObject: /// .type _foo, @gnu_unique_object
> - assert(MAI.hasDotTypeDotSizeDirective() && "Symbol Attr not supported");
> + assert(MAI->hasDotTypeDotSizeDirective() && "Symbol Attr not supported");
> OS << "\t.type\t" << *Symbol << ','
> - << ((MAI.getCommentString()[0] != '@') ? '@' : '%');
> + << ((MAI->getCommentString()[0] != '@') ? '@' : '%');
> switch (Attribute) {
> default: llvm_unreachable("Unknown ELF .type");
> case MCSA_ELF_TypeFunction: OS << "function"; break;
> @@ -468,7 +466,7 @@ void MCAsmStreamer::EmitSymbolAttribute(
> EmitEOL();
> return;
> case MCSA_Global: // .globl/.global
> - OS << MAI.getGlobalDirective();
> + OS << MAI->getGlobalDirective();
> FlagMap[Symbol] |= EHGlobal;
> break;
> case MCSA_Hidden: OS << "\t.hidden\t"; break;
> @@ -490,7 +488,7 @@ void MCAsmStreamer::EmitSymbolAttribute(
> FlagMap[Symbol] |= EHWeakDefinition;
> break;
> // .weak_reference
> - case MCSA_WeakReference: OS << MAI.getWeakRefDirective(); break;
> + case MCSA_WeakReference: OS << MAI->getWeakRefDirective(); break;
> case MCSA_WeakDefAutoPrivate: OS << "\t.weak_def_can_be_hidden\t"; break;
> }
>
> @@ -529,7 +527,7 @@ void MCAsmStreamer::EmitCOFFSecRel32(MCS
> }
>
> void MCAsmStreamer::EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
> - assert(MAI.hasDotTypeDotSizeDirective());
> + assert(MAI->hasDotTypeDotSizeDirective());
> OS << "\t.size\t" << *Symbol << ", " << *Value << '\n';
> }
>
> @@ -537,7 +535,7 @@ void MCAsmStreamer::EmitCommonSymbol(MCS
> unsigned ByteAlignment) {
> OS << "\t.comm\t" << *Symbol << ',' << Size;
> if (ByteAlignment != 0) {
> - if (MAI.getCOMMDirectiveAlignmentIsInBytes())
> + if (MAI->getCOMMDirectiveAlignmentIsInBytes())
> OS << ',' << ByteAlignment;
> else
> OS << ',' << Log2_32(ByteAlignment);
> @@ -553,7 +551,7 @@ void MCAsmStreamer::EmitLocalCommonSymbo
> unsigned ByteAlign) {
> OS << "\t.lcomm\t" << *Symbol << ',' << Size;
> if (ByteAlign > 1) {
> - switch (MAI.getLCOMMDirectiveAlignmentType()) {
> + switch (MAI->getLCOMMDirectiveAlignmentType()) {
> case LCOMM::NoAlignment:
> llvm_unreachable("alignment not supported on .lcomm!");
> case LCOMM::ByteAlignment:
> @@ -644,7 +642,7 @@ void MCAsmStreamer::EmitBytes(StringRef
> if (Data.empty()) return;
>
> if (Data.size() == 1) {
> - OS << MAI.getData8bitsDirective(AddrSpace);
> + OS << MAI->getData8bitsDirective(AddrSpace);
> OS << (unsigned)(unsigned char)Data[0];
> EmitEOL();
> return;
> @@ -652,11 +650,11 @@ void MCAsmStreamer::EmitBytes(StringRef
>
> // If the data ends with 0 and the target supports .asciz, use it, otherwise
> // use .ascii
> - if (MAI.getAscizDirective() && Data.back() == 0) {
> - OS << MAI.getAscizDirective();
> + if (MAI->getAscizDirective() && Data.back() == 0) {
> + OS << MAI->getAscizDirective();
> Data = Data.substr(0, Data.size()-1);
> } else {
> - OS << MAI.getAsciiDirective();
> + OS << MAI->getAsciiDirective();
> }
>
> OS << ' ';
> @@ -676,17 +674,17 @@ void MCAsmStreamer::EmitValueImpl(const
> const char *Directive = 0;
> switch (Size) {
> default: break;
> - case 1: Directive = MAI.getData8bitsDirective(AddrSpace); break;
> - case 2: Directive = MAI.getData16bitsDirective(AddrSpace); break;
> - case 4: Directive = MAI.getData32bitsDirective(AddrSpace); break;
> + case 1: Directive = MAI->getData8bitsDirective(AddrSpace); break;
> + case 2: Directive = MAI->getData16bitsDirective(AddrSpace); break;
> + case 4: Directive = MAI->getData32bitsDirective(AddrSpace); break;
> case 8:
> - Directive = MAI.getData64bitsDirective(AddrSpace);
> + Directive = MAI->getData64bitsDirective(AddrSpace);
> // If the target doesn't support 64-bit data, emit as two 32-bit halves.
> if (Directive) break;
> int64_t IntValue;
> if (!Value->EvaluateAsAbsolute(IntValue))
> report_fatal_error("Don't know how to emit this value.");
> - if (getContext().getAsmInfo().isLittleEndian()) {
> + if (MAI->isLittleEndian()) {
> EmitIntValue((uint32_t)(IntValue >> 0 ), 4, AddrSpace);
> EmitIntValue((uint32_t)(IntValue >> 32), 4, AddrSpace);
> } else {
> @@ -707,7 +705,7 @@ void MCAsmStreamer::EmitULEB128Value(con
> EmitULEB128IntValue(IntValue);
> return;
> }
> - assert(MAI.hasLEB128() && "Cannot print a .uleb");
> + assert(MAI->hasLEB128() && "Cannot print a .uleb");
> OS << ".uleb128 " << *Value;
> EmitEOL();
> }
> @@ -718,20 +716,20 @@ void MCAsmStreamer::EmitSLEB128Value(con
> EmitSLEB128IntValue(IntValue);
> return;
> }
> - assert(MAI.hasLEB128() && "Cannot print a .sleb");
> + assert(MAI->hasLEB128() && "Cannot print a .sleb");
> OS << ".sleb128 " << *Value;
> EmitEOL();
> }
>
> void MCAsmStreamer::EmitGPRel64Value(const MCExpr *Value) {
> - assert(MAI.getGPRel64Directive() != 0);
> - OS << MAI.getGPRel64Directive() << *Value;
> + assert(MAI->getGPRel64Directive() != 0);
> + OS << MAI->getGPRel64Directive() << *Value;
> EmitEOL();
> }
>
> void MCAsmStreamer::EmitGPRel32Value(const MCExpr *Value) {
> - assert(MAI.getGPRel32Directive() != 0);
> - OS << MAI.getGPRel32Directive() << *Value;
> + assert(MAI->getGPRel32Directive() != 0);
> + OS << MAI->getGPRel32Directive() << *Value;
> EmitEOL();
> }
>
> @@ -743,7 +741,7 @@ void MCAsmStreamer::EmitFill(uint64_t Nu
> if (NumBytes == 0) return;
>
> if (AddrSpace == 0)
> - if (const char *ZeroDirective = MAI.getZeroDirective()) {
> + if (const char *ZeroDirective = MAI->getZeroDirective()) {
> OS << ZeroDirective << NumBytes;
> if (FillValue != 0)
> OS << ',' << (int)FillValue;
> @@ -763,14 +761,14 @@ void MCAsmStreamer::EmitValueToAlignment
> if (isPowerOf2_32(ByteAlignment)) {
> switch (ValueSize) {
> default: llvm_unreachable("Invalid size for machine code value!");
> - case 1: OS << MAI.getAlignDirective(); break;
> + case 1: OS << MAI->getAlignDirective(); break;
> // FIXME: use MAI for this!
> case 2: OS << ".p2alignw "; break;
> case 4: OS << ".p2alignl "; break;
> case 8: llvm_unreachable("Unsupported alignment size!");
> }
>
> - if (MAI.getAlignmentIsInBytes())
> + if (MAI->getAlignmentIsInBytes())
> OS << ByteAlignment;
> else
> OS << Log2_32(ByteAlignment);
> @@ -806,7 +804,7 @@ void MCAsmStreamer::EmitValueToAlignment
> void MCAsmStreamer::EmitCodeAlignment(unsigned ByteAlignment,
> unsigned MaxBytesToEmit) {
> // Emit with a text fill value.
> - EmitValueToAlignment(ByteAlignment, MAI.getTextAlignFillValue(),
> + EmitValueToAlignment(ByteAlignment, MAI->getTextAlignFillValue(),
> 1, MaxBytesToEmit);
> }
>
> @@ -820,7 +818,7 @@ bool MCAsmStreamer::EmitValueToOffset(co
>
>
> void MCAsmStreamer::EmitFileDirective(StringRef Filename) {
> - assert(MAI.hasSingleParameterDotFile());
> + assert(MAI->hasSingleParameterDotFile());
> OS << "\t.file\t";
> PrintQuotedString(Filename, OS);
> EmitEOL();
> @@ -886,8 +884,8 @@ void MCAsmStreamer::EmitDwarfLocDirectiv
> OS << "discriminator " << Discriminator;
>
> if (IsVerboseAsm) {
> - OS.PadToColumn(MAI.getCommentColumn());
> - OS << MAI.getCommentString() << ' ' << FileName << ':'
> + OS.PadToColumn(MAI->getCommentColumn());
> + OS << MAI->getCommentString() << ' ' << FileName << ':'
> << Line << ':' << Column;
> }
> EmitEOL();
> @@ -936,9 +934,9 @@ void MCAsmStreamer::EmitCFIEndProcImpl(M
> }
>
> void MCAsmStreamer::EmitRegisterName(int64_t Register) {
> - if (InstPrinter && !MAI.useDwarfRegNumForCFI()) {
> - const MCRegisterInfo &MRI = getContext().getRegisterInfo();
> - unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true);
> + if (InstPrinter && !MAI->useDwarfRegNumForCFI()) {
> + const MCRegisterInfo *MRI = getContext().getRegisterInfo();
> + unsigned LLVMRegister = MRI->getLLVMRegNum(Register, true);
> InstPrinter->printRegName(OS, LLVMRegister);
> } else {
> OS << Register;
> @@ -1276,7 +1274,7 @@ void MCAsmStreamer::AddEncodingComment(c
> unsigned Bit = (Code[i] >> j) & 1;
>
> unsigned FixupBit;
> - if (getContext().getAsmInfo().isLittleEndian())
> + if (MAI->isLittleEndian())
> FixupBit = i * 8 + j;
> else
> FixupBit = i * 8 + (7-j);
> @@ -1376,7 +1374,7 @@ void MCAsmStreamer::EmitInstruction(cons
>
> // Show the MCInst if enabled.
> if (ShowInst) {
> - Inst.dump_pretty(GetCommentOS(), &MAI, InstPrinter.get(), "\n ");
> + Inst.dump_pretty(GetCommentOS(), MAI, InstPrinter.get(), "\n ");
> GetCommentOS() << "\n";
> }
>
> @@ -1384,7 +1382,7 @@ void MCAsmStreamer::EmitInstruction(cons
> if (InstPrinter)
> InstPrinter->printInst(&Inst, OS, "");
> else
> - Inst.print(OS, &MAI);
> + Inst.print(OS, MAI);
> EmitEOL();
> }
>
>
> Modified: llvm/trunk/lib/MC/MCContext.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCContext.cpp (original)
> +++ llvm/trunk/lib/MC/MCContext.cpp Tue Jun 18 02:20:20 2013
> @@ -32,7 +32,7 @@ typedef StringMap<const MCSectionELF*> E
> typedef StringMap<const MCSectionCOFF*> COFFUniqueMapTy;
>
>
> -MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri,
> +MCContext::MCContext(const MCAsmInfo *mai, const MCRegisterInfo *mri,
> const MCObjectFileInfo *mofi, const SourceMgr *mgr,
> bool DoAutoReset) :
> SrcMgr(mgr), MAI(mai), MRI(mri), MOFI(mofi),
> @@ -130,7 +130,7 @@ MCSymbol *MCContext::CreateSymbol(String
> // Determine whether this is an assembler temporary or normal label, if used.
> bool isTemporary = false;
> if (AllowTemporaryLabels)
> - isTemporary = Name.startswith(MAI.getPrivateGlobalPrefix());
> + isTemporary = Name.startswith(MAI->getPrivateGlobalPrefix());
>
> StringMapEntry<bool> *NameEntry = &UsedNames.GetOrCreateValue(Name);
> if (NameEntry->getValue()) {
> @@ -160,7 +160,7 @@ MCSymbol *MCContext::GetOrCreateSymbol(c
> MCSymbol *MCContext::CreateTempSymbol() {
> SmallString<128> NameSV;
> raw_svector_ostream(NameSV)
> - << MAI.getPrivateGlobalPrefix() << "tmp" << NextUniqueID++;
> + << MAI->getPrivateGlobalPrefix() << "tmp" << NextUniqueID++;
> return CreateSymbol(NameSV);
> }
>
> @@ -179,14 +179,14 @@ unsigned MCContext::GetInstance(int64_t
> }
>
> MCSymbol *MCContext::CreateDirectionalLocalSymbol(int64_t LocalLabelVal) {
> - return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) +
> + return GetOrCreateSymbol(Twine(MAI->getPrivateGlobalPrefix()) +
> Twine(LocalLabelVal) +
> "\2" +
> Twine(NextInstance(LocalLabelVal)));
> }
> MCSymbol *MCContext::GetDirectionalLocalSymbol(int64_t LocalLabelVal,
> int bORf) {
> - return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) +
> + return GetOrCreateSymbol(Twine(MAI->getPrivateGlobalPrefix()) +
> Twine(LocalLabelVal) +
> "\2" +
> Twine(GetInstance(LocalLabelVal) + bORf));
>
> Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Tue Jun 18 02:20:20 2013
> @@ -67,7 +67,7 @@ LLVMDisasmContextRef LLVMCreateDisasmCPU
> return 0;
>
> // Set up the MCContext for creating symbols and MCExpr's.
> - MCContext *Ctx = new MCContext(*MAI, *MRI, 0);
> + MCContext *Ctx = new MCContext(MAI, MRI, 0);
> if (!Ctx)
> return 0;
>
>
> Modified: llvm/trunk/lib/MC/MCDwarf.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDwarf.cpp (original)
> +++ llvm/trunk/lib/MC/MCDwarf.cpp Tue Jun 18 02:20:20 2013
> @@ -47,7 +47,7 @@ using namespace llvm;
> #define DWARF2_LINE_RANGE 14
>
> static inline uint64_t ScaleAddrDelta(MCContext &Context, uint64_t AddrDelta) {
> - unsigned MinInsnLength = Context.getAsmInfo().getMinInstAlignment();
> + unsigned MinInsnLength = Context.getAsmInfo()->getMinInstAlignment();
> if (MinInsnLength == 1)
> return AddrDelta;
> if (AddrDelta % MinInsnLength != 0) {
> @@ -176,9 +176,9 @@ static inline void EmitDwarfLineTable(MC
> // At this point we want to emit/create the sequence to encode the delta in
> // line numbers and the increment of the address from the previous Label
> // and the current Label.
> - const MCAsmInfo &asmInfo = MCOS->getContext().getAsmInfo();
> + const MCAsmInfo *asmInfo = MCOS->getContext().getAsmInfo();
> MCOS->EmitDwarfAdvanceLineAddr(LineDelta, LastLabel, Label,
> - asmInfo.getPointerSize());
> + asmInfo->getPointerSize());
>
> LastLine = it->getLine();
> LastLabel = Label;
> @@ -204,9 +204,9 @@ static inline void EmitDwarfLineTable(MC
> // Switch back the dwarf line section.
> MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfLineSection());
>
> - const MCAsmInfo &asmInfo = MCOS->getContext().getAsmInfo();
> + const MCAsmInfo *asmInfo = MCOS->getContext().getAsmInfo();
> MCOS->EmitDwarfAdvanceLineAddr(INT64_MAX, LastLabel, SectionEnd,
> - asmInfo.getPointerSize());
> + asmInfo->getPointerSize());
> }
>
> //
> @@ -271,7 +271,7 @@ const MCSymbol *MCDwarfFileTable::EmitCU
> (4 + 2 + 4)), 4, 0);
>
> // Parameters of the state machine, are next.
> - MCOS->EmitIntValue(context.getAsmInfo().getMinInstAlignment(), 1);
> + MCOS->EmitIntValue(context.getAsmInfo()->getMinInstAlignment(), 1);
> MCOS->EmitIntValue(DWARF2_LINE_DEFAULT_IS_STMT, 1);
> MCOS->EmitIntValue(DWARF2_LINE_BASE, 1);
> MCOS->EmitIntValue(DWARF2_LINE_RANGE, 1);
> @@ -332,7 +332,7 @@ const MCSymbol *MCDwarfFileTable::EmitCU
> EmitDwarfLineTable(MCOS, Sec, Line, CUID);
> }
>
> - if (MCOS->getContext().getAsmInfo().getLinkerRequiresNonEmptyDwarfLines()
> + if (MCOS->getContext().getAsmInfo()->getLinkerRequiresNonEmptyDwarfLines()
> && MCLineSectionOrder.begin() == MCLineSectionOrder.end()) {
> // The darwin9 linker has a bug (see PR8715). For for 32-bit architectures
> // it requires:
> @@ -520,8 +520,8 @@ static void EmitGenDwarfAranges(MCStream
>
> // Figure the padding after the header before the table of address and size
> // pairs who's values are PointerSize'ed.
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> - int AddrSize = asmInfo.getPointerSize();
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> + int AddrSize = asmInfo->getPointerSize();
> int Pad = 2 * AddrSize - (Length & (2 * AddrSize - 1));
> if (Pad == 2 * AddrSize)
> Pad = 0;
> @@ -601,8 +601,8 @@ static void EmitGenDwarfInfo(MCStreamer
> MCOS->EmitIntValue(0, 4);
> }
>
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> - int AddrSize = asmInfo.getPointerSize();
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> + int AddrSize = asmInfo->getPointerSize();
> // The 1 byte size of an address.
> MCOS->EmitIntValue(AddrSize, 1);
>
> @@ -729,9 +729,9 @@ static void EmitGenDwarfInfo(MCStreamer
> void MCGenDwarfInfo::Emit(MCStreamer *MCOS, const MCSymbol *LineSectionSymbol) {
> // Create the dwarf sections in this order (.debug_line already created).
> MCContext &context = MCOS->getContext();
> - const MCAsmInfo &AsmInfo = context.getAsmInfo();
> + const MCAsmInfo *AsmInfo = context.getAsmInfo();
> bool CreateDwarfSectionSymbols =
> - AsmInfo.doesDwarfUseRelocationsAcrossSections();
> + AsmInfo->doesDwarfUseRelocationsAcrossSections();
> if (!CreateDwarfSectionSymbols)
> LineSectionSymbol = NULL;
> MCSymbol *AbbrevSectionSymbol = NULL;
> @@ -807,9 +807,9 @@ void MCGenDwarfLabelEntry::Make(MCSymbol
>
> static int getDataAlignmentFactor(MCStreamer &streamer) {
> MCContext &context = streamer.getContext();
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> - int size = asmInfo.getCalleeSaveStackSlotSize();
> - if (asmInfo.isStackGrowthDirectionUp())
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> + int size = asmInfo->getCalleeSaveStackSlotSize();
> + if (asmInfo->isStackGrowthDirectionUp())
> return size;
> else
> return -size;
> @@ -823,7 +823,7 @@ static unsigned getSizeForEncoding(MCStr
> default: llvm_unreachable("Unknown Encoding");
> case dwarf::DW_EH_PE_absptr:
> case dwarf::DW_EH_PE_signed:
> - return context.getAsmInfo().getPointerSize();
> + return context.getAsmInfo()->getPointerSize();
> case dwarf::DW_EH_PE_udata2:
> case dwarf::DW_EH_PE_sdata2:
> return 2;
> @@ -839,10 +839,10 @@ static unsigned getSizeForEncoding(MCStr
> static void EmitSymbol(MCStreamer &streamer, const MCSymbol &symbol,
> unsigned symbolEncoding, const char *comment = 0) {
> MCContext &context = streamer.getContext();
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> - const MCExpr *v = asmInfo.getExprForFDESymbol(&symbol,
> - symbolEncoding,
> - streamer);
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> + const MCExpr *v = asmInfo->getExprForFDESymbol(&symbol,
> + symbolEncoding,
> + streamer);
> unsigned size = getSizeForEncoding(streamer, symbolEncoding);
> if (streamer.isVerboseAsm() && comment) streamer.AddComment(comment);
> streamer.EmitAbsValue(v, size);
> @@ -851,10 +851,10 @@ static void EmitSymbol(MCStreamer &strea
> static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol,
> unsigned symbolEncoding) {
> MCContext &context = streamer.getContext();
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> - const MCExpr *v = asmInfo.getExprForPersonalitySymbol(&symbol,
> - symbolEncoding,
> - streamer);
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> + const MCExpr *v = asmInfo->getExprForPersonalitySymbol(&symbol,
> + symbolEncoding,
> + streamer);
> unsigned size = getSizeForEncoding(streamer, symbolEncoding);
> streamer.EmitValue(v, size);
> }
> @@ -1194,7 +1194,7 @@ const MCSymbol &FrameEmitterImpl::EmitCI
> bool IsSignalFrame,
> unsigned lsdaEncoding) {
> MCContext &context = streamer.getContext();
> - const MCRegisterInfo &MRI = context.getRegisterInfo();
> + const MCRegisterInfo *MRI = context.getRegisterInfo();
> const MCObjectFileInfo *MOFI = context.getObjectFileInfo();
> bool verboseAsm = streamer.isVerboseAsm();
>
> @@ -1242,7 +1242,7 @@ const MCSymbol &FrameEmitterImpl::EmitCI
>
> // Code Alignment Factor
> if (verboseAsm) streamer.AddComment("CIE Code Alignment Factor");
> - streamer.EmitULEB128IntValue(context.getAsmInfo().getMinInstAlignment());
> + streamer.EmitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment());
>
> // Data Alignment Factor
> if (verboseAsm) streamer.AddComment("CIE Data Alignment Factor");
> @@ -1250,7 +1250,7 @@ const MCSymbol &FrameEmitterImpl::EmitCI
>
> // Return Address Register
> if (verboseAsm) streamer.AddComment("CIE Return Address Column");
> - streamer.EmitULEB128IntValue(MRI.getDwarfRegNum(MRI.getRARegister(), true));
> + streamer.EmitULEB128IntValue(MRI->getDwarfRegNum(MRI->getRARegister(), true));
>
> // Augmentation Data Length (optional)
>
> @@ -1290,14 +1290,13 @@ const MCSymbol &FrameEmitterImpl::EmitCI
>
> // Initial Instructions
>
> - const MCAsmInfo &MAI = context.getAsmInfo();
> + const MCAsmInfo *MAI = context.getAsmInfo();
> const std::vector<MCCFIInstruction> &Instructions =
> - MAI.getInitialFrameState();
> + MAI->getInitialFrameState();
> EmitCFIInstructions(streamer, Instructions, NULL);
>
> // Padding
> - streamer.EmitValueToAlignment(IsEH
> - ? 4 : context.getAsmInfo().getPointerSize());
> + streamer.EmitValueToAlignment(IsEH ? 4 : MAI->getPointerSize());
>
> streamer.EmitLabel(sectionEnd);
> return *sectionStart;
> @@ -1327,13 +1326,13 @@ MCSymbol *FrameEmitterImpl::EmitFDE(MCSt
> streamer.EmitLabel(fdeStart);
>
> // CIE Pointer
> - const MCAsmInfo &asmInfo = context.getAsmInfo();
> + const MCAsmInfo *asmInfo = context.getAsmInfo();
> if (IsEH) {
> const MCExpr *offset = MakeStartMinusEndExpr(streamer, cieStart, *fdeStart,
> 0);
> if (verboseAsm) streamer.AddComment("FDE CIE Offset");
> streamer.EmitAbsValue(offset, 4);
> - } else if (!asmInfo.doesDwarfUseRelocationsAcrossSections()) {
> + } else if (!asmInfo->doesDwarfUseRelocationsAcrossSections()) {
> const MCExpr *offset = MakeStartMinusEndExpr(streamer, *SectionStart,
> cieStart, 0);
> streamer.EmitAbsValue(offset, 4);
> @@ -1436,7 +1435,7 @@ void MCDwarfFrameEmitter::Emit(MCStreame
> if (Frame.CompactUnwindEncoding == 0) continue;
> if (!SectionEmitted) {
> Streamer.SwitchSection(MOFI->getCompactUnwindSection());
> - Streamer.EmitValueToAlignment(Context.getAsmInfo().getPointerSize());
> + Streamer.EmitValueToAlignment(Context.getAsmInfo()->getPointerSize());
> SectionEmitted = true;
> }
> Emitter.EmitCompactUnwind(Streamer, Frame);
> @@ -1472,7 +1471,7 @@ void MCDwarfFrameEmitter::Emit(MCStreame
> Streamer.EmitLabel(FDEEnd);
> }
>
> - Streamer.EmitValueToAlignment(Context.getAsmInfo().getPointerSize());
> + Streamer.EmitValueToAlignment(Context.getAsmInfo()->getPointerSize());
> if (FDEEnd)
> Streamer.EmitLabel(FDEEnd);
> }
>
> Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
> +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Tue Jun 18 02:20:20 2013
> @@ -1311,11 +1311,11 @@ bool AsmParser::ParseStatement(ParseStat
> case DK_DOUBLE:
> return ParseDirectiveRealValue(APFloat::IEEEdouble);
> case DK_ALIGN: {
> - bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
> + bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes();
> return ParseDirectiveAlign(IsPow2, /*ExprSize=*/1);
> }
> case DK_ALIGN32: {
> - bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
> + bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes();
> return ParseDirectiveAlign(IsPow2, /*ExprSize=*/4);
> }
> case DK_BALIGN:
> @@ -2730,7 +2730,7 @@ bool AsmParser::ParseRegisterOrRegisterN
> if (getLexer().isNot(AsmToken::Integer)) {
> if (getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc))
> return true;
> - Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true);
> + Register = getContext().getRegisterInfo()->getDwarfRegNum(RegNo, true);
> } else
> return parseAbsoluteExpression(Register);
>
>
> Modified: llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp (original)
> +++ llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp Tue Jun 18 02:20:20 2013
> @@ -453,7 +453,7 @@ bool COFFAsmParser::ParseAtUnwindOrAtExc
> bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) {
> SMLoc startLoc = getLexer().getLoc();
> if (getLexer().is(AsmToken::Percent)) {
> - const MCRegisterInfo &MRI = getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = getContext().getRegisterInfo();
> SMLoc endLoc;
> unsigned LLVMRegNo;
> if (getParser().getTargetParser().ParseRegister(LLVMRegNo,startLoc,endLoc))
> @@ -473,7 +473,7 @@ bool COFFAsmParser::ParseSEHRegisterNumb
> return Error(startLoc, "expected non-volatile register");
> #endif
>
> - int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo);
> + int SEHRegNo = MRI->getSEHRegNum(LLVMRegNo);
> if (SEHRegNo < 0)
> return Error(startLoc,"register can't be represented in SEH unwind info");
> RegNo = SEHRegNo;
>
> Modified: llvm/trunk/lib/MC/MCStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCStreamer.cpp Tue Jun 18 02:20:20 2013
> @@ -58,7 +58,7 @@ const MCExpr *MCStreamer::BuildSymbolDif
> }
>
> const MCExpr *MCStreamer::ForceExpAbs(const MCExpr* Expr) {
> - if (Context.getAsmInfo().hasAggressiveSymbolFolding() ||
> + if (Context.getAsmInfo()->hasAggressiveSymbolFolding() ||
> isa<MCSymbolRefExpr>(Expr))
> return Expr;
>
> @@ -92,7 +92,7 @@ void MCStreamer::EmitIntValue(uint64_t V
> assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) &&
> "Invalid size");
> char buf[8];
> - const bool isLittleEndian = Context.getAsmInfo().isLittleEndian();
> + const bool isLittleEndian = Context.getAsmInfo()->isLittleEndian();
> for (unsigned i = 0; i != Size; ++i) {
> unsigned index = isLittleEndian ? i : (Size - i - 1);
> buf[i] = uint8_t(Value >> (index * 8));
> @@ -229,7 +229,7 @@ void MCStreamer::RecordProcStart(MCDwarf
> Frame.Function = LastSymbol;
> // If the function is externally visible, we need to create a local
> // symbol to avoid relocations.
> - StringRef Prefix = getContext().getAsmInfo().getPrivateGlobalPrefix();
> + StringRef Prefix = getContext().getAsmInfo()->getPrivateGlobalPrefix();
> if (LastSymbol && LastSymbol->getName().startswith(Prefix)) {
> Frame.Begin = LastSymbol;
> } else {
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -54,7 +54,7 @@ void AArch64FrameLowering::emitPrologue(
> DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
>
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
> bool NeedsFrameMoves = MMI.hasDebugInfo()
> || MF.getFunction()->needsUnwindTableEntry();
>
> @@ -97,7 +97,7 @@ void AArch64FrameLowering::emitPrologue(
> .addSym(SPLabel);
>
> MachineLocation Dst(MachineLocation::VirtualFP);
> - unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
> + unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
> MMI.addFrameInst(
> MCCFIInstruction::createDefCfa(SPLabel, Reg, -NumInitialBytes));
> }
> @@ -132,7 +132,7 @@ void AArch64FrameLowering::emitPrologue(
> MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
> BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
> .addSym(FPLabel);
> - unsigned Reg = MRI.getDwarfRegNum(AArch64::X29, true);
> + unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
> unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
> MMI.addFrameInst(MCCFIInstruction::createDefCfa(FPLabel, Reg, Offset));
> }
> @@ -165,7 +165,7 @@ void AArch64FrameLowering::emitPrologue(
> .addSym(CSLabel);
>
> MachineLocation Dst(MachineLocation::VirtualFP);
> - unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
> + unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
> unsigned Offset = NumResidualBytes + NumInitialBytes;
> MMI.addFrameInst(MCCFIInstruction::createDefCfa(CSLabel, Reg, -Offset));
> }
> @@ -183,7 +183,7 @@ void AArch64FrameLowering::emitPrologue(
> for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
> E = CSI.end(); I != E; ++I) {
> unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
> - unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
> + unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, Reg, Offset));
> }
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -346,7 +346,7 @@ AArch64MCCodeEmitter::getMachineOpValue(
> const MCOperand &MO,
> SmallVectorImpl<MCFixup> &Fixups) const {
> if (MO.isReg()) {
> - return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
> + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
> }
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jun 18 02:20:20 2013
> @@ -277,7 +277,7 @@ public:
> MCAsmParserExtension::Initialize(_Parser);
>
> // Cache the MCRegisterInfo.
> - MRI = &getContext().getRegisterInfo();
> + MRI = getContext().getRegisterInfo();
>
> // Initialize the set of available features.
> setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
> @@ -7851,8 +7851,8 @@ bool ARMAsmParser::parseDirectiveARM(SML
> /// parseDirectiveThumbFunc
> /// ::= .thumbfunc symbol_name
> bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
> - const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
> - bool isMachO = MAI.hasSubsectionsViaSymbols();
> + const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
> + bool isMachO = MAI->hasSubsectionsViaSymbols();
> StringRef Name;
> bool needFuncName = true;
>
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp Tue Jun 18 02:20:20 2013
> @@ -380,10 +380,10 @@ void ARMELFStreamer::FlushPendingOffset(
> void ARMELFStreamer::FlushUnwindOpcodes(bool AllowCompactModel0) {
> // Emit the unwind opcode to restore $sp.
> if (UsedFP) {
> - const MCRegisterInfo &MRI = getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = getContext().getRegisterInfo();
> int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
> UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
> - UnwindOpAsm.EmitSetSP(MRI.getEncodingValue(FPReg));
> + UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg));
> } else {
> FlushPendingOffset();
> }
> @@ -458,9 +458,9 @@ void ARMELFStreamer::EmitRegSave(const S
> // Collect the registers in the register list
> unsigned Count = 0;
> uint32_t Mask = 0;
> - const MCRegisterInfo &MRI = getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = getContext().getRegisterInfo();
> for (size_t i = 0; i < RegList.size(); ++i) {
> - unsigned Reg = MRI.getEncodingValue(RegList[i]);
> + unsigned Reg = MRI->getEncodingValue(RegList[i]);
> assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
> unsigned Bit = (1u << Reg);
> if ((Mask & Bit) == 0) {
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -407,7 +407,7 @@ getMachineOpValue(const MCInst &MI, cons
> SmallVectorImpl<MCFixup> &Fixups) const {
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
>
> // Q registers are encoded as 2x their register number.
> switch (Reg) {
> @@ -436,7 +436,7 @@ EncodeAddrModeOpValues(const MCInst &MI,
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
>
> - Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
>
> int32_t SImm = MO1.getImm();
> bool isAdd = true;
> @@ -724,8 +724,8 @@ getThumbAddrModeRegRegOpValue(const MCIn
> // {2-0} = Rn
> const MCOperand &MO1 = MI.getOperand(OpIdx);
> const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> - unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
> + unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
> return (Rm << 3) | Rn;
> }
>
> @@ -741,7 +741,7 @@ getAddrModeImm12OpValue(const MCInst &MI
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
> Imm12 = 0;
> isAdd = false ; // 'U' bit is set as part of the fixup.
>
> @@ -821,7 +821,7 @@ getT2AddrModeImm8s4OpValue(const MCInst
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
> Imm8 = 0;
> isAdd = false ; // 'U' bit is set as part of the fixup.
>
> @@ -857,7 +857,7 @@ getT2AddrModeImm0_1020s4OpValue(const MC
> // {7-0} = imm8
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> - unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> unsigned Imm8 = MO1.getImm();
> return (Reg << 8) | Imm8;
> }
> @@ -940,8 +940,8 @@ getLdStSORegOpValue(const MCInst &MI, un
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx+1);
> const MCOperand &MO2 = MI.getOperand(OpIdx+2);
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> - unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> + unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
> unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
> bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
> ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
> @@ -975,7 +975,7 @@ getAddrMode2OpValue(const MCInst &MI, un
> // {12} isAdd
> // {11-0} imm12/Rm
> const MCOperand &MO = MI.getOperand(OpIdx);
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
> Binary |= Rn << 14;
> return Binary;
> @@ -998,7 +998,7 @@ getAddrMode2OffsetOpValue(const MCInst &
> ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
> Binary <<= 7; // Shift amount is bits [11:7]
> Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
> - Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
> + Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
> }
> return Binary | (isAdd << 12) | (isReg << 13);
> }
> @@ -1011,7 +1011,7 @@ getPostIdxRegOpValue(const MCInst &MI, u
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx+1);
> bool isAdd = MO1.getImm() != 0;
> - return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
> + return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
> }
>
> uint32_t ARMMCCodeEmitter::
> @@ -1029,7 +1029,7 @@ getAddrMode3OffsetOpValue(const MCInst &
> uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
> // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
> if (!isImm)
> - Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> return Imm8 | (isAdd << 8) | (isImm << 9);
> }
>
> @@ -1047,7 +1047,7 @@ getAddrMode3OpValue(const MCInst &MI, un
>
> // If The first operand isn't a register, we have a label reference.
> if (!MO.isReg()) {
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
>
> assert(MO.isExpr() && "Unexpected machine operand type!");
> const MCExpr *Expr = MO.getExpr();
> @@ -1057,14 +1057,14 @@ getAddrMode3OpValue(const MCInst &MI, un
> ++MCNumCPRelocations;
> return (Rn << 9) | (1 << 13);
> }
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> unsigned Imm = MO2.getImm();
> bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
> bool isImm = MO1.getReg() == 0;
> uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
> // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
> if (!isImm)
> - Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> + Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
> return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
> }
>
> @@ -1092,7 +1092,7 @@ getAddrModeISOpValue(const MCInst &MI, u
> // {2-0} = Rn
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> - unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> unsigned Imm5 = MO1.getImm();
> return ((Imm5 & 0x1f) << 3) | Rn;
> }
> @@ -1119,7 +1119,7 @@ getAddrMode5OpValue(const MCInst &MI, un
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
> Imm8 = 0;
> isAdd = false; // 'U' bit is handled as part of the fixup.
>
> @@ -1165,7 +1165,7 @@ getSORegRegOpValue(const MCInst &MI, uns
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
>
> // Encode Rm.
> - unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1190,7 +1190,7 @@ getSORegRegOpValue(const MCInst &MI, uns
> // Encode the shift operation Rs.
> // Encode Rs bit[11:8].
> assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
> - return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
> + return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
> }
>
> unsigned ARMMCCodeEmitter::
> @@ -1209,7 +1209,7 @@ getSORegImmOpValue(const MCInst &MI, uns
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
>
> // Encode Rm.
> - unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1248,9 +1248,9 @@ getT2AddrModeSORegOpValue(const MCInst &
>
> // Encoded as [Rn, Rm, imm].
> // FIXME: Needs fixup support.
> - unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> + unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
> Value <<= 4;
> - Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
> + Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
> Value <<= 2;
> Value |= MO3.getImm();
>
> @@ -1264,7 +1264,7 @@ getT2AddrModeImm8OpValue(const MCInst &M
> const MCOperand &MO2 = MI.getOperand(OpNum+1);
>
> // FIXME: Needs fixup support.
> - unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> + unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
>
> // Even though the immediate is 8 bits long, we need 9 bits in order
> // to represent the (inverse of the) sign bit.
> @@ -1326,7 +1326,7 @@ getT2SORegOpValue(const MCInst &MI, unsi
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
>
> // Encode Rm.
> - unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1382,7 +1382,7 @@ getRegisterListOpValue(const MCInst &MI,
>
> if (SPRRegs || DPRRegs) {
> // VLDM/VSTM
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
> unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
> Binary |= (RegNo & 0x1f) << 8;
> if (SPRRegs)
> @@ -1391,7 +1391,7 @@ getRegisterListOpValue(const MCInst &MI,
> Binary |= NumRegs * 2;
> } else {
> for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
> Binary |= 1 << RegNo;
> }
> }
> @@ -1407,7 +1407,7 @@ getAddrMode6AddressOpValue(const MCInst
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1430,7 +1430,7 @@ getAddrMode6OneLane32AddressOpValue(cons
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1456,7 +1456,7 @@ getAddrMode6DupAddressOpValue(const MCIn
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1475,7 +1475,7 @@ getAddrMode6OffsetOpValue(const MCInst &
> SmallVectorImpl<MCFixup> &Fixups) const {
> const MCOperand &MO = MI.getOperand(Op);
> if (MO.getReg() == 0) return 0x0D;
> - return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> }
>
> unsigned ARMMCCodeEmitter::
>
> Modified: llvm/trunk/lib/Target/Mangler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mangler.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mangler.cpp (original)
> +++ llvm/trunk/lib/Target/Mangler.cpp Tue Jun 18 02:20:20 2013
> @@ -47,18 +47,18 @@ static void MangleLetter(SmallVectorImpl
>
> /// NameNeedsEscaping - Return true if the identifier \p Str needs quotes
> /// for this assembler.
> -static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo &MAI) {
> +static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo *MAI) {
> assert(!Str.empty() && "Cannot create an empty MCSymbol");
>
> // If the first character is a number and the target does not allow this, we
> // need quotes.
> - if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
> + if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
> return true;
>
> // If any of the characters in the string is an unacceptable character, force
> // quotes.
> - bool AllowPeriod = MAI.doesAllowPeriodsInName();
> - bool AllowUTF8 = MAI.doesAllowUTF8();
> + bool AllowPeriod = MAI->doesAllowPeriodsInName();
> + bool AllowUTF8 = MAI->doesAllowUTF8();
> for (unsigned i = 0, e = Str.size(); i != e; ++i)
> if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
> return true;
> @@ -68,16 +68,16 @@ static bool NameNeedsEscaping(StringRef
> /// appendMangledName - Add the specified string in mangled form if it uses
> /// any unusual characters.
> static void appendMangledName(SmallVectorImpl<char> &OutName, StringRef Str,
> - const MCAsmInfo &MAI) {
> + const MCAsmInfo *MAI) {
> // The first character is not allowed to be a number unless the target
> // explicitly allows it.
> - if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
> + if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
> MangleLetter(OutName, Str[0]);
> Str = Str.substr(1);
> }
>
> - bool AllowPeriod = MAI.doesAllowPeriodsInName();
> - bool AllowUTF8 = MAI.doesAllowUTF8();
> + bool AllowPeriod = MAI->doesAllowPeriodsInName();
> + bool AllowUTF8 = MAI->doesAllowUTF8();
> for (unsigned i = 0, e = Str.size(); i != e; ++i) {
> if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
> MangleLetter(OutName, Str[i]);
> @@ -110,21 +110,21 @@ void Mangler::getNameWithPrefix(SmallVec
> StringRef Name = GVName.toStringRef(TmpData);
> assert(!Name.empty() && "getNameWithPrefix requires non-empty name");
>
> - const MCAsmInfo &MAI = Context.getAsmInfo();
> + const MCAsmInfo *MAI = Context.getAsmInfo();
>
> // If the global name is not led with \1, add the appropriate prefixes.
> if (Name[0] == '\1') {
> Name = Name.substr(1);
> } else {
> if (PrefixTy == Mangler::Private) {
> - const char *Prefix = MAI.getPrivateGlobalPrefix();
> + const char *Prefix = MAI->getPrivateGlobalPrefix();
> OutName.append(Prefix, Prefix+strlen(Prefix));
> } else if (PrefixTy == Mangler::LinkerPrivate) {
> - const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
> + const char *Prefix = MAI->getLinkerPrivateGlobalPrefix();
> OutName.append(Prefix, Prefix+strlen(Prefix));
> }
>
> - const char *Prefix = MAI.getGlobalPrefix();
> + const char *Prefix = MAI->getGlobalPrefix();
> if (Prefix[0] == 0)
> ; // Common noop, no prefix.
> else if (Prefix[1] == 0)
> @@ -137,7 +137,7 @@ void Mangler::getNameWithPrefix(SmallVec
> if (!NameNeedsEscaping(Name, MAI) ||
> // If quotes are supported, they can be used unless the string contains
> // a quote or newline.
> - (MAI.doesAllowQuotesInName() &&
> + (MAI->doesAllowQuotesInName() &&
> Name.find_first_of("\n\"") == StringRef::npos)) {
> OutName.append(Name.begin(), Name.end());
> return;
> @@ -145,7 +145,7 @@ void Mangler::getNameWithPrefix(SmallVec
>
> // On systems that do not allow quoted names, we need to mangle most
> // strange characters.
> - if (!MAI.doesAllowQuotesInName())
> + if (!MAI->doesAllowQuotesInName())
> return appendMangledName(OutName, Name, MAI);
>
> // Okay, the system allows quoted strings. We can quote most anything, the
> @@ -207,7 +207,7 @@ void Mangler::getNameWithPrefix(SmallVec
>
> // If we are supposed to add a microsoft-style suffix for stdcall/fastcall,
> // add it.
> - if (Context.getAsmInfo().hasMicrosoftFastStdCallMangling()) {
> + if (Context.getAsmInfo()->hasMicrosoftFastStdCallMangling()) {
> if (const Function *F = dyn_cast<Function>(GV)) {
> CallingConv::ID CC = F->getCallingConv();
>
>
> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Jun 18 02:20:20 2013
> @@ -880,7 +880,7 @@ int MipsAsmParser::getATReg() {
> }
>
> unsigned MipsAsmParser::getReg(int RC, int RegNo) {
> - return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
> + return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
> }
>
> int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
>
> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -380,7 +380,7 @@ getMachineOpValue(const MCInst &MI, cons
> SmallVectorImpl<MCFixup> &Fixups) const {
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
> - unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
> + unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
> return RegNo;
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
>
> Modified: llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -40,7 +40,7 @@ void Mips16FrameLowering::emitPrologue(M
> if (StackSize == 0 && !MFI->adjustsStack()) return;
>
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
> MachineLocation DstML, SrcML;
>
> // Adjust stack.
> @@ -56,13 +56,13 @@ void Mips16FrameLowering::emitPrologue(M
> MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
> BuildMI(MBB, MBBI, dl,
> TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
> - unsigned S1 = MRI.getDwarfRegNum(Mips::S1, true);
> + unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S1, -8));
>
> - unsigned S0 = MRI.getDwarfRegNum(Mips::S0, true);
> + unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S0, -12));
>
> - unsigned RA = MRI.getDwarfRegNum(Mips::RA, true);
> + unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4));
>
> if (hasFP(MF))
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -285,7 +285,7 @@ void MipsSEFrameLowering::emitPrologue(M
> if (StackSize == 0 && !MFI->adjustsStack()) return;
>
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
> MachineLocation DstML, SrcML;
>
> // Adjust stack.
> @@ -321,9 +321,9 @@ void MipsSEFrameLowering::emitPrologue(M
> // one for each of the paired single precision registers.
> if (Mips::AFGR64RegClass.contains(Reg)) {
> unsigned Reg0 =
> - MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
> + MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
> unsigned Reg1 =
> - MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
> + MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
>
> if (!STI.isLittle())
> std::swap(Reg0, Reg1);
> @@ -335,7 +335,7 @@ void MipsSEFrameLowering::emitPrologue(M
> } else {
> // Reg is either in CPURegs or FGR32.
> MMI.addFrameInst(MCCFIInstruction::createOffset(
> - CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset));
> + CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
> }
> }
> }
> @@ -358,7 +358,7 @@ void MipsSEFrameLowering::emitPrologue(M
> TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
> for (int I = 0; I < 4; ++I) {
> int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
> - unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true);
> + unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
> }
> }
> @@ -373,7 +373,7 @@ void MipsSEFrameLowering::emitPrologue(M
> BuildMI(MBB, MBBI, dl,
> TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
> MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
> - SetFPLabel, MRI.getDwarfRegNum(FP, true)));
> + SetFPLabel, MRI->getDwarfRegNum(FP, true)));
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -191,7 +191,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEnco
> // Return the thread-pointer register's encoding.
> Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
> (MCFixupKind)PPC::fixup_ppc_tlsreg));
> - return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
> + return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
> }
>
> unsigned PPCMCCodeEmitter::
> @@ -202,7 +202,7 @@ get_crbitm_encoding(const MCInst &MI, un
> MI.getOpcode() == PPC::MFOCRF ||
> MI.getOpcode() == PPC::MTCRF8) &&
> (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
> - return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> }
>
>
> @@ -214,7 +214,7 @@ getMachineOpValue(const MCInst &MI, cons
> // The GPR operand should come through here though.
> assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
> MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
> - return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
> }
>
> assert(MO.isImm() &&
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -334,7 +334,7 @@ void PPCFrameLowering::emitPrologue(Mach
> *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
>
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
> DebugLoc dl;
> bool needsFrameMoves = MMI.hasDebugInfo() ||
> MF.getFunction()->needsUnwindTableEntry();
> @@ -530,14 +530,14 @@ void PPCFrameLowering::emitPrologue(Mach
>
> if (HasFP) {
> unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
> - Reg = MRI.getDwarfRegNum(Reg, true);
> + Reg = MRI->getDwarfRegNum(Reg, true);
> MMI.addFrameInst(
> MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
> }
>
> if (MustSaveLR) {
> unsigned Reg = isPPC64 ? PPC::LR8 : PPC::LR;
> - Reg = MRI.getDwarfRegNum(Reg, true);
> + Reg = MRI->getDwarfRegNum(Reg, true);
> MMI.addFrameInst(
> MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
> }
> @@ -565,7 +565,7 @@ void PPCFrameLowering::emitPrologue(Mach
>
> unsigned Reg = HasFP ? (isPPC64 ? PPC::X31 : PPC::R31)
> : (isPPC64 ? PPC::X1 : PPC::R1);
> - Reg = MRI.getDwarfRegNum(Reg, true);
> + Reg = MRI->getDwarfRegNum(Reg, true);
> MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
> }
> }
> @@ -597,13 +597,13 @@ void PPCFrameLowering::emitPrologue(Mach
> && Subtarget.isPPC64()
> && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
> MMI.addFrameInst(MCCFIInstruction::createOffset(
> - Label, MRI.getDwarfRegNum(PPC::CR2, true), 8));
> + Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
> continue;
> }
>
> int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
> MMI.addFrameInst(MCCFIInstruction::createOffset(
> - Label, MRI.getDwarfRegNum(Reg, true), Offset));
> + Label, MRI->getDwarfRegNum(Reg, true), Offset));
> }
> }
> }
>
> Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -112,7 +112,7 @@ uint64_t SystemZMCCodeEmitter::
> getMachineOpValue(const MCInst &MI, const MCOperand &MO,
> SmallVectorImpl<MCFixup> &Fixups) const {
> if (MO.isReg())
> - return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
> + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
> if (MO.isImm())
> return static_cast<uint64_t>(MO.getImm());
> llvm_unreachable("Unexpected operand type!");
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -297,7 +297,7 @@ void SystemZFrameLowering::emitPrologue(
> SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
> MachineBasicBlock::iterator MBBI = MBB.begin();
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
> const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
> bool HasFP = hasFP(MF);
> DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
> @@ -322,7 +322,7 @@ void SystemZFrameLowering::emitPrologue(
> if (SystemZ::GR64BitRegClass.contains(Reg)) {
> int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
> MMI.addFrameInst(MCCFIInstruction::createOffset(
> - GPRSaveLabel, MRI.getDwarfRegNum(Reg, true), Offset));
> + GPRSaveLabel, MRI->getDwarfRegNum(Reg, true), Offset));
> }
> }
> }
> @@ -351,7 +351,7 @@ void SystemZFrameLowering::emitPrologue(
> MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
> BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
> .addSym(SetFPLabel);
> - unsigned HardFP = MRI.getDwarfRegNum(SystemZ::R11D, true);
> + unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
> MMI.addFrameInst(
> MCCFIInstruction::createDefCfaRegister(SetFPLabel, HardFP));
>
> @@ -379,7 +379,7 @@ void SystemZFrameLowering::emitPrologue(
> // Add CFI for the this save.
> if (!FPRSaveLabel)
> FPRSaveLabel = MMI.getContext().CreateTempSymbol();
> - unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
> + unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
> int64_t Offset = getFrameIndexOffset(MF, I->getFrameIdx());
> MMI.addFrameInst(MCCFIInstruction::createOffset(
> FPRSaveLabel, Reg, SPOffsetFromCFA + Offset));
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Tue Jun 18 02:20:20 2013
> @@ -53,7 +53,7 @@ public:
> }
>
> unsigned GetX86RegNum(const MCOperand &MO) const {
> - return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
> + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
> }
>
> // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
>
> Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Jun 18 02:20:20 2013
> @@ -307,7 +307,7 @@ void X86FrameLowering::emitCalleeSavedFr
> unsigned FramePtr) const {
> MachineFrameInfo *MFI = MF.getFrameInfo();
> MachineModuleInfo &MMI = MF.getMMI();
> - const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
> + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
>
> // Add callee saved registers to move list.
> const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
> @@ -360,7 +360,7 @@ void X86FrameLowering::emitCalleeSavedFr
> if (HasFP && FramePtr == Reg)
> continue;
>
> - unsigned DwarfReg = MRI.getDwarfRegNum(Reg, true);
> + unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
> MMI.addFrameInst(MCCFIInstruction::createOffset(Label, DwarfReg, Offset));
> }
> }
>
> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jun 18 02:20:20 2013
> @@ -388,7 +388,7 @@ int main(int argc, char **argv) {
> // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
> // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
> OwningPtr<MCObjectFileInfo> MOFI(new MCObjectFileInfo());
> - MCContext Ctx(*MAI, *MRI, MOFI.get(), &SrcMgr);
> + MCContext Ctx(MAI.get(), MRI.get(), MOFI.get(), &SrcMgr);
> MOFI->InitMCObjectFileInfo(TripleName, RelocModel, CMModel, Ctx);
>
> if (SaveTempLabels)
>
> Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
> +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Jun 18 02:20:20 2013
> @@ -310,7 +310,7 @@ static void DisassembleObject(const Obje
>
> if (Symbolize) {
> MOFI.reset(new MCObjectFileInfo);
> - Ctx.reset(new MCContext(*AsmInfo.get(), *MRI.get(), MOFI.get()));
> + Ctx.reset(new MCContext(AsmInfo.get(), MRI.get(), MOFI.get()));
> OwningPtr<MCRelocationInfo> RelInfo(
> TheTarget->createMCRelocationInfo(TripleName, *Ctx.get()));
> if (RelInfo) {
>
> Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
> +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Tue Jun 18 02:20:20 2013
> @@ -307,7 +307,7 @@ void LTOCodeGenerator::applyScopeRestric
> passes.add(createVerifierPass());
>
> // mark which symbols can not be internalized
> - MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL);
> + MCContext Context(_target->getMCAsmInfo(), _target->getRegisterInfo(), NULL);
> Mangler mangler(Context, _target);
> std::vector<const char*> mustPreserveList;
> SmallPtrSet<GlobalValue*, 8> asmUsed;
>
> Modified: llvm/trunk/tools/lto/LTOModule.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=184175&r1=184174&r2=184175&view=diff
> ==============================================================================
> --- llvm/trunk/tools/lto/LTOModule.cpp (original)
> +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 18 02:20:20 2013
> @@ -158,7 +158,7 @@ SSPBufferSize("stack-protector-buffer-si
>
> LTOModule::LTOModule(llvm::Module *m, llvm::TargetMachine *t)
> : _module(m), _target(t),
> - _context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), NULL),
> + _context(_target->getMCAsmInfo(), _target->getRegisterInfo(), NULL),
> _mangler(_context, t) {}
>
> /// isBitcodeFile - Returns 'true' if the file (or memory contents) is LLVM
>
>
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