[llvm] r183939 - [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.

Chad Rosier mcrosier at apple.com
Fri Jun 14 10:37:37 PDT 2013 

On Jun 14, 2013, at 10:34 AM, Bill Schmidt <wschmidt at linux.vnet.ibm.com> wrote:

> Sorry, I missed your other comments.  Answers below.

np, thanks.

> On Fri, 2013-06-14 at 10:10 -0700, Chad Rosier wrote:
>> Hi Bill,
>> What is the current status of fast-isel support for PowerPC?  Does the target-dependent side even exist?
>> 
>> On Jun 13, 2013, at 1:23 PM, Bill Schmidt <wschmidt at linux.vnet.ibm.com> wrote:
>> 
>>> Author: wschmidt
>>> Date: Thu Jun 13 15:23:34 2013
>>> New Revision: 183939
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=183939&view=rev
>>> Log:
>>> [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
>> 
>> The standard code path for -O0 is through fast-isel and disabling it seems to go against the grain, but I think I understand why it's necessary (i.e., the test cases we added prior to fast-isel's existence).
> 
> Exactly.  Part of the preliminary work to avoid cluttering up the
> initial fast-isel patch.
> 
>> 
>>> This is a preliminary patch for fast instruction selection on
>>> PowerPC.  Code generation can differ between DAG isel and fast isel.
>>> Existing tests that specify -O0 were written to expect DAG isel.  Make
>>> this explicit by adding -fast-isel=false to the tests.
>>> 
>>> In some cases specifying -fast-isel=false produces different code even
>>> when there isn't a fast instruction selector specified.  This is
>>> because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel
>>> object exists.  Thus disabling fast isel can actually produce less
>>> conservative code.  Because of this, some of the expected code
>>> generation in the -O0 tests needs to be adjusted.
>>> 
>>> In particular, handling of function arguments is less conservative
>>> with -fast-isel=false (see isOnlyUsedInEntryBlock() in
>>> SelectionDAGBuilder.cpp).  This results in fewer stack accesses and,
>>> in some cases, reduced stack size as uselessly loaded values are no
>>> longer stored back to spill locations in the stack.
>>> 
>>> No functional change with this patch; test case adjustments only.
>>> 
>>> Modified:
>>>   llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/floatPSA.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll
>>>   llvm/trunk/test/CodeGen/PowerPC/vrspill.ll
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
>>> +; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
>>> ; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
>>> ; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s
>>> 
>>> @@ -22,8 +22,8 @@ unequal:
>>> 
>>> ; CHECK: func1:
>>> ; CHECK: cmpld {{[0-9]+}}, 4, 5
>>> -; CHECK: std 4, -[[OFFSET1:[0-9]+]]
>>> -; CHECK: std 5, -[[OFFSET2:[0-9]+]]
>>> +; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
>>> +; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
>> 
>> I see no --check-prefix for CHECK-DAG in the command line, thus I don't think this is being tested properly.
> 
> CHECK-DAG support was added recently.  It isn't a separate check-prefix.
> It indicates that the two instructions can appear in either order, so
> using it can make tests less fragile when the instructions are
> independent.

Good to know..

> Hope this helps,

It does.. thanks, Bill.

> Bill
> 
>> 
>>> ; CHECK: ld 3, -[[OFFSET1]](1)
>>> ; CHECK: ld 3, -[[OFFSET2]](1)
>>> 
>>> @@ -65,8 +65,8 @@ unequal:
>>> ; CHECK: addi [[REG1:[0-9]+]], 1, 64
>>> ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
>>> ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
>>> -; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]]
>>> -; CHECK: std 4, -[[OFFSET2:[0-9]+]]
>>> +; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
>>> +; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
>> 
>> Same.
>> 
>>> ; CHECK: ld 3, -[[OFFSET2]](1)
>>> ; CHECK: ld 3, -[[OFFSET1]](1)
>>> 
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/emptystruct.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
>>> 
>>> ; This tests correct handling of empty aggregate parameters and return values.
>>> ; An empty parameter passed by value does not consume a protocol register or
>>> @@ -27,7 +27,6 @@ entry:
>>> 
>>> ; CHECK: callee:
>>> ; CHECK: std 4,
>>> -; CHECK: std 3,
>>> ; CHECK-NOT: std 5,
>>> ; CHECK-NOT: std 6,
>>> ; CHECK: blr
>>> @@ -45,7 +44,6 @@ entry:
>>> 
>>> ; CHECK: caller:
>>> ; CHECK: addi 4,
>>> -; CHECK: std 3,
>>> ; CHECK-NOT: std 5,
>>> ; CHECK-NOT: std 6,
>>> ; CHECK: bl callee
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/floatPSA.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/floatPSA.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/floatPSA.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/floatPSA.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
>>> +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
>>> 
>>> ; This verifies that single-precision floating point values that can't
>>> ; be passed in registers are stored in the rightmost word of the parameter
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
>>> 
>>> ; This tests receiving and re-passing parameters consisting of structures
>>> ; of size 3, 5, 6, and 7.  They are to be found/placed right-adjusted in
>>> @@ -18,25 +18,25 @@ entry:
>>>  ret void
>>> }
>>> 
>>> -; CHECK: std 6, 216(1)
>>> -; CHECK: std 5, 208(1)
>>> -; CHECK: std 4, 200(1)
>>> -; CHECK: std 3, 192(1)
>>> -; CHECK: lbz {{[0-9]+}}, 199(1)
>>> -; CHECK: lhz {{[0-9]+}}, 197(1)
>>> +; CHECK: std 6, 184(1)
>>> +; CHECK: std 5, 176(1)
>>> +; CHECK: std 4, 168(1)
>>> +; CHECK: std 3, 160(1)
>>> +; CHECK: lbz {{[0-9]+}}, 167(1)
>>> +; CHECK: lhz {{[0-9]+}}, 165(1)
>>> ; CHECK: stb {{[0-9]+}}, 55(1)
>>> ; CHECK: sth {{[0-9]+}}, 53(1)
>>> -; CHECK: lbz {{[0-9]+}}, 207(1)
>>> -; CHECK: lwz {{[0-9]+}}, 203(1)
>>> +; CHECK: lbz {{[0-9]+}}, 175(1)
>>> +; CHECK: lwz {{[0-9]+}}, 171(1)
>>> ; CHECK: stb {{[0-9]+}}, 63(1)
>>> ; CHECK: stw {{[0-9]+}}, 59(1)
>>> -; CHECK: lhz {{[0-9]+}}, 214(1)
>>> -; CHECK: lwz {{[0-9]+}}, 210(1)
>>> +; CHECK: lhz {{[0-9]+}}, 182(1)
>>> +; CHECK: lwz {{[0-9]+}}, 178(1)
>>> ; CHECK: sth {{[0-9]+}}, 70(1)
>>> ; CHECK: stw {{[0-9]+}}, 66(1)
>>> -; CHECK: lbz {{[0-9]+}}, 223(1)
>>> -; CHECK: lhz {{[0-9]+}}, 221(1)
>>> -; CHECK: lwz {{[0-9]+}}, 217(1)
>>> +; CHECK: lbz {{[0-9]+}}, 191(1)
>>> +; CHECK: lhz {{[0-9]+}}, 189(1)
>>> +; CHECK: lwz {{[0-9]+}}, 185(1)
>>> ; CHECK: stb {{[0-9]+}}, 79(1)
>>> ; CHECK: sth {{[0-9]+}}, 77(1)
>>> ; CHECK: stw {{[0-9]+}}, 73(1)
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,5 +1,5 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
>>> -; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
>>> 
>>> ; Test correct code generation for medium and large code model
>>> ; for loading a value from the constant pool (TOC-relative).
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,6 +1,6 @@
>>> -; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
>>> +; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
>>> ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
>>> -; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
>>> +; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
>>> ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
>>> 
>>> ; FIXME: When asm-parse is available, could make this an assembly test.
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
>>> 
>>> ; Verify internal alignment of long double in a struct.  The double
>>> ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
>>> 
>>> target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
>>> target triple = "powerpc64-unknown-linux-gnu"
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,4 +1,4 @@
>>> -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
>>> +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
>>> 
>>> target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
>>> target triple = "powerpc64-unknown-linux-gnu"
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PowerPC/vrspill.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vrspill.ll?rev=183939&r1=183938&r2=183939&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PowerPC/vrspill.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PowerPC/vrspill.ll Thu Jun 13 15:23:34 2013
>>> @@ -1,5 +1,5 @@
>>> -; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs  < %s | FileCheck %s
>>> -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
>>> +; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
>>> +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
>>> 
>>> ; This verifies that we generate correct spill/reload code for vector regs.
>>> 
>>> @@ -13,7 +13,6 @@ entry:
>>>  ret void
>>> }
>>> 
>>> -; CHECK: stvx 2, 1,
>>> -; CHECK: lvx 2, 1,
>>> +; CHECK: stvx 2,
>>> 
>>> declare void @foo(i32*)
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>

More information about the llvm-commits mailing list