[PATCH] ARM: fix thumb coprocessor instruction with pre-writeback disassembly
Amaury de la Vieuville
amaury.dlv at gmail.com
Thu Jun 13 09:40:26 PDT 2013
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
http://llvm-reviews.chandlerc.com/D974
Files:
lib/Target/ARM/ARMInstrThumb2.td
test/MC/Disassembler/ARM/thumb-tests.txt
Index: lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- lib/Target/ARM/ARMInstrThumb2.td
+++ lib/Target/ARM/ARMInstrThumb2.td
@@ -3632,7 +3632,7 @@
let DecoderMethod = "DecodeCopMemInstruction";
}
def _PRE : T2CI<op31_28,
- (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
+ (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
asm, "\t$cop, $CRd, $addr!"> {
bits<13> addr;
bits<4> cop;
Index: test/MC/Disassembler/ARM/thumb-tests.txt
===================================================================
--- test/MC/Disassembler/ARM/thumb-tests.txt
+++ test/MC/Disassembler/ARM/thumb-tests.txt
@@ -221,6 +221,9 @@
# CHECK: stc2 p12, c15, [r9], {137}
0x89 0xfc 0x89 0xfc
+# CHECK: stc2 p0, c0, [r0, #0]!
+0xa0 0xfd 0x00 0x00
+
# CHECK: vmov r1, r0, d11
0x50 0xec 0x1b 0x1b
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