[PATCH] Vselect improvements part 2

[Matt Arsenault]

Hi nadav,

Continuation of http://llvm-reviews.chandlerc.com/D903, but this one involves a test change, which I believe is correct but I'm not 100% sure. The test attached to the bug that this originated from seems to work. With this patch it recognizes that loading the second half of the <8 x float> is pointless.


Before:
mp_11193:                               # @mp_11193
# BB#0:                                 # %allocas
	movaps	.LCPI2_0(%rip), %xmm2
	movaps	.LCPI2_1(%rip), %xmm0
	cmpltps	%xmm2, %xmm0
	pshufb	.LCPI2_2(%rip), %xmm0
	movaps	.LCPI2_3(%rip), %xmm1
	cmpltps	%xmm2, %xmm1
	pshufb	.LCPI2_4(%rip), %xmm1
	por	%xmm0, %xmm1
	psllw	$15, %xmm1
	psraw	$15, %xmm1
	pextrb	$0, %xmm1, %eax
	shlb	$7, %al
	sarb	$7, %al
	movsbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%rsi)
	ret

After:
mp_11193:                               # @mp_11193
# BB#0:                                 # %allocas
	movaps	.LCPI2_0(%rip), %xmm0
	cmpltps	.LCPI2_1(%rip), %xmm0
	pextrb	$0, %xmm0, %eax
	shlb	$7, %al
	sarb	$7, %al
	movsbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%rsi)
	ret

http://llvm-reviews.chandlerc.com/D904

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  test/CodeGen/X86/2011-10-21-widen-cmp.ll

Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1368,16 +1368,21 @@
   SDLoc DL(N);
   GetSplitVector(N->getOperand(0), Lo0, Hi0);
   GetSplitVector(N->getOperand(1), Lo1, Hi1);
-  unsigned PartElements = Lo0.getValueType().getVectorNumElements();
-  EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
-  EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
 
-  LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
-  HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
-  SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
-  return PromoteTargetBoolean(Con, N->getValueType(0));
-}
+  EVT ResVT = N->getValueType(0);
+  EVT InVT = Lo0.getValueType();
 
+  EVT OutVT = EVT::getVectorVT(*DAG.getContext(),
+                               ResVT.getVectorElementType(),
+                               InVT.getVectorNumElements());
+
+  LoRes = DAG.getNode(ISD::SETCC, DL, OutVT, Lo0, Lo1, N->getOperand(2));
+  HiRes = DAG.getNode(ISD::SETCC, DL, OutVT, Hi0, Hi1, N->getOperand(2));
+  SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, LoRes, HiRes);
+  return ResVT.getVectorElementType() == MVT::i1
+       ? PromoteTargetBoolean(Con, N->getValueType(0))
+       : Con;
+}
 
 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
   // The result has a legal vector type, but the input needs splitting.
Index: test/CodeGen/X86/2011-10-21-widen-cmp.ll
===================================================================
--- test/CodeGen/X86/2011-10-21-widen-cmp.ll
+++ test/CodeGen/X86/2011-10-21-widen-cmp.ll
@@ -30,7 +30,11 @@
 }
 
 ; CHECK: mp_11193
-; CHECK: psraw   $15
+; CHECK: cmpltps
+; CHECK: pextrb $0
+; CHECK: shlb $7
+; CHECK: sarb $7
+; CHECK: cvtsi2ssl
 ; CHECK: ret
 define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET)
 nounwind {
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