[llvm] r182600 - R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

[Tom Stellard]

Hi Bill,

Can you cherry-pick this to the 3.3 branch.

Thanks,
Tom

On Thu, May 23, 2013 at 06:26:43PM -0000, Tom Stellard wrote:
> Author: tstellar
> Date: Thu May 23 13:26:42 2013
> New Revision: 182600
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=182600&view=rev
> Log:
> R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
> 
> Patch by: Vincent Lejeune
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=64877
> 
> NOTE: This is a candidate for the 3.3 branch.
> 
> Added:
>     llvm/trunk/test/CodeGen/R600/vtx-schedule.ll
> Modified:
>     llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp
> 
> Modified: llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp?rev=182600&r1=182599&r2=182600&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ControlFlowFinalizer.cpp Thu May 23 13:26:42 2013
> @@ -117,8 +117,15 @@ private:
>        const MachineOperand &MO = *I;
>        if (!MO.isReg())
>          continue;
> -      if (MO.isDef())
> -        DstMI = MO.getReg();
> +      if (MO.isDef()) {
> +        unsigned Reg = MO.getReg();
> +        if (AMDGPU::R600_Reg128RegClass.contains(Reg))
> +          DstMI = Reg;
> +        else
> +          DstMI = TRI.getMatchingSuperReg(Reg,
> +              TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
> +              &AMDGPU::R600_Reg128RegClass);
> +      }
>        if (MO.isUse()) {
>          unsigned Reg = MO.getReg();
>          if (AMDGPU::R600_Reg128RegClass.contains(Reg))
> 
> Added: llvm/trunk/test/CodeGen/R600/vtx-schedule.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/vtx-schedule.ll?rev=182600&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/vtx-schedule.ll (added)
> +++ llvm/trunk/test/CodeGen/R600/vtx-schedule.ll Thu May 23 13:26:42 2013
> @@ -0,0 +1,22 @@
> +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +
> +; This test is for a scheduler bug where VTX_READ instructions that used
> +; the result of another VTX_READ instruction were being grouped in the
> +; same fetch clasue.
> +
> +; CHECK: @test
> +; CHECK: Fetch clause
> +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40
> +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44
> +; CHECK: Fetch clause
> +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
> +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
> +define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) {
> +entry:
> +  %0 = load i32 addrspace(1)* %in0, align 4
> +  %1 = load i32 addrspace(1)* %in1, align 4
> +  %cmp.i = icmp slt i32 %0, %1
> +  %cond.i = select i1 %cmp.i, i32 %0, i32 %1
> +  store i32 %cond.i, i32 addrspace(1)* %out, align 4
> +  ret void
> +}
> 
> 
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