[llvm] r182486 - X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.

[Benjamin Kramer]

On 22.05.2013, at 19:01, Benjamin Kramer <benny.kra at googlemail.com> wrote:

> Author: d0k
> Date: Wed May 22 12:01:12 2013
> New Revision: 182486
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=182486&view=rev
> Log:
> X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.
> 
> Take #2 on fixing PR15977.

This is a follow up to r182364 (hopefully the last one) and should also go into 3.3.

- Ben

> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/vec_compare.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=182486&r1=182485&r2=182486&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 22 12:01:12 2013
> @@ -9358,12 +9358,19 @@ static SDValue LowerVSETCC(SDValue Op, c
>       Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
> 
>       // Since SSE has no unsigned integer comparisons, we need to flip the sign
> -      // bits of the inputs before performing those operations.
> +      // bits of the inputs before performing those operations. The lower
> +      // compare is always unsigned.
> +      SDValue SB;
>       if (FlipSigns) {
> -        SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32);
> -        Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
> -        Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
> +        SB = DAG.getConstant(0x80000000U, MVT::v4i32);
> +      } else {
> +        SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
> +        SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
> +        SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
> +                         Sign, Zero, Sign, Zero);
>       }
> +      Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
> +      Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
> 
>       // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
>       SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
> 
> Modified: llvm/trunk/test/CodeGen/X86/vec_compare.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare.ll?rev=182486&r1=182485&r2=182486&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vec_compare.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vec_compare.ll Wed May 22 12:01:12 2013
> @@ -67,7 +67,15 @@ define <2 x i64> @test6(<2 x i64> %A, <2
> }
> 
> define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
> +; CHECK: [[CONSTSEG:[A-Z0-9_]*]]:
> +; CHECK:      .long	2147483648
> +; CHECK-NEXT: .long	0
> +; CHECK-NEXT: .long	2147483648
> +; CHECK-NEXT: .long	0
> ; CHECK: test7:
> +; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
> +; CHECK: pxor [[CONSTREG]]
> +; CHECK: pxor [[CONSTREG]]
> ; CHECK: pcmpgtd %xmm1
> ; CHECK: pshufd $-96
> ; CHECK: pcmpeqd
> @@ -83,6 +91,8 @@ define <2 x i64> @test7(<2 x i64> %A, <2
> 
> define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
> ; CHECK: test8:
> +; CHECK: pxor
> +; CHECK: pxor
> ; CHECK: pcmpgtd %xmm0
> ; CHECK: pshufd $-96
> ; CHECK: pcmpeqd
> @@ -98,6 +108,8 @@ define <2 x i64> @test8(<2 x i64> %A, <2
> 
> define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
> ; CHECK: test9:
> +; CHECK: pxor
> +; CHECK: pxor
> ; CHECK: pcmpgtd %xmm0
> ; CHECK: pshufd $-96
> ; CHECK: pcmpeqd
> @@ -115,6 +127,8 @@ define <2 x i64> @test9(<2 x i64> %A, <2
> 
> define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
> ; CHECK: test10:
> +; CHECK: pxor
> +; CHECK: pxor
> ; CHECK: pcmpgtd %xmm1
> ; CHECK: pshufd $-96
> ; CHECK: pcmpeqd
> 
> 
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