[llvm] r175092 - Don't build tail calls to functions with three inreg arguments on x86-32 PIC.

[Rafael Espíndola]

looks like you forgot the testcase

On 13 February 2013 16:59, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Wed Feb 13 15:59:15 2013
> New Revision: 175092
>
> URL: http://llvm.org/viewvc/llvm-project?rev=175092&view=rev
> Log:
> Don't build tail calls to functions with three inreg arguments on x86-32 PIC.
> Fixes PR15250!
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=175092&r1=175091&r2=175092&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 13 15:59:15 2013
> @@ -2814,7 +2814,7 @@ X86TargetLowering::IsEligibleForTailCall
>                                      const SmallVectorImpl<ISD::OutputArg> &Outs,
>                                      const SmallVectorImpl<SDValue> &OutVals,
>                                      const SmallVectorImpl<ISD::InputArg> &Ins,
> -                                                     SelectionDAG& DAG) const {
> +                                                     SelectionDAG &DAG) const {
>    if (!IsTailCallConvention(CalleeCC) &&
>        CalleeCC != CallingConv::C)
>      return false;
> @@ -2853,7 +2853,7 @@ X86TargetLowering::IsEligibleForTailCall
>
>    // An stdcall caller is expected to clean up its arguments; the callee
>    // isn't going to do that.
> -  if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
> +  if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
>      return false;
>
>    // Do not sibcall optimize vararg calls unless all arguments are passed via
> @@ -2973,9 +2973,15 @@ X86TargetLowering::IsEligibleForTailCall
>      // callee-saved registers are restored. These happen to be the same
>      // registers used to pass 'inreg' arguments so watch out for those.
>      if (!Subtarget->is64Bit() &&
> -        !isa<GlobalAddressSDNode>(Callee) &&
> -        !isa<ExternalSymbolSDNode>(Callee)) {
> +        ((!isa<GlobalAddressSDNode>(Callee) &&
> +          !isa<ExternalSymbolSDNode>(Callee)) ||
> +         getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
>        unsigned NumInRegs = 0;
> +      // In PIC we need an extra register to formulate the address computation
> +      // for the callee.
> +      unsigned MaxInRegs =
> +          (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
> +
>        for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
>          CCValAssign &VA = ArgLocs[i];
>          if (!VA.isRegLoc())
> @@ -2984,7 +2990,7 @@ X86TargetLowering::IsEligibleForTailCall
>          switch (Reg) {
>          default: break;
>          case X86::EAX: case X86::EDX: case X86::ECX:
> -          if (++NumInRegs == 3)
> +          if (++NumInRegs == MaxInRegs)
>              return false;
>            break;
>          }
>
>
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