[llvm] r182396 - [mips] Add instruction selection patterns for blez and bgez.

[Akira Hatanaka]

Author: ahatanak
Date: Tue May 21 12:13:47 2013
New Revision: 182396

URL: http://llvm.org/viewvc/llvm-project?rev=182396&view=rev
Log:
[mips] Add instruction selection patterns for blez and bgez.


Added:
    llvm/trunk/test/CodeGen/Mips/blez_bgez.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/CodeGen/Mips/brdelayslot.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=182396&r1=182395&r2=182396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue May 21 12:13:47 2013
@@ -294,6 +294,11 @@ def : WrapperPat<tglobaltlsaddr, DADDiu,
 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
 
+def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
+              (BLEZ64 i64:$lhs, bb:$dst)>;
+def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
+              (BGEZ64 i64:$lhs, bb:$dst)>;
+
 // setcc patterns
 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=182396&r1=182395&r2=182396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue May 21 12:13:47 2013
@@ -1277,6 +1277,11 @@ def : MipsPat<(brcond RC:$cond, bb:$dst)
 
 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
 
+def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
+              (BLEZ i32:$lhs, bb:$dst)>;
+def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
+              (BGEZ i32:$lhs, bb:$dst)>;
+
 // setcc patterns
 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
                      Instruction SLTuOp, Register ZEROReg> {

Added: llvm/trunk/test/CodeGen/Mips/blez_bgez.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/blez_bgez.ll?rev=182396&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/blez_bgez.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/blez_bgez.ll Tue May 21 12:13:47 2013
@@ -0,0 +1,36 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+
+; CHECK: test_blez:
+; CHECK: blez ${{[0-9]+}}, $BB
+
+define void @test_blez(i32 %a) {
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+declare void @foo1()
+
+; CHECK: test_bgez:
+; CHECK: bgez ${{[0-9]+}}, $BB
+
+define void @test_bgez(i32 %a) {
+entry:
+  %cmp = icmp slt i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}

Modified: llvm/trunk/test/CodeGen/Mips/brdelayslot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/brdelayslot.ll?rev=182396&r1=182395&r2=182396&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/brdelayslot.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/brdelayslot.ll Tue May 21 12:13:47 2013
@@ -131,7 +131,7 @@ declare void @foo11()
 ; filled.
 ;
 ; SUCCBB:      succbbs_loop1:
-; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
+; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
 ; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
 ; SUCCBB-NEXT: addiu