[llvm] r182228 - Implement spill and fill of I64Regs.

[Jakob Stoklund Olesen]

Author: stoklund
Date: Sun May 19 19:53:25 2013
New Revision: 182228

URL: http://llvm.org/viewvc/llvm-project?rev=182228&view=rev
Log:
Implement spill and fill of I64Regs.

Modified:
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
    llvm/trunk/test/CodeGen/SPARC/64bit.ll

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=182228&r1=182227&r2=182228&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Sun May 19 19:53:25 2013
@@ -40,6 +40,7 @@ SparcInstrInfo::SparcInstrInfo(SparcSubt
 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                              int &FrameIndex) const {
   if (MI->getOpcode() == SP::LDri ||
+      MI->getOpcode() == SP::LDXri ||
       MI->getOpcode() == SP::LDFri ||
       MI->getOpcode() == SP::LDDFri) {
     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
@@ -59,6 +60,7 @@ unsigned SparcInstrInfo::isLoadFromStack
 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
                                             int &FrameIndex) const {
   if (MI->getOpcode() == SP::STri ||
+      MI->getOpcode() == SP::STXri ||
       MI->getOpcode() == SP::STFri ||
       MI->getOpcode() == SP::STDFri) {
     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
@@ -303,7 +305,10 @@ storeRegToStackSlot(MachineBasicBlock &M
   if (I != MBB.end()) DL = I->getDebugLoc();
 
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  if (RC == &SP::IntRegsRegClass)
+  if (RC == &SP::I64RegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
+      .addReg(SrcReg, getKillRegState(isKill));
+  else if (RC == &SP::IntRegsRegClass)
     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
       .addReg(SrcReg, getKillRegState(isKill));
   else if (RC == &SP::FPRegsRegClass)
@@ -324,7 +329,9 @@ loadRegFromStackSlot(MachineBasicBlock &
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (RC == &SP::IntRegsRegClass)
+  if (RC == &SP::I64RegsRegClass)
+    BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0);
+  else if (RC == &SP::IntRegsRegClass)
     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
   else if (RC == &SP::FPRegsRegClass)
     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);

Modified: llvm/trunk/test/CodeGen/SPARC/64bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/64bit.ll?rev=182228&r1=182227&r2=182228&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/64bit.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/64bit.ll Sun May 19 19:53:25 2013
@@ -201,3 +201,11 @@ define i32 @expand_setcc(i64 %a) {
   %RV = sub i32 1, %cast2
   ret i32 %RV
 }
+
+; CHECK: spill_i64
+; CHECK: stx
+; CHECK: ldx
+define i64 @spill_i64(i64 %x) {
+  call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"()
+  ret i64 %x
+}