[llvm] r182221 - Implement SPselectfcc for i64 operands.
Jakob Stoklund Olesen
stoklund at 2pi.dk
Sun May 19 13:20:54 PDT 2013
Author: stoklund
Date: Sun May 19 15:20:54 2013
New Revision: 182221
URL: http://llvm.org/viewvc/llvm-project?rev=182221&view=rev
Log:
Implement SPselectfcc for i64 operands.
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).
Modified:
llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/test/CodeGen/SPARC/64cond.ll
Modified: llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td?rev=182221&r1=182220&r2=182221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td Sun May 19 15:20:54 2013
@@ -322,7 +322,7 @@ def MOVXCCri : Pseudo<(outs IntRegs:$rd)
(ins i32imm:$i, IntRegs:$f, CCOp:$cond),
"mov$cond %xcc, $i, $rd",
[(set i32:$rd,
- (SPselecticc simm11:$i, i32:$f, imm:$cond))]>;
+ (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
} // Uses, Constraints
def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
@@ -330,4 +330,9 @@ def : Pat<(SPselectxcc i64:$t, i64:$f, i
def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
(MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
+def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
+ (MOVFCCrr $t, $f, imm:$cond)>;
+def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
+ (MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
+
} // Predicates = [Is64Bit]
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=182221&r1=182220&r2=182221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sun May 19 15:20:54 2013
@@ -698,52 +698,51 @@ let Defs = [FCC] in {
//===----------------------------------------------------------------------===//
// V9 Conditional Moves.
-let Predicates = [HasV9], Constraints = "$T = $dst" in {
+let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
let Uses = [ICC] in {
def MOVICCrr
- : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
- "mov$cc %icc, $F, $dst",
- [(set i32:$dst, (SPselecticc i32:$F, i32:$T, imm:$cc))]>;
+ : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
+ "mov$cc %icc, $rs2, $rd",
+ [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>;
def MOVICCri
- : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
- "mov$cc %icc, $F, $dst",
- [(set i32:$dst, (SPselecticc simm11:$F, i32:$T, imm:$cc))]>;
+ : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
+ "mov$cc %icc, $i, $rd",
+ [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>;
}
let Uses = [FCC] in {
def MOVFCCrr
- : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
- "mov$cc %fcc0, $F, $dst",
- [(set i32:$dst, (SPselectfcc i32:$F, i32:$T, imm:$cc))]>;
+ : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
+ "mov$cc %fcc0, $rs2, $rd",
+ [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>;
def MOVFCCri
- : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
- "mov$cc %fcc0, $F, $dst",
- [(set i32:$dst, (SPselectfcc simm11:$F, i32:$T, imm:$cc))]>;
+ : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
+ "mov$cc %fcc0, $i, $rd",
+ [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>;
}
let Uses = [ICC] in {
def FMOVS_ICC
- : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
- "fmovs$cc %icc, $F, $dst",
- [(set f32:$dst,
- (SPselecticc f32:$F, f32:$T, imm:$cc))]>;
+ : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
+ "fmovs$cc %icc, $rs2, $rd",
+ [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>;
def FMOVD_ICC
- : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
- "fmovd$cc %icc, $F, $dst",
- [(set f64:$dst, (SPselecticc f64:$F, f64:$T, imm:$cc))]>;
+ : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
+ "fmovd$cc %icc, $rs2, $rd",
+ [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>;
}
let Uses = [FCC] in {
def FMOVS_FCC
- : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
- "fmovs$cc %fcc0, $F, $dst",
- [(set f32:$dst, (SPselectfcc f32:$F, f32:$T, imm:$cc))]>;
+ : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
+ "fmovs$cc %fcc0, $rs2, $rd",
+ [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>;
def FMOVD_FCC
- : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
- "fmovd$cc %fcc0, $F, $dst",
- [(set f64:$dst, (SPselectfcc f64:$F, f64:$T, imm:$cc))]>;
+ : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
+ "fmovd$cc %fcc0, $rs2, $rd",
+ [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>;
}
}
Modified: llvm/trunk/test/CodeGen/SPARC/64cond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/64cond.ll?rev=182221&r1=182220&r2=182221&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/64cond.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/64cond.ll Sun May 19 15:20:54 2013
@@ -54,3 +54,14 @@ entry:
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
+
+; CHECK: selecti64_fcc
+; CHECK: fcmps %f1, %f3
+; CHECK: movul %fcc0, %i2, %i3
+; CHECK: or %g0, %i3, %i0
+define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
+entry:
+ %tobool = fcmp ult float %x, %y
+ %rv = select i1 %tobool, i64 %a, i64 %b
+ ret i64 %rv
+}
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