[llvm] r182092 - [PowerPC] Merge/rename PPC fixup types
Ulrich Weigand
ulrich.weigand at de.ibm.com
Fri May 17 05:37:22 PDT 2013
Author: uweigand
Date: Fri May 17 07:37:21 2013
New Revision: 182092
URL: http://llvm.org/viewvc/llvm-project?rev=182092&view=rev
Log:
[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.
This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)
No change in code generation expected.
Modified:
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=182092&r1=182091&r2=182092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Fri May 17 07:37:21 2013
@@ -37,13 +37,9 @@ static uint64_t adjustFixupValue(unsigne
return Value & 0xfffc;
case PPC::fixup_ppc_br24:
return Value & 0x3fffffc;
-#if 0
- case PPC::fixup_ppc_hi16:
-#endif
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
+ case PPC::fixup_ppc_half16:
return Value & 0xffff;
- case PPC::fixup_ppc_lo16_ds:
+ case PPC::fixup_ppc_half16ds:
return Value & 0xfffc;
}
}
@@ -55,9 +51,8 @@ static unsigned getFixupKindNumBytes(uns
case FK_Data_1:
return 1;
case FK_Data_2:
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
- case PPC::fixup_ppc_lo16_ds:
+ case PPC::fixup_ppc_half16:
+ case PPC::fixup_ppc_half16ds:
return 2;
case FK_Data_4:
case PPC::fixup_ppc_brcond14:
@@ -98,9 +93,8 @@ public:
// name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_lo16", 0, 16, 0 },
- { "fixup_ppc_ha16", 0, 16, 0 },
- { "fixup_ppc_lo16_ds", 0, 14, 0 },
+ { "fixup_ppc_half16", 0, 16, 0 },
+ { "fixup_ppc_half16ds", 0, 14, 0 },
{ "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=182092&r1=182091&r2=182092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Fri May 17 07:37:21 2013
@@ -81,8 +81,7 @@ unsigned PPCELFObjectWriter::getRelocTyp
case PPC::fixup_ppc_brcond14:
Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
break;
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
+ case PPC::fixup_ppc_half16:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_PPC_TPREL16_HA:
@@ -134,7 +133,7 @@ unsigned PPCELFObjectWriter::getRelocTyp
break;
}
break;
- case PPC::fixup_ppc_lo16_ds:
+ case PPC::fixup_ppc_half16ds:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_None:
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h?rev=182092&r1=182091&r2=182092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h Fri May 17 07:37:21 2013
@@ -25,17 +25,13 @@ enum Fixups {
/// branches.
fixup_ppc_brcond14,
- /// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs
- /// like 'li'.
- fixup_ppc_lo16,
+ /// fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo)
+ /// or ha16(_foo) for instrs like 'li' or 'addis'.
+ fixup_ppc_half16,
- /// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs
- /// like 'lis'.
- fixup_ppc_ha16,
-
- /// fixup_ppc_lo16_ds - A 14-bit fixup corresponding to lo16(_foo) with
+ /// fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with
/// implied 2 zero bits for instrs like 'std'.
- fixup_ppc_lo16_ds,
+ fixup_ppc_half16ds,
/// fixup_ppc_tlsreg - Insert thread-pointer register number.
fixup_ppc_tlsreg,
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=182092&r1=182091&r2=182092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Fri May 17 07:37:21 2013
@@ -143,7 +143,7 @@ unsigned PPCMCCodeEmitter::getHA16Encodi
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_ha16));
+ (MCFixupKind)PPC::fixup_ppc_half16));
return 0;
}
@@ -154,7 +154,7 @@ unsigned PPCMCCodeEmitter::getLO16Encodi
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo16));
+ (MCFixupKind)PPC::fixup_ppc_half16));
return 0;
}
@@ -171,7 +171,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncod
// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo16));
+ (MCFixupKind)PPC::fixup_ppc_half16));
return RegBits;
}
@@ -189,7 +189,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEnco
// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo16_ds));
+ (MCFixupKind)PPC::fixup_ppc_half16ds));
return RegBits;
}
Modified: llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-fixups.s?rev=182092&r1=182091&r2=182092&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-fixups.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-fixups.s Fri May 17 07:37:21 2013
@@ -8,77 +8,77 @@
# FIXME: .TOC. at tocbase
# CHECK: li 3, target at l # encoding: [0x38,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
li 3, target at l
# CHECK: addis 3, 3, target at ha # encoding: [0x3c,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
addis 3, 3, target at ha
# CHECK: lis 3, target at ha # encoding: [0x3c,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
lis 3, target at ha
# CHECK: addi 4, 3, target at l # encoding: [0x38,0x83,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
addi 4, 3, target at l
# CHECK: li 3, target at ha # encoding: [0x38,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
li 3, target at ha
# CHECK: lis 3, target at l # encoding: [0x3c,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
lis 3, target at l
# CHECK: li 3, target # encoding: [0x38,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
li 3, target
# CHECK: lis 3, target # encoding: [0x3c,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
lis 3, target
# CHECK: lwz 1, target at l(3) # encoding: [0x80,0x23,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
lwz 1, target at l(3)
# CHECK: ld 1, target at l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16_ds
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
ld 1, target at l(3)
# CHECK: ld 1, target at toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at toc, kind: fixup_ppc_lo16_ds
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
ld 1, target at toc(2)
# CHECK: addis 3, 2, target at toc@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
addis 3, 2, target at toc@ha
# CHECK: addi 4, 3, target at toc@l # encoding: [0x38,0x83,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
addi 4, 3, target at toc@l
# CHECK: lwz 1, target at toc@l(3) # encoding: [0x80,0x23,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
lwz 1, target at toc@l(3)
# CHECK: ld 1, target at toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16_ds
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
ld 1, target at toc@l(3)
@@ -86,55 +86,55 @@
# CHECK: addis 3, 2, target at tprel@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
addis 3, 2, target at tprel@ha
# CHECK: addi 3, 3, target at tprel@l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
addi 3, 3, target at tprel@l
# CHECK: addis 3, 2, target at dtprel@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
addis 3, 2, target at dtprel@ha
# CHECK: addi 3, 3, target at dtprel@l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
addi 3, 3, target at dtprel@l
# CHECK: addis 3, 2, target at got@tprel at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
addis 3, 2, target at got@tprel at ha
# CHECK: ld 1, target at got@tprel at l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at l, kind: fixup_ppc_lo16_ds
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at l, kind: fixup_ppc_half16ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
ld 1, target at got@tprel at l(3)
# CHECK: addis 3, 2, target at got@tlsgd at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
addis 3, 2, target at got@tlsgd at ha
# CHECK: addi 3, 3, target at got@tlsgd at l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
addi 3, 3, target at got@tlsgd at l
# CHECK: addis 3, 2, target at got@tlsld at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at ha, kind: fixup_ppc_ha16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at ha, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
addis 3, 2, target at got@tlsld at ha
# CHECK: addi 3, 3, target at got@tlsld at l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at l, kind: fixup_ppc_lo16
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at l, kind: fixup_ppc_half16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
addi 3, 3, target at got@tlsld at l
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